hw/omap.h

   1 /*
   2  * Texas Instruments OMAP processors.
   3  *
   4  * Copyright (C) 2006-2008 Andrzej Zaborowski  <balrog@zabor.org>
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License as
   8  * published by the Free Software Foundation; either version 2 or
   9  * (at your option) version 3 of the License.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License along
  17  * with this program; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19 #ifndef hw_omap_h
  20 # define hw_omap_h              "omap.h"
  21
  22 # define OMAP_EMIFS_BASE        0x00000000
  23 # define OMAP2_Q0_BASE          0x00000000
  24 # define OMAP_CS0_BASE          0x00000000
  25 # define OMAP_CS1_BASE          0x04000000
  26 # define OMAP_CS2_BASE          0x08000000
  27 # define OMAP_CS3_BASE          0x0c000000
  28 # define OMAP_EMIFF_BASE        0x10000000
  29 # define OMAP_IMIF_BASE         0x20000000
  30 # define OMAP_LOCALBUS_BASE     0x30000000
  31 # define OMAP2_Q1_BASE          0x40000000
  32 # define OMAP2_L4_BASE          0x48000000
  33 # define OMAP2_SRAM_BASE        0x40200000
  34 # define OMAP2_L3_BASE          0x68000000
  35 # define OMAP2_Q2_BASE          0x80000000
  36 # define OMAP2_Q3_BASE          0xc0000000
  37 # define OMAP_MPUI_BASE         0xe1000000
  38
  39 # define OMAP730_SRAM_SIZE      0x00032000
  40 # define OMAP15XX_SRAM_SIZE     0x00030000
  41 # define OMAP16XX_SRAM_SIZE     0x00004000
  42 # define OMAP1611_SRAM_SIZE     0x0003e800
  43 # define OMAP242X_SRAM_SIZE     0x000a0000
  44 # define OMAP243X_SRAM_SIZE     0x00010000
  45 # define OMAP_CS0_SIZE          0x04000000
  46 # define OMAP_CS1_SIZE          0x04000000
  47 # define OMAP_CS2_SIZE          0x04000000
  48 # define OMAP_CS3_SIZE          0x04000000
  49
  50 /* omap_clk.c */
  51 struct omap_mpu_state_s;
  52 typedef struct clk *omap_clk;
  53 omap_clk omap_findclk(struct omap_mpu_state_s *mpu, const char *name);
  54 void omap_clk_init(struct omap_mpu_state_s *mpu);
  55 void omap_clk_adduser(struct clk *clk, qemu_irq user);
  56 void omap_clk_get(omap_clk clk);
  57 void omap_clk_put(omap_clk clk);
  58 void omap_clk_onoff(omap_clk clk, int on);
  59 void omap_clk_canidle(omap_clk clk, int can);
  60 void omap_clk_setrate(omap_clk clk, int divide, int multiply);
  61 int64_t omap_clk_getrate(omap_clk clk);
  62 void omap_clk_reparent(omap_clk clk, omap_clk parent);
  63
  64 /* OMAP2 l4 Interconnect */
  65 struct omap_l4_s;
  66 struct omap_l4_region_s {
  67     target_phys_addr_t offset;
  68     size_t size;
  69     int access;
  70 };
  71 struct omap_l4_agent_info_s {
  72     int ta;
  73     int region;
  74     int regions;
  75     int ta_region;
  76 };
  77 struct omap_target_agent_s {
  78     struct omap_l4_s *bus;
  79     int regions;
  80     const struct omap_l4_region_s *start;
  81     target_phys_addr_t base;
  82     uint32_t component;
  83     uint32_t control;
  84     uint32_t status;
  85 };
  86 struct omap_l4_s *omap_l4_init(target_phys_addr_t base, int ta_num);
  87
  88 struct omap_target_agent_s;
  89 struct omap_target_agent_s *omap_l4ta_get(
  90     struct omap_l4_s *bus,
  91     const struct omap_l4_region_s *regions,
  92     const struct omap_l4_agent_info_s *agents,
  93     int cs);
  94 target_phys_addr_t omap_l4_attach(struct omap_target_agent_s *ta, int region,
  95                 int iotype);
  96 target_phys_addr_t omap_l4_region_base(struct omap_target_agent_s *ta,
  97                                        int region);
  98 int l4_register_io_memory(CPUReadMemoryFunc * const *mem_read,
  99                 CPUWriteMemoryFunc * const *mem_write, void *opaque);
 100
 101 /* OMAP interrupt controller */
 102 struct omap_intr_handler_s;
 103 struct omap_intr_handler_s *omap_inth_init(target_phys_addr_t base,
 104                 unsigned long size, unsigned char nbanks, qemu_irq **pins,
 105                 qemu_irq parent_irq, qemu_irq parent_fiq, omap_clk clk);
 106 struct omap_intr_handler_s *omap2_inth_init(target_phys_addr_t base,
 107                 int size, int nbanks, qemu_irq **pins,
 108                 qemu_irq parent_irq, qemu_irq parent_fiq,
 109                 omap_clk fclk, omap_clk iclk);
 110 void omap_inth_reset(struct omap_intr_handler_s *s);
 111 qemu_irq omap_inth_get_pin(struct omap_intr_handler_s *s, int n);
 112
 113 /* OMAP2 SDRAM controller */
 114 struct omap_sdrc_s;
 115 struct omap_sdrc_s *omap_sdrc_init(target_phys_addr_t base);
 116 void omap_sdrc_reset(struct omap_sdrc_s *s);
 117
 118 /* OMAP2 general purpose memory controller */
 119 struct omap_gpmc_s;
 120 struct omap_gpmc_s *omap_gpmc_init(target_phys_addr_t base, qemu_irq irq);
 121 void omap_gpmc_reset(struct omap_gpmc_s *s);
 122 void omap_gpmc_attach(struct omap_gpmc_s *s, int cs, int iomemtype,
 123                 void (*base_upd)(void *opaque, target_phys_addr_t new),
 124                 void (*unmap)(void *opaque), void *opaque);
 125
 126 /*
 127  * Common IRQ numbers for level 1 interrupt handler
 128  * See /usr/include/asm-arm/arch-omap/irqs.h in Linux.
 129  */
 130 # define OMAP_INT_CAMERA                1
 131 # define OMAP_INT_FIQ                   3
 132 # define OMAP_INT_RTDX                  6
 133 # define OMAP_INT_DSP_MMU_ABORT         7
 134 # define OMAP_INT_HOST                  8
 135 # define OMAP_INT_ABORT                 9
 136 # define OMAP_INT_BRIDGE_PRIV           13
 137 # define OMAP_INT_GPIO_BANK1            14
 138 # define OMAP_INT_UART3                 15
 139 # define OMAP_INT_TIMER3                16
 140 # define OMAP_INT_DMA_CH0_6             19
 141 # define OMAP_INT_DMA_CH1_7             20
 142 # define OMAP_INT_DMA_CH2_8             21
 143 # define OMAP_INT_DMA_CH3               22
 144 # define OMAP_INT_DMA_CH4               23
 145 # define OMAP_INT_DMA_CH5               24
 146 # define OMAP_INT_DMA_LCD               25
 147 # define OMAP_INT_TIMER1                26
 148 # define OMAP_INT_WD_TIMER              27
 149 # define OMAP_INT_BRIDGE_PUB            28
 150 # define OMAP_INT_TIMER2                30
 151 # define OMAP_INT_LCD_CTRL              31
 152
 153 /*
 154  * Common OMAP-15xx IRQ numbers for level 1 interrupt handler
 155  */
 156 # define OMAP_INT_15XX_IH2_IRQ          0
 157 # define OMAP_INT_15XX_LB_MMU           17
 158 # define OMAP_INT_15XX_LOCAL_BUS        29
 159
 160 /*
 161  * OMAP-1510 specific IRQ numbers for level 1 interrupt handler
 162  */
 163 # define OMAP_INT_1510_SPI_TX           4
 164 # define OMAP_INT_1510_SPI_RX           5
 165 # define OMAP_INT_1510_DSP_MAILBOX1     10
 166 # define OMAP_INT_1510_DSP_MAILBOX2     11
 167
 168 /*
 169  * OMAP-310 specific IRQ numbers for level 1 interrupt handler
 170  */
 171 # define OMAP_INT_310_McBSP2_TX         4
 172 # define OMAP_INT_310_McBSP2_RX         5
 173 # define OMAP_INT_310_HSB_MAILBOX1      12
 174 # define OMAP_INT_310_HSAB_MMU          18
 175
 176 /*
 177  * OMAP-1610 specific IRQ numbers for level 1 interrupt handler
 178  */
 179 # define OMAP_INT_1610_IH2_IRQ          0
 180 # define OMAP_INT_1610_IH2_FIQ          2
 181 # define OMAP_INT_1610_McBSP2_TX        4
 182 # define OMAP_INT_1610_McBSP2_RX        5
 183 # define OMAP_INT_1610_DSP_MAILBOX1     10
 184 # define OMAP_INT_1610_DSP_MAILBOX2     11
 185 # define OMAP_INT_1610_LCD_LINE         12
 186 # define OMAP_INT_1610_GPTIMER1         17
 187 # define OMAP_INT_1610_GPTIMER2         18
 188 # define OMAP_INT_1610_SSR_FIFO_0       29
 189
 190 /*
 191  * OMAP-730 specific IRQ numbers for level 1 interrupt handler
 192  */
 193 # define OMAP_INT_730_IH2_FIQ           0
 194 # define OMAP_INT_730_IH2_IRQ           1
 195 # define OMAP_INT_730_USB_NON_ISO       2
 196 # define OMAP_INT_730_USB_ISO           3
 197 # define OMAP_INT_730_ICR               4
 198 # define OMAP_INT_730_EAC               5
 199 # define OMAP_INT_730_GPIO_BANK1        6
 200 # define OMAP_INT_730_GPIO_BANK2        7
 201 # define OMAP_INT_730_GPIO_BANK3        8
 202 # define OMAP_INT_730_McBSP2TX          10
 203 # define OMAP_INT_730_McBSP2RX          11
 204 # define OMAP_INT_730_McBSP2RX_OVF      12
 205 # define OMAP_INT_730_LCD_LINE          14
 206 # define OMAP_INT_730_GSM_PROTECT       15
 207 # define OMAP_INT_730_TIMER3            16
 208 # define OMAP_INT_730_GPIO_BANK5        17
 209 # define OMAP_INT_730_GPIO_BANK6        18
 210 # define OMAP_INT_730_SPGIO_WR          29
 211
 212 /*
 213  * Common IRQ numbers for level 2 interrupt handler
 214  */
 215 # define OMAP_INT_KEYBOARD              1
 216 # define OMAP_INT_uWireTX               2
 217 # define OMAP_INT_uWireRX               3
 218 # define OMAP_INT_I2C                   4
 219 # define OMAP_INT_MPUIO                 5
 220 # define OMAP_INT_USB_HHC_1             6
 221 # define OMAP_INT_McBSP3TX              10
 222 # define OMAP_INT_McBSP3RX              11
 223 # define OMAP_INT_McBSP1TX              12
 224 # define OMAP_INT_McBSP1RX              13
 225 # define OMAP_INT_UART1                 14
 226 # define OMAP_INT_UART2                 15
 227 # define OMAP_INT_USB_W2FC              20
 228 # define OMAP_INT_1WIRE                 21
 229 # define OMAP_INT_OS_TIMER              22
 230 # define OMAP_INT_OQN                   23
 231 # define OMAP_INT_GAUGE_32K             24
 232 # define OMAP_INT_RTC_TIMER             25
 233 # define OMAP_INT_RTC_ALARM             26
 234 # define OMAP_INT_DSP_MMU               28
 235
 236 /*
 237  * OMAP-1510 specific IRQ numbers for level 2 interrupt handler
 238  */
 239 # define OMAP_INT_1510_BT_MCSI1TX       16
 240 # define OMAP_INT_1510_BT_MCSI1RX       17
 241 # define OMAP_INT_1510_SoSSI_MATCH      19
 242 # define OMAP_INT_1510_MEM_STICK        27
 243 # define OMAP_INT_1510_COM_SPI_RO       31
 244
 245 /*
 246  * OMAP-310 specific IRQ numbers for level 2 interrupt handler
 247  */
 248 # define OMAP_INT_310_FAC               0
 249 # define OMAP_INT_310_USB_HHC_2         7
 250 # define OMAP_INT_310_MCSI1_FE          16
 251 # define OMAP_INT_310_MCSI2_FE          17
 252 # define OMAP_INT_310_USB_W2FC_ISO      29
 253 # define OMAP_INT_310_USB_W2FC_NON_ISO  30
 254 # define OMAP_INT_310_McBSP2RX_OF       31
 255
 256 /*
 257  * OMAP-1610 specific IRQ numbers for level 2 interrupt handler
 258  */
 259 # define OMAP_INT_1610_FAC              0
 260 # define OMAP_INT_1610_USB_HHC_2        7
 261 # define OMAP_INT_1610_USB_OTG          8
 262 # define OMAP_INT_1610_SoSSI            9
 263 # define OMAP_INT_1610_BT_MCSI1TX       16
 264 # define OMAP_INT_1610_BT_MCSI1RX       17
 265 # define OMAP_INT_1610_SoSSI_MATCH      19
 266 # define OMAP_INT_1610_MEM_STICK        27
 267 # define OMAP_INT_1610_McBSP2RX_OF      31
 268 # define OMAP_INT_1610_STI              32
 269 # define OMAP_INT_1610_STI_WAKEUP       33
 270 # define OMAP_INT_1610_GPTIMER3         34
 271 # define OMAP_INT_1610_GPTIMER4         35
 272 # define OMAP_INT_1610_GPTIMER5         36
 273 # define OMAP_INT_1610_GPTIMER6         37
 274 # define OMAP_INT_1610_GPTIMER7         38
 275 # define OMAP_INT_1610_GPTIMER8         39
 276 # define OMAP_INT_1610_GPIO_BANK2       40
 277 # define OMAP_INT_1610_GPIO_BANK3       41
 278 # define OMAP_INT_1610_MMC2             42
 279 # define OMAP_INT_1610_CF               43
 280 # define OMAP_INT_1610_WAKE_UP_REQ      46
 281 # define OMAP_INT_1610_GPIO_BANK4       48
 282 # define OMAP_INT_1610_SPI              49
 283 # define OMAP_INT_1610_DMA_CH6          53
 284 # define OMAP_INT_1610_DMA_CH7          54
 285 # define OMAP_INT_1610_DMA_CH8          55
 286 # define OMAP_INT_1610_DMA_CH9          56
 287 # define OMAP_INT_1610_DMA_CH10         57
 288 # define OMAP_INT_1610_DMA_CH11         58
 289 # define OMAP_INT_1610_DMA_CH12         59
 290 # define OMAP_INT_1610_DMA_CH13         60
 291 # define OMAP_INT_1610_DMA_CH14         61
 292 # define OMAP_INT_1610_DMA_CH15         62
 293 # define OMAP_INT_1610_NAND             63
 294
 295 /*
 296  * OMAP-730 specific IRQ numbers for level 2 interrupt handler
 297  */
 298 # define OMAP_INT_730_HW_ERRORS         0
 299 # define OMAP_INT_730_NFIQ_PWR_FAIL     1
 300 # define OMAP_INT_730_CFCD              2
 301 # define OMAP_INT_730_CFIREQ            3
 302 # define OMAP_INT_730_I2C               4
 303 # define OMAP_INT_730_PCC               5
 304 # define OMAP_INT_730_MPU_EXT_NIRQ      6
 305 # define OMAP_INT_730_SPI_100K_1        7
 306 # define OMAP_INT_730_SYREN_SPI         8
 307 # define OMAP_INT_730_VLYNQ             9
 308 # define OMAP_INT_730_GPIO_BANK4        10
 309 # define OMAP_INT_730_McBSP1TX          11
 310 # define OMAP_INT_730_McBSP1RX          12
 311 # define OMAP_INT_730_McBSP1RX_OF       13
 312 # define OMAP_INT_730_UART_MODEM_IRDA_2 14
 313 # define OMAP_INT_730_UART_MODEM_1      15
 314 # define OMAP_INT_730_MCSI              16
 315 # define OMAP_INT_730_uWireTX           17
 316 # define OMAP_INT_730_uWireRX           18
 317 # define OMAP_INT_730_SMC_CD            19
 318 # define OMAP_INT_730_SMC_IREQ          20
 319 # define OMAP_INT_730_HDQ_1WIRE         21
 320 # define OMAP_INT_730_TIMER32K          22
 321 # define OMAP_INT_730_MMC_SDIO          23
 322 # define OMAP_INT_730_UPLD              24
 323 # define OMAP_INT_730_USB_HHC_1         27
 324 # define OMAP_INT_730_USB_HHC_2         28
 325 # define OMAP_INT_730_USB_GENI          29
 326 # define OMAP_INT_730_USB_OTG           30
 327 # define OMAP_INT_730_CAMERA_IF         31
 328 # define OMAP_INT_730_RNG               32
 329 # define OMAP_INT_730_DUAL_MODE_TIMER   33
 330 # define OMAP_INT_730_DBB_RF_EN         34
 331 # define OMAP_INT_730_MPUIO_KEYPAD      35
 332 # define OMAP_INT_730_SHA1_MD5          36
 333 # define OMAP_INT_730_SPI_100K_2        37
 334 # define OMAP_INT_730_RNG_IDLE          38
 335 # define OMAP_INT_730_MPUIO             39
 336 # define OMAP_INT_730_LLPC_LCD_CTRL_OFF 40
 337 # define OMAP_INT_730_LLPC_OE_FALLING   41
 338 # define OMAP_INT_730_LLPC_OE_RISING    42
 339 # define OMAP_INT_730_LLPC_VSYNC        43
 340 # define OMAP_INT_730_WAKE_UP_REQ       46
 341 # define OMAP_INT_730_DMA_CH6           53
 342 # define OMAP_INT_730_DMA_CH7           54
 343 # define OMAP_INT_730_DMA_CH8           55
 344 # define OMAP_INT_730_DMA_CH9           56
 345 # define OMAP_INT_730_DMA_CH10          57
 346 # define OMAP_INT_730_DMA_CH11          58
 347 # define OMAP_INT_730_DMA_CH12          59
 348 # define OMAP_INT_730_DMA_CH13          60
 349 # define OMAP_INT_730_DMA_CH14          61
 350 # define OMAP_INT_730_DMA_CH15          62
 351 # define OMAP_INT_730_NAND              63
 352
 353 /*
 354  * OMAP-24xx common IRQ numbers
 355  */
 356 # define OMAP_INT_24XX_STI              4
 357 # define OMAP_INT_24XX_SYS_NIRQ         7
 358 # define OMAP_INT_24XX_L3_IRQ           10
 359 # define OMAP_INT_24XX_PRCM_MPU_IRQ     11
 360 # define OMAP_INT_24XX_SDMA_IRQ0        12
 361 # define OMAP_INT_24XX_SDMA_IRQ1        13
 362 # define OMAP_INT_24XX_SDMA_IRQ2        14
 363 # define OMAP_INT_24XX_SDMA_IRQ3        15
 364 # define OMAP_INT_243X_MCBSP2_IRQ       16
 365 # define OMAP_INT_243X_MCBSP3_IRQ       17
 366 # define OMAP_INT_243X_MCBSP4_IRQ       18
 367 # define OMAP_INT_243X_MCBSP5_IRQ       19
 368 # define OMAP_INT_24XX_GPMC_IRQ         20
 369 # define OMAP_INT_24XX_GUFFAW_IRQ       21
 370 # define OMAP_INT_24XX_IVA_IRQ          22
 371 # define OMAP_INT_24XX_EAC_IRQ          23
 372 # define OMAP_INT_24XX_CAM_IRQ          24
 373 # define OMAP_INT_24XX_DSS_IRQ          25
 374 # define OMAP_INT_24XX_MAIL_U0_MPU      26
 375 # define OMAP_INT_24XX_DSP_UMA          27
 376 # define OMAP_INT_24XX_DSP_MMU          28
 377 # define OMAP_INT_24XX_GPIO_BANK1       29
 378 # define OMAP_INT_24XX_GPIO_BANK2       30
 379 # define OMAP_INT_24XX_GPIO_BANK3       31
 380 # define OMAP_INT_24XX_GPIO_BANK4       32
 381 # define OMAP_INT_243X_GPIO_BANK5       33
 382 # define OMAP_INT_24XX_MAIL_U3_MPU      34
 383 # define OMAP_INT_24XX_WDT3             35
 384 # define OMAP_INT_24XX_WDT4             36
 385 # define OMAP_INT_24XX_GPTIMER1         37
 386 # define OMAP_INT_24XX_GPTIMER2         38
 387 # define OMAP_INT_24XX_GPTIMER3         39
 388 # define OMAP_INT_24XX_GPTIMER4         40
 389 # define OMAP_INT_24XX_GPTIMER5         41
 390 # define OMAP_INT_24XX_GPTIMER6         42
 391 # define OMAP_INT_24XX_GPTIMER7         43
 392 # define OMAP_INT_24XX_GPTIMER8         44
 393 # define OMAP_INT_24XX_GPTIMER9         45
 394 # define OMAP_INT_24XX_GPTIMER10        46
 395 # define OMAP_INT_24XX_GPTIMER11        47
 396 # define OMAP_INT_24XX_GPTIMER12        48
 397 # define OMAP_INT_24XX_PKA_IRQ          50
 398 # define OMAP_INT_24XX_SHA1MD5_IRQ      51
 399 # define OMAP_INT_24XX_RNG_IRQ          52
 400 # define OMAP_INT_24XX_MG_IRQ           53
 401 # define OMAP_INT_24XX_I2C1_IRQ         56
 402 # define OMAP_INT_24XX_I2C2_IRQ         57
 403 # define OMAP_INT_24XX_MCBSP1_IRQ_TX    59
 404 # define OMAP_INT_24XX_MCBSP1_IRQ_RX    60
 405 # define OMAP_INT_24XX_MCBSP2_IRQ_TX    62
 406 # define OMAP_INT_24XX_MCBSP2_IRQ_RX    63
 407 # define OMAP_INT_243X_MCBSP1_IRQ       64
 408 # define OMAP_INT_24XX_MCSPI1_IRQ       65
 409 # define OMAP_INT_24XX_MCSPI2_IRQ       66
 410 # define OMAP_INT_24XX_SSI1_IRQ0        67
 411 # define OMAP_INT_24XX_SSI1_IRQ1        68
 412 # define OMAP_INT_24XX_SSI2_IRQ0        69
 413 # define OMAP_INT_24XX_SSI2_IRQ1        70
 414 # define OMAP_INT_24XX_SSI_GDD_IRQ      71
 415 # define OMAP_INT_24XX_UART1_IRQ        72
 416 # define OMAP_INT_24XX_UART2_IRQ        73
 417 # define OMAP_INT_24XX_UART3_IRQ        74
 418 # define OMAP_INT_24XX_USB_IRQ_GEN      75
 419 # define OMAP_INT_24XX_USB_IRQ_NISO     76
 420 # define OMAP_INT_24XX_USB_IRQ_ISO      77
 421 # define OMAP_INT_24XX_USB_IRQ_HGEN     78
 422 # define OMAP_INT_24XX_USB_IRQ_HSOF     79
 423 # define OMAP_INT_24XX_USB_IRQ_OTG      80
 424 # define OMAP_INT_24XX_VLYNQ_IRQ        81
 425 # define OMAP_INT_24XX_MMC_IRQ          83
 426 # define OMAP_INT_24XX_MS_IRQ           84
 427 # define OMAP_INT_24XX_FAC_IRQ          85
 428 # define OMAP_INT_24XX_MCSPI3_IRQ       91
 429 # define OMAP_INT_243X_HS_USB_MC        92
 430 # define OMAP_INT_243X_HS_USB_DMA       93
 431 # define OMAP_INT_243X_CARKIT           94
 432 # define OMAP_INT_34XX_GPTIMER12        95
 433
 434 /* omap_dma.c */
 435 enum omap_dma_model {
 436     omap_dma_3_0,
 437     omap_dma_3_1,
 438     omap_dma_3_2,
 439     omap_dma_4,
 440 };
 441
 442 struct soc_dma_s;
 443 struct soc_dma_s *omap_dma_init(target_phys_addr_t base, qemu_irq *irqs,
 444                 qemu_irq lcd_irq, struct omap_mpu_state_s *mpu, omap_clk clk,
 445                 enum omap_dma_model model);
 446 struct soc_dma_s *omap_dma4_init(target_phys_addr_t base, qemu_irq *irqs,
 447                 struct omap_mpu_state_s *mpu, int fifo,
 448                 int chans, omap_clk iclk, omap_clk fclk);
 449 void omap_dma_reset(struct soc_dma_s *s);
 450
 451 struct dma_irq_map {
 452     int ih;
 453     int intr;
 454 };
 455
 456 /* Only used in OMAP DMA 3.x gigacells */
 457 enum omap_dma_port {
 458     emiff = 0,
 459     emifs,
 460     imif,       /* omap16xx: ocp_t1 */
 461     tipb,
 462     local,      /* omap16xx: ocp_t2 */
 463     tipb_mpui,
 464     __omap_dma_port_last,
 465 };
 466
 467 typedef enum {
 468     constant = 0,
 469     post_incremented,
 470     single_index,
 471     double_index,
 472 } omap_dma_addressing_t;
 473
 474 /* Only used in OMAP DMA 3.x gigacells */
 475 struct omap_dma_lcd_channel_s {
 476     enum omap_dma_port src;
 477     target_phys_addr_t src_f1_top;
 478     target_phys_addr_t src_f1_bottom;
 479     target_phys_addr_t src_f2_top;
 480     target_phys_addr_t src_f2_bottom;
 481
 482     /* Used in OMAP DMA 3.2 gigacell */
 483     unsigned char brust_f1;
 484     unsigned char pack_f1;
 485     unsigned char data_type_f1;
 486     unsigned char brust_f2;
 487     unsigned char pack_f2;
 488     unsigned char data_type_f2;
 489     unsigned char end_prog;
 490     unsigned char repeat;
 491     unsigned char auto_init;
 492     unsigned char priority;
 493     unsigned char fs;
 494     unsigned char running;
 495     unsigned char bs;
 496     unsigned char omap_3_1_compatible_disable;
 497     unsigned char dst;
 498     unsigned char lch_type;
 499     int16_t element_index_f1;
 500     int16_t element_index_f2;
 501     int32_t frame_index_f1;
 502     int32_t frame_index_f2;
 503     uint16_t elements_f1;
 504     uint16_t frames_f1;
 505     uint16_t elements_f2;
 506     uint16_t frames_f2;
 507     omap_dma_addressing_t mode_f1;
 508     omap_dma_addressing_t mode_f2;
 509
 510     /* Destination port is fixed.  */
 511     int interrupts;
 512     int condition;
 513     int dual;
 514
 515     int current_frame;
 516     target_phys_addr_t phys_framebuffer[2];
 517     qemu_irq irq;
 518     struct omap_mpu_state_s *mpu;
 519 } *omap_dma_get_lcdch(struct soc_dma_s *s);
 520
 521 /*
 522  * DMA request numbers for OMAP1
 523  * See /usr/include/asm-arm/arch-omap/dma.h in Linux.
 524  */
 525 # define OMAP_DMA_NO_DEVICE             0
 526 # define OMAP_DMA_MCSI1_TX              1
 527 # define OMAP_DMA_MCSI1_RX              2
 528 # define OMAP_DMA_I2C_RX                3
 529 # define OMAP_DMA_I2C_TX                4
 530 # define OMAP_DMA_EXT_NDMA_REQ0         5
 531 # define OMAP_DMA_EXT_NDMA_REQ1         6
 532 # define OMAP_DMA_UWIRE_TX              7
 533 # define OMAP_DMA_MCBSP1_TX             8
 534 # define OMAP_DMA_MCBSP1_RX             9
 535 # define OMAP_DMA_MCBSP3_TX             10
 536 # define OMAP_DMA_MCBSP3_RX             11
 537 # define OMAP_DMA_UART1_TX              12
 538 # define OMAP_DMA_UART1_RX              13
 539 # define OMAP_DMA_UART2_TX              14
 540 # define OMAP_DMA_UART2_RX              15
 541 # define OMAP_DMA_MCBSP2_TX             16
 542 # define OMAP_DMA_MCBSP2_RX             17
 543 # define OMAP_DMA_UART3_TX              18
 544 # define OMAP_DMA_UART3_RX              19
 545 # define OMAP_DMA_CAMERA_IF_RX          20
 546 # define OMAP_DMA_MMC_TX                21
 547 # define OMAP_DMA_MMC_RX                22
 548 # define OMAP_DMA_NAND                  23      /* Not in OMAP310 */
 549 # define OMAP_DMA_IRQ_LCD_LINE          24      /* Not in OMAP310 */
 550 # define OMAP_DMA_MEMORY_STICK          25      /* Not in OMAP310 */
 551 # define OMAP_DMA_USB_W2FC_RX0          26
 552 # define OMAP_DMA_USB_W2FC_RX1          27
 553 # define OMAP_DMA_USB_W2FC_RX2          28
 554 # define OMAP_DMA_USB_W2FC_TX0          29
 555 # define OMAP_DMA_USB_W2FC_TX1          30
 556 # define OMAP_DMA_USB_W2FC_TX2          31
 557
 558 /* These are only for 1610 */
 559 # define OMAP_DMA_CRYPTO_DES_IN         32
 560 # define OMAP_DMA_SPI_TX                33
 561 # define OMAP_DMA_SPI_RX                34
 562 # define OMAP_DMA_CRYPTO_HASH           35
 563 # define OMAP_DMA_CCP_ATTN              36
 564 # define OMAP_DMA_CCP_FIFO_NOT_EMPTY    37
 565 # define OMAP_DMA_CMT_APE_TX_CHAN_0     38
 566 # define OMAP_DMA_CMT_APE_RV_CHAN_0     39
 567 # define OMAP_DMA_CMT_APE_TX_CHAN_1     40
 568 # define OMAP_DMA_CMT_APE_RV_CHAN_1     41
 569 # define OMAP_DMA_CMT_APE_TX_CHAN_2     42
 570 # define OMAP_DMA_CMT_APE_RV_CHAN_2     43
 571 # define OMAP_DMA_CMT_APE_TX_CHAN_3     44
 572 # define OMAP_DMA_CMT_APE_RV_CHAN_3     45
 573 # define OMAP_DMA_CMT_APE_TX_CHAN_4     46
 574 # define OMAP_DMA_CMT_APE_RV_CHAN_4     47
 575 # define OMAP_DMA_CMT_APE_TX_CHAN_5     48
 576 # define OMAP_DMA_CMT_APE_RV_CHAN_5     49
 577 # define OMAP_DMA_CMT_APE_TX_CHAN_6     50
 578 # define OMAP_DMA_CMT_APE_RV_CHAN_6     51
 579 # define OMAP_DMA_CMT_APE_TX_CHAN_7     52
 580 # define OMAP_DMA_CMT_APE_RV_CHAN_7     53
 581 # define OMAP_DMA_MMC2_TX               54
 582 # define OMAP_DMA_MMC2_RX               55
 583 # define OMAP_DMA_CRYPTO_DES_OUT        56
 584
 585 /*
 586  * DMA request numbers for the OMAP2
 587  */
 588 # define OMAP24XX_DMA_NO_DEVICE         0
 589 # define OMAP24XX_DMA_XTI_DMA           1       /* Not in OMAP2420 */
 590 # define OMAP24XX_DMA_EXT_DMAREQ0       2
 591 # define OMAP24XX_DMA_EXT_DMAREQ1       3
 592 # define OMAP24XX_DMA_GPMC              4
 593 # define OMAP24XX_DMA_GFX               5       /* Not in OMAP2420 */
 594 # define OMAP24XX_DMA_DSS               6
 595 # define OMAP24XX_DMA_VLYNQ_TX          7       /* Not in OMAP2420 */
 596 # define OMAP24XX_DMA_CWT               8       /* Not in OMAP2420 */
 597 # define OMAP24XX_DMA_AES_TX            9       /* Not in OMAP2420 */
 598 # define OMAP24XX_DMA_AES_RX            10      /* Not in OMAP2420 */
 599 # define OMAP24XX_DMA_DES_TX            11      /* Not in OMAP2420 */
 600 # define OMAP24XX_DMA_DES_RX            12      /* Not in OMAP2420 */
 601 # define OMAP24XX_DMA_SHA1MD5_RX        13      /* Not in OMAP2420 */
 602 # define OMAP24XX_DMA_EXT_DMAREQ2       14
 603 # define OMAP24XX_DMA_EXT_DMAREQ3       15
 604 # define OMAP24XX_DMA_EXT_DMAREQ4       16
 605 # define OMAP24XX_DMA_EAC_AC_RD         17
 606 # define OMAP24XX_DMA_EAC_AC_WR         18
 607 # define OMAP24XX_DMA_EAC_MD_UL_RD      19
 608 # define OMAP24XX_DMA_EAC_MD_UL_WR      20
 609 # define OMAP24XX_DMA_EAC_MD_DL_RD      21
 610 # define OMAP24XX_DMA_EAC_MD_DL_WR      22
 611 # define OMAP24XX_DMA_EAC_BT_UL_RD      23
 612 # define OMAP24XX_DMA_EAC_BT_UL_WR      24
 613 # define OMAP24XX_DMA_EAC_BT_DL_RD      25
 614 # define OMAP24XX_DMA_EAC_BT_DL_WR      26
 615 # define OMAP24XX_DMA_I2C1_TX           27
 616 # define OMAP24XX_DMA_I2C1_RX           28
 617 # define OMAP24XX_DMA_I2C2_TX           29
 618 # define OMAP24XX_DMA_I2C2_RX           30
 619 # define OMAP24XX_DMA_MCBSP1_TX         31
 620 # define OMAP24XX_DMA_MCBSP1_RX         32
 621 # define OMAP24XX_DMA_MCBSP2_TX         33
 622 # define OMAP24XX_DMA_MCBSP2_RX         34
 623 # define OMAP24XX_DMA_SPI1_TX0          35
 624 # define OMAP24XX_DMA_SPI1_RX0          36
 625 # define OMAP24XX_DMA_SPI1_TX1          37
 626 # define OMAP24XX_DMA_SPI1_RX1          38
 627 # define OMAP24XX_DMA_SPI1_TX2          39
 628 # define OMAP24XX_DMA_SPI1_RX2          40
 629 # define OMAP24XX_DMA_SPI1_TX3          41
 630 # define OMAP24XX_DMA_SPI1_RX3          42
 631 # define OMAP24XX_DMA_SPI2_TX0          43
 632 # define OMAP24XX_DMA_SPI2_RX0          44
 633 # define OMAP24XX_DMA_SPI2_TX1          45
 634 # define OMAP24XX_DMA_SPI2_RX1          46
 635
 636 # define OMAP24XX_DMA_UART1_TX          49
 637 # define OMAP24XX_DMA_UART1_RX          50
 638 # define OMAP24XX_DMA_UART2_TX          51
 639 # define OMAP24XX_DMA_UART2_RX          52
 640 # define OMAP24XX_DMA_UART3_TX          53
 641 # define OMAP24XX_DMA_UART3_RX          54
 642 # define OMAP24XX_DMA_USB_W2FC_TX0      55
 643 # define OMAP24XX_DMA_USB_W2FC_RX0      56
 644 # define OMAP24XX_DMA_USB_W2FC_TX1      57
 645 # define OMAP24XX_DMA_USB_W2FC_RX1      58
 646 # define OMAP24XX_DMA_USB_W2FC_TX2      59
 647 # define OMAP24XX_DMA_USB_W2FC_RX2      60
 648 # define OMAP24XX_DMA_MMC1_TX           61
 649 # define OMAP24XX_DMA_MMC1_RX           62
 650 # define OMAP24XX_DMA_MS                63      /* Not in OMAP2420 */
 651 # define OMAP24XX_DMA_EXT_DMAREQ5       64
 652
 653 /* omap[123].c */
 654 /* OMAP2 gp timer */
 655 struct omap_gp_timer_s;
 656 struct omap_gp_timer_s *omap_gp_timer_init(struct omap_target_agent_s *ta,
 657                 qemu_irq irq, omap_clk fclk, omap_clk iclk);
 658 void omap_gp_timer_reset(struct omap_gp_timer_s *s);
 659
 660 /* OMAP2 sysctimer */
 661 struct omap_synctimer_s;
 662 struct omap_synctimer_s *omap_synctimer_init(struct omap_target_agent_s *ta,
 663                 struct omap_mpu_state_s *mpu, omap_clk fclk, omap_clk iclk);
 664 void omap_synctimer_reset(struct omap_synctimer_s *s);
 665
 666 struct omap_uart_s;
 667 struct omap_uart_s *omap_uart_init(target_phys_addr_t base,
 668                 qemu_irq irq, omap_clk fclk, omap_clk iclk,
 669                 qemu_irq txdma, qemu_irq rxdma,
 670                 const char *label, CharDriverState *chr);
 671 struct omap_uart_s *omap2_uart_init(struct omap_target_agent_s *ta,
 672                 qemu_irq irq, omap_clk fclk, omap_clk iclk,
 673                 qemu_irq txdma, qemu_irq rxdma,
 674                 const char *label, CharDriverState *chr);
 675 void omap_uart_reset(struct omap_uart_s *s);
 676 void omap_uart_attach(struct omap_uart_s *s, CharDriverState *chr);
 677
 678 struct omap_mpuio_s;
 679 struct omap_mpuio_s *omap_mpuio_init(target_phys_addr_t base,
 680                 qemu_irq kbd_int, qemu_irq gpio_int, qemu_irq wakeup,
 681                 omap_clk clk);
 682 qemu_irq *omap_mpuio_in_get(struct omap_mpuio_s *s);
 683 void omap_mpuio_out_set(struct omap_mpuio_s *s, int line, qemu_irq handler);
 684 void omap_mpuio_key(struct omap_mpuio_s *s, int row, int col, int down);
 685
 686 struct uWireSlave {
 687     uint16_t (*receive)(void *opaque);
 688     void (*send)(void *opaque, uint16_t data);
 689     void *opaque;
 690 };
 691 struct omap_uwire_s;
 692 struct omap_uwire_s *omap_uwire_init(target_phys_addr_t base,
 693                 qemu_irq *irq, qemu_irq dma, omap_clk clk);
 694 void omap_uwire_attach(struct omap_uwire_s *s,
 695                 uWireSlave *slave, int chipselect);
 696
 697 /* OMAP2 spi */
 698 struct omap_mcspi_s;
 699 struct omap_mcspi_s *omap_mcspi_init(struct omap_target_agent_s *ta, int chnum,
 700                 qemu_irq irq, qemu_irq *drq, omap_clk fclk, omap_clk iclk);
 701 void omap_mcspi_attach(struct omap_mcspi_s *s,
 702                 uint32_t (*txrx)(void *opaque, uint32_t, int), void *opaque,
 703                 int chipselect);
 704 void omap_mcspi_reset(struct omap_mcspi_s *s);
 705
 706 struct I2SCodec {
 707     void *opaque;
 708
 709     /* The CPU can call this if it is generating the clock signal on the
 710      * i2s port.  The CODEC can ignore it if it is set up as a clock
 711      * master and generates its own clock.  */
 712     void (*set_rate)(void *opaque, int in, int out);
 713
 714     void (*tx_swallow)(void *opaque);
 715     qemu_irq rx_swallow;
 716     qemu_irq tx_start;
 717
 718     int tx_rate;
 719     int cts;
 720     int rx_rate;
 721     int rts;
 722
 723     struct i2s_fifo_s {
 724         uint8_t *fifo;
 725         int len;
 726         int start;
 727         int size;
 728     } in, out;
 729 };
 730 struct omap_mcbsp_s;
 731 struct omap_mcbsp_s *omap_mcbsp_init(target_phys_addr_t base,
 732                 qemu_irq *irq, qemu_irq *dma, omap_clk clk);
 733 void omap_mcbsp_i2s_attach(struct omap_mcbsp_s *s, I2SCodec *slave);
 734
 735 void omap_tap_init(struct omap_target_agent_s *ta,
 736                 struct omap_mpu_state_s *mpu);
 737
 738 /* omap_lcdc.c */
 739 struct omap_lcd_panel_s;
 740 void omap_lcdc_reset(struct omap_lcd_panel_s *s);
 741 struct omap_lcd_panel_s *omap_lcdc_init(target_phys_addr_t base, qemu_irq irq,
 742                 struct omap_dma_lcd_channel_s *dma,
 743                 ram_addr_t imif_base, ram_addr_t emiff_base, omap_clk clk);
 744
 745 /* omap_dss.c */
 746 struct rfbi_chip_s {
 747     void *opaque;
 748     void (*write)(void *opaque, int dc, uint16_t value);
 749     void (*block)(void *opaque, int dc, void *buf, size_t len, int pitch);
 750     uint16_t (*read)(void *opaque, int dc);
 751 };
 752 struct omap_dss_s;
 753 void omap_dss_reset(struct omap_dss_s *s);
 754 struct omap_dss_s *omap_dss_init(struct omap_target_agent_s *ta,
 755                 target_phys_addr_t l3_base,
 756                 qemu_irq irq, qemu_irq drq,
 757                 omap_clk fck1, omap_clk fck2, omap_clk ck54m,
 758                 omap_clk ick1, omap_clk ick2);
 759 void omap_rfbi_attach(struct omap_dss_s *s, int cs, struct rfbi_chip_s *chip);
 760
 761 /* omap_mmc.c */
 762 struct omap_mmc_s;
 763 struct omap_mmc_s *omap_mmc_init(target_phys_addr_t base,
 764                 BlockDriverState *bd,
 765                 qemu_irq irq, qemu_irq dma[], omap_clk clk);
 766 struct omap_mmc_s *omap2_mmc_init(struct omap_target_agent_s *ta,
 767                 BlockDriverState *bd, qemu_irq irq, qemu_irq dma[],
 768                 omap_clk fclk, omap_clk iclk);
 769 void omap_mmc_reset(struct omap_mmc_s *s);
 770 void omap_mmc_handlers(struct omap_mmc_s *s, qemu_irq ro, qemu_irq cover);
 771 void omap_mmc_enable(struct omap_mmc_s *s, int enable);
 772
 773 /* omap_i2c.c */
 774 struct omap_i2c_s;
 775 struct omap_i2c_s *omap_i2c_init(target_phys_addr_t base,
 776                 qemu_irq irq, qemu_irq *dma, omap_clk clk);
 777 struct omap_i2c_s *omap2_i2c_init(struct omap_target_agent_s *ta,
 778                 qemu_irq irq, qemu_irq *dma, omap_clk fclk, omap_clk iclk);
 779 void omap_i2c_reset(struct omap_i2c_s *s);
 780 i2c_bus *omap_i2c_bus(struct omap_i2c_s *s);
 781
 782 # define cpu_is_omap310(cpu)            (cpu->mpu_model == omap310)
 783 # define cpu_is_omap1510(cpu)           (cpu->mpu_model == omap1510)
 784 # define cpu_is_omap1610(cpu)           (cpu->mpu_model == omap1610)
 785 # define cpu_is_omap1710(cpu)           (cpu->mpu_model == omap1710)
 786 # define cpu_is_omap2410(cpu)           (cpu->mpu_model == omap2410)
 787 # define cpu_is_omap2420(cpu)           (cpu->mpu_model == omap2420)
 788 # define cpu_is_omap2430(cpu)           (cpu->mpu_model == omap2430)
 789 # define cpu_is_omap3430(cpu)           (cpu->mpu_model == omap3430)
 790
 791 # define cpu_is_omap15xx(cpu)           \
 792         (cpu_is_omap310(cpu) || cpu_is_omap1510(cpu))
 793 # define cpu_is_omap16xx(cpu)           \
 794         (cpu_is_omap1610(cpu) || cpu_is_omap1710(cpu))
 795 # define cpu_is_omap24xx(cpu)           \
 796         (cpu_is_omap2410(cpu) || cpu_is_omap2420(cpu) || cpu_is_omap2430(cpu))
 797
 798 # define cpu_class_omap1(cpu)           \
 799         (cpu_is_omap15xx(cpu) || cpu_is_omap16xx(cpu))
 800 # define cpu_class_omap2(cpu)           cpu_is_omap24xx(cpu)
 801 # define cpu_class_omap3(cpu)           cpu_is_omap3430(cpu)
 802
 803 struct omap_mpu_state_s {
 804     enum omap_mpu_model {
 805         omap310,
 806         omap1510,
 807         omap1610,
 808         omap1710,
 809         omap2410,
 810         omap2420,
 811         omap2422,
 812         omap2423,
 813         omap2430,
 814         omap3430,
 815     } mpu_model;
 816
 817     CPUState *env;
 818
 819     qemu_irq *irq[2];
 820     qemu_irq *drq;
 821
 822     qemu_irq wakeup;
 823
 824     struct omap_dma_port_if_s {
 825         uint32_t (*read[3])(struct omap_mpu_state_s *s,
 826                         target_phys_addr_t offset);
 827         void (*write[3])(struct omap_mpu_state_s *s,
 828                         target_phys_addr_t offset, uint32_t value);
 829         int (*addr_valid)(struct omap_mpu_state_s *s,
 830                         target_phys_addr_t addr);
 831     } port[__omap_dma_port_last];
 832
 833     unsigned long sdram_size;
 834     unsigned long sram_size;
 835
 836     /* MPUI-TIPB peripherals */
 837     struct omap_uart_s *uart[3];
 838
 839     DeviceState *gpio;
 840
 841     struct omap_mcbsp_s *mcbsp1;
 842     struct omap_mcbsp_s *mcbsp3;
 843
 844     /* MPU public TIPB peripherals */
 845     struct omap_32khz_timer_s *os_timer;
 846
 847     struct omap_mmc_s *mmc;
 848
 849     struct omap_mpuio_s *mpuio;
 850
 851     struct omap_uwire_s *microwire;
 852
 853     struct {
 854         uint8_t output;
 855         uint8_t level;
 856         uint8_t enable;
 857         int clk;
 858     } pwl;
 859
 860     struct {
 861         uint8_t frc;
 862         uint8_t vrc;
 863         uint8_t gcr;
 864         omap_clk clk;
 865     } pwt;
 866
 867     struct omap_i2c_s *i2c[2];
 868
 869     struct omap_rtc_s *rtc;
 870
 871     struct omap_mcbsp_s *mcbsp2;
 872
 873     struct omap_lpg_s *led[2];
 874
 875     /* MPU private TIPB peripherals */
 876     struct omap_intr_handler_s *ih[2];
 877
 878     struct soc_dma_s *dma;
 879
 880     struct omap_mpu_timer_s *timer[3];
 881     struct omap_watchdog_timer_s *wdt;
 882
 883     struct omap_lcd_panel_s *lcd;
 884
 885     uint32_t ulpd_pm_regs[21];
 886     int64_t ulpd_gauge_start;
 887
 888     uint32_t func_mux_ctrl[14];
 889     uint32_t comp_mode_ctrl[1];
 890     uint32_t pull_dwn_ctrl[4];
 891     uint32_t gate_inh_ctrl[1];
 892     uint32_t voltage_ctrl[1];
 893     uint32_t test_dbg_ctrl[1];
 894     uint32_t mod_conf_ctrl[1];
 895     int compat1509;
 896
 897     uint32_t mpui_ctrl;
 898
 899     struct omap_tipb_bridge_s *private_tipb;
 900     struct omap_tipb_bridge_s *public_tipb;
 901
 902     uint32_t tcmi_regs[17];
 903
 904     struct dpll_ctl_s {
 905         uint16_t mode;
 906         omap_clk dpll;
 907     } dpll[3];
 908
 909     omap_clk clks;
 910     struct {
 911         int cold_start;
 912         int clocking_scheme;
 913         uint16_t arm_ckctl;
 914         uint16_t arm_idlect1;
 915         uint16_t arm_idlect2;
 916         uint16_t arm_ewupct;
 917         uint16_t arm_rstct1;
 918         uint16_t arm_rstct2;
 919         uint16_t arm_ckout1;
 920         int dpll1_mode;
 921         uint16_t dsp_idlect1;
 922         uint16_t dsp_idlect2;
 923         uint16_t dsp_rstct2;
 924     } clkm;
 925
 926     /* OMAP2-only peripherals */
 927     struct omap_l4_s *l4;
 928
 929     struct omap_gp_timer_s *gptimer[12];
 930     struct omap_synctimer_s *synctimer;
 931
 932     struct omap_prcm_s *prcm;
 933     struct omap_sdrc_s *sdrc;
 934     struct omap_gpmc_s *gpmc;
 935     struct omap_sysctl_s *sysc;
 936
 937     struct omap_mcspi_s *mcspi[2];
 938
 939     struct omap_dss_s *dss;
 940
 941     struct omap_eac_s *eac;
 942 };
 943
 944 /* omap1.c */
 945 struct omap_mpu_state_s *omap310_mpu_init(unsigned long sdram_size,
 946                 const char *core);
 947
 948 /* omap2.c */
 949 struct omap_mpu_state_s *omap2420_mpu_init(unsigned long sdram_size,
 950                 const char *core);
 951
 952 # if TARGET_PHYS_ADDR_BITS == 32
 953 #  define OMAP_FMT_plx "%#08x"
 954 # elif TARGET_PHYS_ADDR_BITS == 64
 955 #  define OMAP_FMT_plx "%#08" PRIx64
 956 # else
 957 #  error TARGET_PHYS_ADDR_BITS undefined
 958 # endif
 959
 960 uint32_t omap_badwidth_read8(void *opaque, target_phys_addr_t addr);
 961 void omap_badwidth_write8(void *opaque, target_phys_addr_t addr,
 962                 uint32_t value);
 963 uint32_t omap_badwidth_read16(void *opaque, target_phys_addr_t addr);
 964 void omap_badwidth_write16(void *opaque, target_phys_addr_t addr,
 965                 uint32_t value);
 966 uint32_t omap_badwidth_read32(void *opaque, target_phys_addr_t addr);
 967 void omap_badwidth_write32(void *opaque, target_phys_addr_t addr,
 968                 uint32_t value);
 969
 970 void omap_mpu_wakeup(void *opaque, int irq, int req);
 971
 972 # define OMAP_BAD_REG(paddr)            \
 973         fprintf(stderr, "%s: Bad register " OMAP_FMT_plx "\n",  \
 974                         __FUNCTION__, paddr)
 975 # define OMAP_RO_REG(paddr)             \
 976         fprintf(stderr, "%s: Read-only register " OMAP_FMT_plx "\n",    \
 977                         __FUNCTION__, paddr)
 978
 979 /* OMAP-specific Linux bootloader tags for the ATAG_BOARD area
 980    (Board-specifc tags are not here)  */
 981 #define OMAP_TAG_CLOCK          0x4f01
 982 #define OMAP_TAG_MMC            0x4f02
 983 #define OMAP_TAG_SERIAL_CONSOLE 0x4f03
 984 #define OMAP_TAG_USB            0x4f04
 985 #define OMAP_TAG_LCD            0x4f05
 986 #define OMAP_TAG_GPIO_SWITCH    0x4f06
 987 #define OMAP_TAG_UART           0x4f07
 988 #define OMAP_TAG_FBMEM          0x4f08
 989 #define OMAP_TAG_STI_CONSOLE    0x4f09
 990 #define OMAP_TAG_CAMERA_SENSOR  0x4f0a
 991 #define OMAP_TAG_PARTITION      0x4f0b
 992 #define OMAP_TAG_TEA5761        0x4f10
 993 #define OMAP_TAG_TMP105         0x4f11
 994 #define OMAP_TAG_BOOT_REASON    0x4f80
 995 #define OMAP_TAG_FLASH_PART_STR 0x4f81
 996 #define OMAP_TAG_VERSION_STR    0x4f82
 997
 998 enum {
 999     OMAP_GPIOSW_TYPE_COVER      = 0 << 4,
1000     OMAP_GPIOSW_TYPE_CONNECTION = 1 << 4,
1001     OMAP_GPIOSW_TYPE_ACTIVITY   = 2 << 4,
1002 };
1003
1004 #define OMAP_GPIOSW_INVERTED    0x0001
1005 #define OMAP_GPIOSW_OUTPUT      0x0002
1006
1007 # define TCMI_VERBOSE                   1
1008 //# define MEM_VERBOSE                  1
1009
1010 # ifdef TCMI_VERBOSE
1011 #  define OMAP_8B_REG(paddr)            \
1012         fprintf(stderr, "%s: 8-bit register " OMAP_FMT_plx "\n",        \
1013                         __FUNCTION__, paddr)
1014 #  define OMAP_16B_REG(paddr)           \
1015         fprintf(stderr, "%s: 16-bit register " OMAP_FMT_plx "\n",       \
1016                         __FUNCTION__, paddr)
1017 #  define OMAP_32B_REG(paddr)           \
1018         fprintf(stderr, "%s: 32-bit register " OMAP_FMT_plx "\n",       \
1019                         __FUNCTION__, paddr)
1020 # else
1021 #  define OMAP_8B_REG(paddr)
1022 #  define OMAP_16B_REG(paddr)
1023 #  define OMAP_32B_REG(paddr)
1024 # endif
1025
1026 # define OMAP_MPUI_REG_MASK             0x000007ff
1027
1028 # ifdef MEM_VERBOSE
1029 struct io_fn {
1030     CPUReadMemoryFunc * const *mem_read;
1031     CPUWriteMemoryFunc * const *mem_write;
1032     void *opaque;
1033     int in;
1034 };
1035
1036 static uint32_t io_readb(void *opaque, target_phys_addr_t addr)
1037 {
1038     struct io_fn *s = opaque;
1039     uint32_t ret;
1040
1041     s->in ++;
1042     ret = s->mem_read[0](s->opaque, addr);
1043     s->in --;
1044     if (!s->in)
1045         fprintf(stderr, "%08x ---> %02x\n", (uint32_t) addr, ret);
1046     return ret;
1047 }
1048 static uint32_t io_readh(void *opaque, target_phys_addr_t addr)
1049 {
1050     struct io_fn *s = opaque;
1051     uint32_t ret;
1052
1053     s->in ++;
1054     ret = s->mem_read[1](s->opaque, addr);
1055     s->in --;
1056     if (!s->in)
1057         fprintf(stderr, "%08x ---> %04x\n", (uint32_t) addr, ret);
1058     return ret;
1059 }
1060 static uint32_t io_readw(void *opaque, target_phys_addr_t addr)
1061 {
1062     struct io_fn *s = opaque;
1063     uint32_t ret;
1064
1065     s->in ++;
1066     ret = s->mem_read[2](s->opaque, addr);
1067     s->in --;
1068     if (!s->in)
1069         fprintf(stderr, "%08x ---> %08x\n", (uint32_t) addr, ret);
1070     return ret;
1071 }
1072 static void io_writeb(void *opaque, target_phys_addr_t addr, uint32_t value)
1073 {
1074     struct io_fn *s = opaque;
1075
1076     if (!s->in)
1077         fprintf(stderr, "%08x <--- %02x\n", (uint32_t) addr, value);
1078     s->in ++;
1079     s->mem_write[0](s->opaque, addr, value);
1080     s->in --;
1081 }
1082 static void io_writeh(void *opaque, target_phys_addr_t addr, uint32_t value)
1083 {
1084     struct io_fn *s = opaque;
1085
1086     if (!s->in)
1087         fprintf(stderr, "%08x <--- %04x\n", (uint32_t) addr, value);
1088     s->in ++;
1089     s->mem_write[1](s->opaque, addr, value);
1090     s->in --;
1091 }
1092 static void io_writew(void *opaque, target_phys_addr_t addr, uint32_t value)
1093 {
1094     struct io_fn *s = opaque;
1095
1096     if (!s->in)
1097         fprintf(stderr, "%08x <--- %08x\n", (uint32_t) addr, value);
1098     s->in ++;
1099     s->mem_write[2](s->opaque, addr, value);
1100     s->in --;
1101 }
1102
1103 static CPUReadMemoryFunc * const io_readfn[] = { io_readb, io_readh, io_readw, };
1104 static CPUWriteMemoryFunc * const io_writefn[] = { io_writeb, io_writeh, io_writew, };
1105
1106 inline static int debug_register_io_memory(CPUReadMemoryFunc * const *mem_read,
1107                                            CPUWriteMemoryFunc * const *mem_write,
1108                                            void *opaque)
1109 {
1110     struct io_fn *s = qemu_malloc(sizeof(struct io_fn));
1111
1112     s->mem_read = mem_read;
1113     s->mem_write = mem_write;
1114     s->opaque = opaque;
1115     s->in = 0;
1116     return cpu_register_io_memory(io_readfn, io_writefn, s,
1117                                   DEVICE_NATIVE_ENDIAN);
1118 }
1119 #  define cpu_register_io_memory        debug_register_io_memory
1120 # endif
1121
1122 /* Define when we want to reduce the number of IO regions registered.  */
1123 /*# define L4_MUX_HACK*/
1124
1125 #endif /* hw_omap_h */