?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
fix event fallout in sh_serial.c
[qemu/aliguori.git] / hw / ppc405_uc.c
blob06a053bf07c284ae7c4455243d699ae7384058f3
1 /*
2 * QEMU PowerPC 405 embedded processors emulation
3 *
4 * Copyright (c) 2007 Jocelyn Mayer
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24 #include "hw.h"
25 #include "ppc.h"
26 #include "ppc405.h"
27 #include "pc.h"
28 #include "qemu-timer.h"
29 #include "sysemu.h"
30 #include "qemu-log.h"
31
32 #define DEBUG_OPBA
33 #define DEBUG_SDRAM
34 #define DEBUG_GPIO
35 #define DEBUG_SERIAL
36 #define DEBUG_OCM
37 //#define DEBUG_I2C
38 #define DEBUG_GPT
39 #define DEBUG_MAL
40 #define DEBUG_CLOCKS
41 //#define DEBUG_CLOCKS_LL
42
43 ram_addr_t ppc405_set_bootinfo (CPUState *env, ppc4xx_bd_info_t *bd,
44 uint32_t flags)
45 {
46 ram_addr_t bdloc;
47 int i, n;
48
49 /* We put the bd structure at the top of memory */
50 if (bd->bi_memsize >= 0x01000000UL)
51 bdloc = 0x01000000UL - sizeof(struct ppc4xx_bd_info_t);
52 else
53 bdloc = bd->bi_memsize - sizeof(struct ppc4xx_bd_info_t);
54 stl_be_phys(bdloc + 0x00, bd->bi_memstart);
55 stl_be_phys(bdloc + 0x04, bd->bi_memsize);
56 stl_be_phys(bdloc + 0x08, bd->bi_flashstart);
57 stl_be_phys(bdloc + 0x0C, bd->bi_flashsize);
58 stl_be_phys(bdloc + 0x10, bd->bi_flashoffset);
59 stl_be_phys(bdloc + 0x14, bd->bi_sramstart);
60 stl_be_phys(bdloc + 0x18, bd->bi_sramsize);
61 stl_be_phys(bdloc + 0x1C, bd->bi_bootflags);
62 stl_be_phys(bdloc + 0x20, bd->bi_ipaddr);
63 for (i = 0; i < 6; i++) {
64 stb_phys(bdloc + 0x24 + i, bd->bi_enetaddr[i]);
65 }
66 stw_be_phys(bdloc + 0x2A, bd->bi_ethspeed);
67 stl_be_phys(bdloc + 0x2C, bd->bi_intfreq);
68 stl_be_phys(bdloc + 0x30, bd->bi_busfreq);
69 stl_be_phys(bdloc + 0x34, bd->bi_baudrate);
70 for (i = 0; i < 4; i++) {
71 stb_phys(bdloc + 0x38 + i, bd->bi_s_version[i]);
72 }
73 for (i = 0; i < 32; i++) {
74 stb_phys(bdloc + 0x3C + i, bd->bi_r_version[i]);
75 }
76 stl_be_phys(bdloc + 0x5C, bd->bi_plb_busfreq);
77 stl_be_phys(bdloc + 0x60, bd->bi_pci_busfreq);
78 for (i = 0; i < 6; i++) {
79 stb_phys(bdloc + 0x64 + i, bd->bi_pci_enetaddr[i]);
80 }
81 n = 0x6A;
82 if (flags & 0x00000001) {
83 for (i = 0; i < 6; i++)
84 stb_phys(bdloc + n++, bd->bi_pci_enetaddr2[i]);
85 }
86 stl_be_phys(bdloc + n, bd->bi_opbfreq);
87 n += 4;
88 for (i = 0; i < 2; i++) {
89 stl_be_phys(bdloc + n, bd->bi_iic_fast[i]);
90 n += 4;
91 }
92
93 return bdloc;
94 }
95
96 /*****************************************************************************/
97 /* Shared peripherals */
98
99 /*****************************************************************************/
100 /* Peripheral local bus arbitrer */
101 enum {
102 PLB0_BESR = 0x084,
103 PLB0_BEAR = 0x086,
104 PLB0_ACR = 0x087,
105 };
106
107 typedef struct ppc4xx_plb_t ppc4xx_plb_t;
108 struct ppc4xx_plb_t {
109 uint32_t acr;
110 uint32_t bear;
111 uint32_t besr;
112 };
113
114 static uint32_t dcr_read_plb (void *opaque, int dcrn)
115 {
116 ppc4xx_plb_t *plb;
117 uint32_t ret;
118
119 plb = opaque;
120 switch (dcrn) {
121 case PLB0_ACR:
122 ret = plb->acr;
123 break;
124 case PLB0_BEAR:
125 ret = plb->bear;
126 break;
127 case PLB0_BESR:
128 ret = plb->besr;
129 break;
130 default:
131 /* Avoid gcc warning */
132 ret = 0;
133 break;
134 }
135
136 return ret;
137 }
138
139 static void dcr_write_plb (void *opaque, int dcrn, uint32_t val)
140 {
141 ppc4xx_plb_t *plb;
142
143 plb = opaque;
144 switch (dcrn) {
145 case PLB0_ACR:
146 /* We don't care about the actual parameters written as
147 * we don't manage any priorities on the bus
148 */
149 plb->acr = val & 0xF8000000;
150 break;
151 case PLB0_BEAR:
152 /* Read only */
153 break;
154 case PLB0_BESR:
155 /* Write-clear */
156 plb->besr &= ~val;
157 break;
158 }
159 }
160
161 static void ppc4xx_plb_reset (void *opaque)
162 {
163 ppc4xx_plb_t *plb;
164
165 plb = opaque;
166 plb->acr = 0x00000000;
167 plb->bear = 0x00000000;
168 plb->besr = 0x00000000;
169 }
170
171 static void ppc4xx_plb_init(CPUState *env)
172 {
173 ppc4xx_plb_t *plb;
174
175 plb = qemu_mallocz(sizeof(ppc4xx_plb_t));
176 ppc_dcr_register(env, PLB0_ACR, plb, &dcr_read_plb, &dcr_write_plb);
177 ppc_dcr_register(env, PLB0_BEAR, plb, &dcr_read_plb, &dcr_write_plb);
178 ppc_dcr_register(env, PLB0_BESR, plb, &dcr_read_plb, &dcr_write_plb);
179 qemu_register_reset(ppc4xx_plb_reset, plb);
180 }
181
182 /*****************************************************************************/
183 /* PLB to OPB bridge */
184 enum {
185 POB0_BESR0 = 0x0A0,
186 POB0_BESR1 = 0x0A2,
187 POB0_BEAR = 0x0A4,
188 };
189
190 typedef struct ppc4xx_pob_t ppc4xx_pob_t;
191 struct ppc4xx_pob_t {
192 uint32_t bear;
193 uint32_t besr[2];
194 };
195
196 static uint32_t dcr_read_pob (void *opaque, int dcrn)
197 {
198 ppc4xx_pob_t *pob;
199 uint32_t ret;
200
201 pob = opaque;
202 switch (dcrn) {
203 case POB0_BEAR:
204 ret = pob->bear;
205 break;
206 case POB0_BESR0:
207 case POB0_BESR1:
208 ret = pob->besr[dcrn - POB0_BESR0];
209 break;
210 default:
211 /* Avoid gcc warning */
212 ret = 0;
213 break;
214 }
215
216 return ret;
217 }
218
219 static void dcr_write_pob (void *opaque, int dcrn, uint32_t val)
220 {
221 ppc4xx_pob_t *pob;
222
223 pob = opaque;
224 switch (dcrn) {
225 case POB0_BEAR:
226 /* Read only */
227 break;
228 case POB0_BESR0:
229 case POB0_BESR1:
230 /* Write-clear */
231 pob->besr[dcrn - POB0_BESR0] &= ~val;
232 break;
233 }
234 }
235
236 static void ppc4xx_pob_reset (void *opaque)
237 {
238 ppc4xx_pob_t *pob;
239
240 pob = opaque;
241 /* No error */
242 pob->bear = 0x00000000;
243 pob->besr[0] = 0x0000000;
244 pob->besr[1] = 0x0000000;
245 }
246
247 static void ppc4xx_pob_init(CPUState *env)
248 {
249 ppc4xx_pob_t *pob;
250
251 pob = qemu_mallocz(sizeof(ppc4xx_pob_t));
252 ppc_dcr_register(env, POB0_BEAR, pob, &dcr_read_pob, &dcr_write_pob);
253 ppc_dcr_register(env, POB0_BESR0, pob, &dcr_read_pob, &dcr_write_pob);
254 ppc_dcr_register(env, POB0_BESR1, pob, &dcr_read_pob, &dcr_write_pob);
255 qemu_register_reset(ppc4xx_pob_reset, pob);
256 }
257
258 /*****************************************************************************/
259 /* OPB arbitrer */
260 typedef struct ppc4xx_opba_t ppc4xx_opba_t;
261 struct ppc4xx_opba_t {
262 uint8_t cr;
263 uint8_t pr;
264 };
265
266 static uint32_t opba_readb (void *opaque, target_phys_addr_t addr)
267 {
268 ppc4xx_opba_t *opba;
269 uint32_t ret;
270
271 #ifdef DEBUG_OPBA
272 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
273 #endif
274 opba = opaque;
275 switch (addr) {
276 case 0x00:
277 ret = opba->cr;
278 break;
279 case 0x01:
280 ret = opba->pr;
281 break;
282 default:
283 ret = 0x00;
284 break;
285 }
286
287 return ret;
288 }
289
290 static void opba_writeb (void *opaque,
291 target_phys_addr_t addr, uint32_t value)
292 {
293 ppc4xx_opba_t *opba;
294
295 #ifdef DEBUG_OPBA
296 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
297 value);
298 #endif
299 opba = opaque;
300 switch (addr) {
301 case 0x00:
302 opba->cr = value & 0xF8;
303 break;
304 case 0x01:
305 opba->pr = value & 0xFF;
306 break;
307 default:
308 break;
309 }
310 }
311
312 static uint32_t opba_readw (void *opaque, target_phys_addr_t addr)
313 {
314 uint32_t ret;
315
316 #ifdef DEBUG_OPBA
317 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
318 #endif
319 ret = opba_readb(opaque, addr) << 8;
320 ret |= opba_readb(opaque, addr + 1);
321
322 return ret;
323 }
324
325 static void opba_writew (void *opaque,
326 target_phys_addr_t addr, uint32_t value)
327 {
328 #ifdef DEBUG_OPBA
329 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
330 value);
331 #endif
332 opba_writeb(opaque, addr, value >> 8);
333 opba_writeb(opaque, addr + 1, value);
334 }
335
336 static uint32_t opba_readl (void *opaque, target_phys_addr_t addr)
337 {
338 uint32_t ret;
339
340 #ifdef DEBUG_OPBA
341 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
342 #endif
343 ret = opba_readb(opaque, addr) << 24;
344 ret |= opba_readb(opaque, addr + 1) << 16;
345
346 return ret;
347 }
348
349 static void opba_writel (void *opaque,
350 target_phys_addr_t addr, uint32_t value)
351 {
352 #ifdef DEBUG_OPBA
353 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
354 value);
355 #endif
356 opba_writeb(opaque, addr, value >> 24);
357 opba_writeb(opaque, addr + 1, value >> 16);
358 }
359
360 static CPUReadMemoryFunc * const opba_read[] = {
361 &opba_readb,
362 &opba_readw,
363 &opba_readl,
364 };
365
366 static CPUWriteMemoryFunc * const opba_write[] = {
367 &opba_writeb,
368 &opba_writew,
369 &opba_writel,
370 };
371
372 static void ppc4xx_opba_reset (void *opaque)
373 {
374 ppc4xx_opba_t *opba;
375
376 opba = opaque;
377 opba->cr = 0x00; /* No dynamic priorities - park disabled */
378 opba->pr = 0x11;
379 }
380
381 static void ppc4xx_opba_init(target_phys_addr_t base)
382 {
383 ppc4xx_opba_t *opba;
384 int io;
385
386 opba = qemu_mallocz(sizeof(ppc4xx_opba_t));
387 #ifdef DEBUG_OPBA
388 printf("%s: offset " TARGET_FMT_plx "\n", __func__, base);
389 #endif
390 io = cpu_register_io_memory(opba_read, opba_write, opba,
391 DEVICE_NATIVE_ENDIAN);
392 cpu_register_physical_memory(base, 0x002, io);
393 qemu_register_reset(ppc4xx_opba_reset, opba);
394 }
395
396 /*****************************************************************************/
397 /* Code decompression controller */
398 /* XXX: TODO */
399
400 /*****************************************************************************/
401 /* Peripheral controller */
402 typedef struct ppc4xx_ebc_t ppc4xx_ebc_t;
403 struct ppc4xx_ebc_t {
404 uint32_t addr;
405 uint32_t bcr[8];
406 uint32_t bap[8];
407 uint32_t bear;
408 uint32_t besr0;
409 uint32_t besr1;
410 uint32_t cfg;
411 };
412
413 enum {
414 EBC0_CFGADDR = 0x012,
415 EBC0_CFGDATA = 0x013,
416 };
417
418 static uint32_t dcr_read_ebc (void *opaque, int dcrn)
419 {
420 ppc4xx_ebc_t *ebc;
421 uint32_t ret;
422
423 ebc = opaque;
424 switch (dcrn) {
425 case EBC0_CFGADDR:
426 ret = ebc->addr;
427 break;
428 case EBC0_CFGDATA:
429 switch (ebc->addr) {
430 case 0x00: /* B0CR */
431 ret = ebc->bcr[0];
432 break;
433 case 0x01: /* B1CR */
434 ret = ebc->bcr[1];
435 break;
436 case 0x02: /* B2CR */
437 ret = ebc->bcr[2];
438 break;
439 case 0x03: /* B3CR */
440 ret = ebc->bcr[3];
441 break;
442 case 0x04: /* B4CR */
443 ret = ebc->bcr[4];
444 break;
445 case 0x05: /* B5CR */
446 ret = ebc->bcr[5];
447 break;
448 case 0x06: /* B6CR */
449 ret = ebc->bcr[6];
450 break;
451 case 0x07: /* B7CR */
452 ret = ebc->bcr[7];
453 break;
454 case 0x10: /* B0AP */
455 ret = ebc->bap[0];
456 break;
457 case 0x11: /* B1AP */
458 ret = ebc->bap[1];
459 break;
460 case 0x12: /* B2AP */
461 ret = ebc->bap[2];
462 break;
463 case 0x13: /* B3AP */
464 ret = ebc->bap[3];
465 break;
466 case 0x14: /* B4AP */
467 ret = ebc->bap[4];
468 break;
469 case 0x15: /* B5AP */
470 ret = ebc->bap[5];
471 break;
472 case 0x16: /* B6AP */
473 ret = ebc->bap[6];
474 break;
475 case 0x17: /* B7AP */
476 ret = ebc->bap[7];
477 break;
478 case 0x20: /* BEAR */
479 ret = ebc->bear;
480 break;
481 case 0x21: /* BESR0 */
482 ret = ebc->besr0;
483 break;
484 case 0x22: /* BESR1 */
485 ret = ebc->besr1;
486 break;
487 case 0x23: /* CFG */
488 ret = ebc->cfg;
489 break;
490 default:
491 ret = 0x00000000;
492 break;
493 }
494 break;
495 default:
496 ret = 0x00000000;
497 break;
498 }
499
500 return ret;
501 }
502
503 static void dcr_write_ebc (void *opaque, int dcrn, uint32_t val)
504 {
505 ppc4xx_ebc_t *ebc;
506
507 ebc = opaque;
508 switch (dcrn) {
509 case EBC0_CFGADDR:
510 ebc->addr = val;
511 break;
512 case EBC0_CFGDATA:
513 switch (ebc->addr) {
514 case 0x00: /* B0CR */
515 break;
516 case 0x01: /* B1CR */
517 break;
518 case 0x02: /* B2CR */
519 break;
520 case 0x03: /* B3CR */
521 break;
522 case 0x04: /* B4CR */
523 break;
524 case 0x05: /* B5CR */
525 break;
526 case 0x06: /* B6CR */
527 break;
528 case 0x07: /* B7CR */
529 break;
530 case 0x10: /* B0AP */
531 break;
532 case 0x11: /* B1AP */
533 break;
534 case 0x12: /* B2AP */
535 break;
536 case 0x13: /* B3AP */
537 break;
538 case 0x14: /* B4AP */
539 break;
540 case 0x15: /* B5AP */
541 break;
542 case 0x16: /* B6AP */
543 break;
544 case 0x17: /* B7AP */
545 break;
546 case 0x20: /* BEAR */
547 break;
548 case 0x21: /* BESR0 */
549 break;
550 case 0x22: /* BESR1 */
551 break;
552 case 0x23: /* CFG */
553 break;
554 default:
555 break;
556 }
557 break;
558 default:
559 break;
560 }
561 }
562
563 static void ebc_reset (void *opaque)
564 {
565 ppc4xx_ebc_t *ebc;
566 int i;
567
568 ebc = opaque;
569 ebc->addr = 0x00000000;
570 ebc->bap[0] = 0x7F8FFE80;
571 ebc->bcr[0] = 0xFFE28000;
572 for (i = 0; i < 8; i++) {
573 ebc->bap[i] = 0x00000000;
574 ebc->bcr[i] = 0x00000000;
575 }
576 ebc->besr0 = 0x00000000;
577 ebc->besr1 = 0x00000000;
578 ebc->cfg = 0x80400000;
579 }
580
581 static void ppc405_ebc_init(CPUState *env)
582 {
583 ppc4xx_ebc_t *ebc;
584
585 ebc = qemu_mallocz(sizeof(ppc4xx_ebc_t));
586 qemu_register_reset(&ebc_reset, ebc);
587 ppc_dcr_register(env, EBC0_CFGADDR,
588 ebc, &dcr_read_ebc, &dcr_write_ebc);
589 ppc_dcr_register(env, EBC0_CFGDATA,
590 ebc, &dcr_read_ebc, &dcr_write_ebc);
591 }
592
593 /*****************************************************************************/
594 /* DMA controller */
595 enum {
596 DMA0_CR0 = 0x100,
597 DMA0_CT0 = 0x101,
598 DMA0_DA0 = 0x102,
599 DMA0_SA0 = 0x103,
600 DMA0_SG0 = 0x104,
601 DMA0_CR1 = 0x108,
602 DMA0_CT1 = 0x109,
603 DMA0_DA1 = 0x10A,
604 DMA0_SA1 = 0x10B,
605 DMA0_SG1 = 0x10C,
606 DMA0_CR2 = 0x110,
607 DMA0_CT2 = 0x111,
608 DMA0_DA2 = 0x112,
609 DMA0_SA2 = 0x113,
610 DMA0_SG2 = 0x114,
611 DMA0_CR3 = 0x118,
612 DMA0_CT3 = 0x119,
613 DMA0_DA3 = 0x11A,
614 DMA0_SA3 = 0x11B,
615 DMA0_SG3 = 0x11C,
616 DMA0_SR = 0x120,
617 DMA0_SGC = 0x123,
618 DMA0_SLP = 0x125,
619 DMA0_POL = 0x126,
620 };
621
622 typedef struct ppc405_dma_t ppc405_dma_t;
623 struct ppc405_dma_t {
624 qemu_irq irqs[4];
625 uint32_t cr[4];
626 uint32_t ct[4];
627 uint32_t da[4];
628 uint32_t sa[4];
629 uint32_t sg[4];
630 uint32_t sr;
631 uint32_t sgc;
632 uint32_t slp;
633 uint32_t pol;
634 };
635
636 static uint32_t dcr_read_dma (void *opaque, int dcrn)
637 {
638 return 0;
639 }
640
641 static void dcr_write_dma (void *opaque, int dcrn, uint32_t val)
642 {
643 }
644
645 static void ppc405_dma_reset (void *opaque)
646 {
647 ppc405_dma_t *dma;
648 int i;
649
650 dma = opaque;
651 for (i = 0; i < 4; i++) {
652 dma->cr[i] = 0x00000000;
653 dma->ct[i] = 0x00000000;
654 dma->da[i] = 0x00000000;
655 dma->sa[i] = 0x00000000;
656 dma->sg[i] = 0x00000000;
657 }
658 dma->sr = 0x00000000;
659 dma->sgc = 0x00000000;
660 dma->slp = 0x7C000000;
661 dma->pol = 0x00000000;
662 }
663
664 static void ppc405_dma_init(CPUState *env, qemu_irq irqs[4])
665 {
666 ppc405_dma_t *dma;
667
668 dma = qemu_mallocz(sizeof(ppc405_dma_t));
669 memcpy(dma->irqs, irqs, 4 * sizeof(qemu_irq));
670 qemu_register_reset(&ppc405_dma_reset, dma);
671 ppc_dcr_register(env, DMA0_CR0,
672 dma, &dcr_read_dma, &dcr_write_dma);
673 ppc_dcr_register(env, DMA0_CT0,
674 dma, &dcr_read_dma, &dcr_write_dma);
675 ppc_dcr_register(env, DMA0_DA0,
676 dma, &dcr_read_dma, &dcr_write_dma);
677 ppc_dcr_register(env, DMA0_SA0,
678 dma, &dcr_read_dma, &dcr_write_dma);
679 ppc_dcr_register(env, DMA0_SG0,
680 dma, &dcr_read_dma, &dcr_write_dma);
681 ppc_dcr_register(env, DMA0_CR1,
682 dma, &dcr_read_dma, &dcr_write_dma);
683 ppc_dcr_register(env, DMA0_CT1,
684 dma, &dcr_read_dma, &dcr_write_dma);
685 ppc_dcr_register(env, DMA0_DA1,
686 dma, &dcr_read_dma, &dcr_write_dma);
687 ppc_dcr_register(env, DMA0_SA1,
688 dma, &dcr_read_dma, &dcr_write_dma);
689 ppc_dcr_register(env, DMA0_SG1,
690 dma, &dcr_read_dma, &dcr_write_dma);
691 ppc_dcr_register(env, DMA0_CR2,
692 dma, &dcr_read_dma, &dcr_write_dma);
693 ppc_dcr_register(env, DMA0_CT2,
694 dma, &dcr_read_dma, &dcr_write_dma);
695 ppc_dcr_register(env, DMA0_DA2,
696 dma, &dcr_read_dma, &dcr_write_dma);
697 ppc_dcr_register(env, DMA0_SA2,
698 dma, &dcr_read_dma, &dcr_write_dma);
699 ppc_dcr_register(env, DMA0_SG2,
700 dma, &dcr_read_dma, &dcr_write_dma);
701 ppc_dcr_register(env, DMA0_CR3,
702 dma, &dcr_read_dma, &dcr_write_dma);
703 ppc_dcr_register(env, DMA0_CT3,
704 dma, &dcr_read_dma, &dcr_write_dma);
705 ppc_dcr_register(env, DMA0_DA3,
706 dma, &dcr_read_dma, &dcr_write_dma);
707 ppc_dcr_register(env, DMA0_SA3,
708 dma, &dcr_read_dma, &dcr_write_dma);
709 ppc_dcr_register(env, DMA0_SG3,
710 dma, &dcr_read_dma, &dcr_write_dma);
711 ppc_dcr_register(env, DMA0_SR,
712 dma, &dcr_read_dma, &dcr_write_dma);
713 ppc_dcr_register(env, DMA0_SGC,
714 dma, &dcr_read_dma, &dcr_write_dma);
715 ppc_dcr_register(env, DMA0_SLP,
716 dma, &dcr_read_dma, &dcr_write_dma);
717 ppc_dcr_register(env, DMA0_POL,
718 dma, &dcr_read_dma, &dcr_write_dma);
719 }
720
721 /*****************************************************************************/
722 /* GPIO */
723 typedef struct ppc405_gpio_t ppc405_gpio_t;
724 struct ppc405_gpio_t {
725 uint32_t or;
726 uint32_t tcr;
727 uint32_t osrh;
728 uint32_t osrl;
729 uint32_t tsrh;
730 uint32_t tsrl;
731 uint32_t odr;
732 uint32_t ir;
733 uint32_t rr1;
734 uint32_t isr1h;
735 uint32_t isr1l;
736 };
737
738 static uint32_t ppc405_gpio_readb (void *opaque, target_phys_addr_t addr)
739 {
740 #ifdef DEBUG_GPIO
741 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
742 #endif
743
744 return 0;
745 }
746
747 static void ppc405_gpio_writeb (void *opaque,
748 target_phys_addr_t addr, uint32_t value)
749 {
750 #ifdef DEBUG_GPIO
751 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
752 value);
753 #endif
754 }
755
756 static uint32_t ppc405_gpio_readw (void *opaque, target_phys_addr_t addr)
757 {
758 #ifdef DEBUG_GPIO
759 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
760 #endif
761
762 return 0;
763 }
764
765 static void ppc405_gpio_writew (void *opaque,
766 target_phys_addr_t addr, uint32_t value)
767 {
768 #ifdef DEBUG_GPIO
769 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
770 value);
771 #endif
772 }
773
774 static uint32_t ppc405_gpio_readl (void *opaque, target_phys_addr_t addr)
775 {
776 #ifdef DEBUG_GPIO
777 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
778 #endif
779
780 return 0;
781 }
782
783 static void ppc405_gpio_writel (void *opaque,
784 target_phys_addr_t addr, uint32_t value)
785 {
786 #ifdef DEBUG_GPIO
787 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
788 value);
789 #endif
790 }
791
792 static CPUReadMemoryFunc * const ppc405_gpio_read[] = {
793 &ppc405_gpio_readb,
794 &ppc405_gpio_readw,
795 &ppc405_gpio_readl,
796 };
797
798 static CPUWriteMemoryFunc * const ppc405_gpio_write[] = {
799 &ppc405_gpio_writeb,
800 &ppc405_gpio_writew,
801 &ppc405_gpio_writel,
802 };
803
804 static void ppc405_gpio_reset (void *opaque)
805 {
806 }
807
808 static void ppc405_gpio_init(target_phys_addr_t base)
809 {
810 ppc405_gpio_t *gpio;
811 int io;
812
813 gpio = qemu_mallocz(sizeof(ppc405_gpio_t));
814 #ifdef DEBUG_GPIO
815 printf("%s: offset " TARGET_FMT_plx "\n", __func__, base);
816 #endif
817 io = cpu_register_io_memory(ppc405_gpio_read, ppc405_gpio_write, gpio,
818 DEVICE_NATIVE_ENDIAN);
819 cpu_register_physical_memory(base, 0x038, io);
820 qemu_register_reset(&ppc405_gpio_reset, gpio);
821 }
822
823 /*****************************************************************************/
824 /* On Chip Memory */
825 enum {
826 OCM0_ISARC = 0x018,
827 OCM0_ISACNTL = 0x019,
828 OCM0_DSARC = 0x01A,
829 OCM0_DSACNTL = 0x01B,
830 };
831
832 typedef struct ppc405_ocm_t ppc405_ocm_t;
833 struct ppc405_ocm_t {
834 target_ulong offset;
835 uint32_t isarc;
836 uint32_t isacntl;
837 uint32_t dsarc;
838 uint32_t dsacntl;
839 };
840
841 static void ocm_update_mappings (ppc405_ocm_t *ocm,
842 uint32_t isarc, uint32_t isacntl,
843 uint32_t dsarc, uint32_t dsacntl)
844 {
845 #ifdef DEBUG_OCM
846 printf("OCM update ISA %08" PRIx32 " %08" PRIx32 " (%08" PRIx32
847 " %08" PRIx32 ") DSA %08" PRIx32 " %08" PRIx32
848 " (%08" PRIx32 " %08" PRIx32 ")\n",
849 isarc, isacntl, dsarc, dsacntl,
850 ocm->isarc, ocm->isacntl, ocm->dsarc, ocm->dsacntl);
851 #endif
852 if (ocm->isarc != isarc ||
853 (ocm->isacntl & 0x80000000) != (isacntl & 0x80000000)) {
854 if (ocm->isacntl & 0x80000000) {
855 /* Unmap previously assigned memory region */
856 printf("OCM unmap ISA %08" PRIx32 "\n", ocm->isarc);
857 cpu_register_physical_memory(ocm->isarc, 0x04000000,
858 IO_MEM_UNASSIGNED);
859 }
860 if (isacntl & 0x80000000) {
861 /* Map new instruction memory region */
862 #ifdef DEBUG_OCM
863 printf("OCM map ISA %08" PRIx32 "\n", isarc);
864 #endif
865 cpu_register_physical_memory(isarc, 0x04000000,
866 ocm->offset | IO_MEM_RAM);
867 }
868 }
869 if (ocm->dsarc != dsarc ||
870 (ocm->dsacntl & 0x80000000) != (dsacntl & 0x80000000)) {
871 if (ocm->dsacntl & 0x80000000) {
872 /* Beware not to unmap the region we just mapped */
873 if (!(isacntl & 0x80000000) || ocm->dsarc != isarc) {
874 /* Unmap previously assigned memory region */
875 #ifdef DEBUG_OCM
876 printf("OCM unmap DSA %08" PRIx32 "\n", ocm->dsarc);
877 #endif
878 cpu_register_physical_memory(ocm->dsarc, 0x04000000,
879 IO_MEM_UNASSIGNED);
880 }
881 }
882 if (dsacntl & 0x80000000) {
883 /* Beware not to remap the region we just mapped */
884 if (!(isacntl & 0x80000000) || dsarc != isarc) {
885 /* Map new data memory region */
886 #ifdef DEBUG_OCM
887 printf("OCM map DSA %08" PRIx32 "\n", dsarc);
888 #endif
889 cpu_register_physical_memory(dsarc, 0x04000000,
890 ocm->offset | IO_MEM_RAM);
891 }
892 }
893 }
894 }
895
896 static uint32_t dcr_read_ocm (void *opaque, int dcrn)
897 {
898 ppc405_ocm_t *ocm;
899 uint32_t ret;
900
901 ocm = opaque;
902 switch (dcrn) {
903 case OCM0_ISARC:
904 ret = ocm->isarc;
905 break;
906 case OCM0_ISACNTL:
907 ret = ocm->isacntl;
908 break;
909 case OCM0_DSARC:
910 ret = ocm->dsarc;
911 break;
912 case OCM0_DSACNTL:
913 ret = ocm->dsacntl;
914 break;
915 default:
916 ret = 0;
917 break;
918 }
919
920 return ret;
921 }
922
923 static void dcr_write_ocm (void *opaque, int dcrn, uint32_t val)
924 {
925 ppc405_ocm_t *ocm;
926 uint32_t isarc, dsarc, isacntl, dsacntl;
927
928 ocm = opaque;
929 isarc = ocm->isarc;
930 dsarc = ocm->dsarc;
931 isacntl = ocm->isacntl;
932 dsacntl = ocm->dsacntl;
933 switch (dcrn) {
934 case OCM0_ISARC:
935 isarc = val & 0xFC000000;
936 break;
937 case OCM0_ISACNTL:
938 isacntl = val & 0xC0000000;
939 break;
940 case OCM0_DSARC:
941 isarc = val & 0xFC000000;
942 break;
943 case OCM0_DSACNTL:
944 isacntl = val & 0xC0000000;
945 break;
946 }
947 ocm_update_mappings(ocm, isarc, isacntl, dsarc, dsacntl);
948 ocm->isarc = isarc;
949 ocm->dsarc = dsarc;
950 ocm->isacntl = isacntl;
951 ocm->dsacntl = dsacntl;
952 }
953
954 static void ocm_reset (void *opaque)
955 {
956 ppc405_ocm_t *ocm;
957 uint32_t isarc, dsarc, isacntl, dsacntl;
958
959 ocm = opaque;
960 isarc = 0x00000000;
961 isacntl = 0x00000000;
962 dsarc = 0x00000000;
963 dsacntl = 0x00000000;
964 ocm_update_mappings(ocm, isarc, isacntl, dsarc, dsacntl);
965 ocm->isarc = isarc;
966 ocm->dsarc = dsarc;
967 ocm->isacntl = isacntl;
968 ocm->dsacntl = dsacntl;
969 }
970
971 static void ppc405_ocm_init(CPUState *env)
972 {
973 ppc405_ocm_t *ocm;
974
975 ocm = qemu_mallocz(sizeof(ppc405_ocm_t));
976 ocm->offset = qemu_ram_alloc(NULL, "ppc405.ocm", 4096);
977 qemu_register_reset(&ocm_reset, ocm);
978 ppc_dcr_register(env, OCM0_ISARC,
979 ocm, &dcr_read_ocm, &dcr_write_ocm);
980 ppc_dcr_register(env, OCM0_ISACNTL,
981 ocm, &dcr_read_ocm, &dcr_write_ocm);
982 ppc_dcr_register(env, OCM0_DSARC,
983 ocm, &dcr_read_ocm, &dcr_write_ocm);
984 ppc_dcr_register(env, OCM0_DSACNTL,
985 ocm, &dcr_read_ocm, &dcr_write_ocm);
986 }
987
988 /*****************************************************************************/
989 /* I2C controller */
990 typedef struct ppc4xx_i2c_t ppc4xx_i2c_t;
991 struct ppc4xx_i2c_t {
992 qemu_irq irq;
993 uint8_t mdata;
994 uint8_t lmadr;
995 uint8_t hmadr;
996 uint8_t cntl;
997 uint8_t mdcntl;
998 uint8_t sts;
999 uint8_t extsts;
1000 uint8_t sdata;
1001 uint8_t lsadr;
1002 uint8_t hsadr;
1003 uint8_t clkdiv;
1004 uint8_t intrmsk;
1005 uint8_t xfrcnt;
1006 uint8_t xtcntlss;
1007 uint8_t directcntl;
1008 };
1009
1010 static uint32_t ppc4xx_i2c_readb (void *opaque, target_phys_addr_t addr)
1011 {
1012 ppc4xx_i2c_t *i2c;
1013 uint32_t ret;
1014
1015 #ifdef DEBUG_I2C
1016 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
1017 #endif
1018 i2c = opaque;
1019 switch (addr) {
1020 case 0x00:
1021 // i2c_readbyte(&i2c->mdata);
1022 ret = i2c->mdata;
1023 break;
1024 case 0x02:
1025 ret = i2c->sdata;
1026 break;
1027 case 0x04:
1028 ret = i2c->lmadr;
1029 break;
1030 case 0x05:
1031 ret = i2c->hmadr;
1032 break;
1033 case 0x06:
1034 ret = i2c->cntl;
1035 break;
1036 case 0x07:
1037 ret = i2c->mdcntl;
1038 break;
1039 case 0x08:
1040 ret = i2c->sts;
1041 break;
1042 case 0x09:
1043 ret = i2c->extsts;
1044 break;
1045 case 0x0A:
1046 ret = i2c->lsadr;
1047 break;
1048 case 0x0B:
1049 ret = i2c->hsadr;
1050 break;
1051 case 0x0C:
1052 ret = i2c->clkdiv;
1053 break;
1054 case 0x0D:
1055 ret = i2c->intrmsk;
1056 break;
1057 case 0x0E:
1058 ret = i2c->xfrcnt;
1059 break;
1060 case 0x0F:
1061 ret = i2c->xtcntlss;
1062 break;
1063 case 0x10:
1064 ret = i2c->directcntl;
1065 break;
1066 default:
1067 ret = 0x00;
1068 break;
1069 }
1070 #ifdef DEBUG_I2C
1071 printf("%s: addr " TARGET_FMT_plx " %02" PRIx32 "\n", __func__, addr, ret);
1072 #endif
1073
1074 return ret;
1075 }
1076
1077 static void ppc4xx_i2c_writeb (void *opaque,
1078 target_phys_addr_t addr, uint32_t value)
1079 {
1080 ppc4xx_i2c_t *i2c;
1081
1082 #ifdef DEBUG_I2C
1083 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
1084 value);
1085 #endif
1086 i2c = opaque;
1087 switch (addr) {
1088 case 0x00:
1089 i2c->mdata = value;
1090 // i2c_sendbyte(&i2c->mdata);
1091 break;
1092 case 0x02:
1093 i2c->sdata = value;
1094 break;
1095 case 0x04:
1096 i2c->lmadr = value;
1097 break;
1098 case 0x05:
1099 i2c->hmadr = value;
1100 break;
1101 case 0x06:
1102 i2c->cntl = value;
1103 break;
1104 case 0x07:
1105 i2c->mdcntl = value & 0xDF;
1106 break;
1107 case 0x08:
1108 i2c->sts &= ~(value & 0x0A);
1109 break;
1110 case 0x09:
1111 i2c->extsts &= ~(value & 0x8F);
1112 break;
1113 case 0x0A:
1114 i2c->lsadr = value;
1115 break;
1116 case 0x0B:
1117 i2c->hsadr = value;
1118 break;
1119 case 0x0C:
1120 i2c->clkdiv = value;
1121 break;
1122 case 0x0D:
1123 i2c->intrmsk = value;
1124 break;
1125 case 0x0E:
1126 i2c->xfrcnt = value & 0x77;
1127 break;
1128 case 0x0F:
1129 i2c->xtcntlss = value;
1130 break;
1131 case 0x10:
1132 i2c->directcntl = value & 0x7;
1133 break;
1134 }
1135 }
1136
1137 static uint32_t ppc4xx_i2c_readw (void *opaque, target_phys_addr_t addr)
1138 {
1139 uint32_t ret;
1140
1141 #ifdef DEBUG_I2C
1142 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
1143 #endif
1144 ret = ppc4xx_i2c_readb(opaque, addr) << 8;
1145 ret |= ppc4xx_i2c_readb(opaque, addr + 1);
1146
1147 return ret;
1148 }
1149
1150 static void ppc4xx_i2c_writew (void *opaque,
1151 target_phys_addr_t addr, uint32_t value)
1152 {
1153 #ifdef DEBUG_I2C
1154 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
1155 value);
1156 #endif
1157 ppc4xx_i2c_writeb(opaque, addr, value >> 8);
1158 ppc4xx_i2c_writeb(opaque, addr + 1, value);
1159 }
1160
1161 static uint32_t ppc4xx_i2c_readl (void *opaque, target_phys_addr_t addr)
1162 {
1163 uint32_t ret;
1164
1165 #ifdef DEBUG_I2C
1166 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
1167 #endif
1168 ret = ppc4xx_i2c_readb(opaque, addr) << 24;
1169 ret |= ppc4xx_i2c_readb(opaque, addr + 1) << 16;
1170 ret |= ppc4xx_i2c_readb(opaque, addr + 2) << 8;
1171 ret |= ppc4xx_i2c_readb(opaque, addr + 3);
1172
1173 return ret;
1174 }
1175
1176 static void ppc4xx_i2c_writel (void *opaque,
1177 target_phys_addr_t addr, uint32_t value)
1178 {
1179 #ifdef DEBUG_I2C
1180 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
1181 value);
1182 #endif
1183 ppc4xx_i2c_writeb(opaque, addr, value >> 24);
1184 ppc4xx_i2c_writeb(opaque, addr + 1, value >> 16);
1185 ppc4xx_i2c_writeb(opaque, addr + 2, value >> 8);
1186 ppc4xx_i2c_writeb(opaque, addr + 3, value);
1187 }
1188
1189 static CPUReadMemoryFunc * const i2c_read[] = {
1190 &ppc4xx_i2c_readb,
1191 &ppc4xx_i2c_readw,
1192 &ppc4xx_i2c_readl,
1193 };
1194
1195 static CPUWriteMemoryFunc * const i2c_write[] = {
1196 &ppc4xx_i2c_writeb,
1197 &ppc4xx_i2c_writew,
1198 &ppc4xx_i2c_writel,
1199 };
1200
1201 static void ppc4xx_i2c_reset (void *opaque)
1202 {
1203 ppc4xx_i2c_t *i2c;
1204
1205 i2c = opaque;
1206 i2c->mdata = 0x00;
1207 i2c->sdata = 0x00;
1208 i2c->cntl = 0x00;
1209 i2c->mdcntl = 0x00;
1210 i2c->sts = 0x00;
1211 i2c->extsts = 0x00;
1212 i2c->clkdiv = 0x00;
1213 i2c->xfrcnt = 0x00;
1214 i2c->directcntl = 0x0F;
1215 }
1216
1217 static void ppc405_i2c_init(target_phys_addr_t base, qemu_irq irq)
1218 {
1219 ppc4xx_i2c_t *i2c;
1220 int io;
1221
1222 i2c = qemu_mallocz(sizeof(ppc4xx_i2c_t));
1223 i2c->irq = irq;
1224 #ifdef DEBUG_I2C
1225 printf("%s: offset " TARGET_FMT_plx "\n", __func__, base);
1226 #endif
1227 io = cpu_register_io_memory(i2c_read, i2c_write, i2c,
1228 DEVICE_NATIVE_ENDIAN);
1229 cpu_register_physical_memory(base, 0x011, io);
1230 qemu_register_reset(ppc4xx_i2c_reset, i2c);
1231 }
1232
1233 /*****************************************************************************/
1234 /* General purpose timers */
1235 typedef struct ppc4xx_gpt_t ppc4xx_gpt_t;
1236 struct ppc4xx_gpt_t {
1237 int64_t tb_offset;
1238 uint32_t tb_freq;
1239 struct QEMUTimer *timer;
1240 qemu_irq irqs[5];
1241 uint32_t oe;
1242 uint32_t ol;
1243 uint32_t im;
1244 uint32_t is;
1245 uint32_t ie;
1246 uint32_t comp[5];
1247 uint32_t mask[5];
1248 };
1249
1250 static uint32_t ppc4xx_gpt_readb (void *opaque, target_phys_addr_t addr)
1251 {
1252 #ifdef DEBUG_GPT
1253 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
1254 #endif
1255 /* XXX: generate a bus fault */
1256 return -1;
1257 }
1258
1259 static void ppc4xx_gpt_writeb (void *opaque,
1260 target_phys_addr_t addr, uint32_t value)
1261 {
1262 #ifdef DEBUG_I2C
1263 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
1264 value);
1265 #endif
1266 /* XXX: generate a bus fault */
1267 }
1268
1269 static uint32_t ppc4xx_gpt_readw (void *opaque, target_phys_addr_t addr)
1270 {
1271 #ifdef DEBUG_GPT
1272 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
1273 #endif
1274 /* XXX: generate a bus fault */
1275 return -1;
1276 }
1277
1278 static void ppc4xx_gpt_writew (void *opaque,
1279 target_phys_addr_t addr, uint32_t value)
1280 {
1281 #ifdef DEBUG_I2C
1282 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
1283 value);
1284 #endif
1285 /* XXX: generate a bus fault */
1286 }
1287
1288 static int ppc4xx_gpt_compare (ppc4xx_gpt_t *gpt, int n)
1289 {
1290 /* XXX: TODO */
1291 return 0;
1292 }
1293
1294 static void ppc4xx_gpt_set_output (ppc4xx_gpt_t *gpt, int n, int level)
1295 {
1296 /* XXX: TODO */
1297 }
1298
1299 static void ppc4xx_gpt_set_outputs (ppc4xx_gpt_t *gpt)
1300 {
1301 uint32_t mask;
1302 int i;
1303
1304 mask = 0x80000000;
1305 for (i = 0; i < 5; i++) {
1306 if (gpt->oe & mask) {
1307 /* Output is enabled */
1308 if (ppc4xx_gpt_compare(gpt, i)) {
1309 /* Comparison is OK */
1310 ppc4xx_gpt_set_output(gpt, i, gpt->ol & mask);
1311 } else {
1312 /* Comparison is KO */
1313 ppc4xx_gpt_set_output(gpt, i, gpt->ol & mask ? 0 : 1);
1314 }
1315 }
1316 mask = mask >> 1;
1317 }
1318 }
1319
1320 static void ppc4xx_gpt_set_irqs (ppc4xx_gpt_t *gpt)
1321 {
1322 uint32_t mask;
1323 int i;
1324
1325 mask = 0x00008000;
1326 for (i = 0; i < 5; i++) {
1327 if (gpt->is & gpt->im & mask)
1328 qemu_irq_raise(gpt->irqs[i]);
1329 else
1330 qemu_irq_lower(gpt->irqs[i]);
1331 mask = mask >> 1;
1332 }
1333 }
1334
1335 static void ppc4xx_gpt_compute_timer (ppc4xx_gpt_t *gpt)
1336 {
1337 /* XXX: TODO */
1338 }
1339
1340 static uint32_t ppc4xx_gpt_readl (void *opaque, target_phys_addr_t addr)
1341 {
1342 ppc4xx_gpt_t *gpt;
1343 uint32_t ret;
1344 int idx;
1345
1346 #ifdef DEBUG_GPT
1347 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
1348 #endif
1349 gpt = opaque;
1350 switch (addr) {
1351 case 0x00:
1352 /* Time base counter */
1353 ret = muldiv64(qemu_get_clock_ns(vm_clock) + gpt->tb_offset,
1354 gpt->tb_freq, get_ticks_per_sec());
1355 break;
1356 case 0x10:
1357 /* Output enable */
1358 ret = gpt->oe;
1359 break;
1360 case 0x14:
1361 /* Output level */
1362 ret = gpt->ol;
1363 break;
1364 case 0x18:
1365 /* Interrupt mask */
1366 ret = gpt->im;
1367 break;
1368 case 0x1C:
1369 case 0x20:
1370 /* Interrupt status */
1371 ret = gpt->is;
1372 break;
1373 case 0x24:
1374 /* Interrupt enable */
1375 ret = gpt->ie;
1376 break;
1377 case 0x80 ... 0x90:
1378 /* Compare timer */
1379 idx = (addr - 0x80) >> 2;
1380 ret = gpt->comp[idx];
1381 break;
1382 case 0xC0 ... 0xD0:
1383 /* Compare mask */
1384 idx = (addr - 0xC0) >> 2;
1385 ret = gpt->mask[idx];
1386 break;
1387 default:
1388 ret = -1;
1389 break;
1390 }
1391
1392 return ret;
1393 }
1394
1395 static void ppc4xx_gpt_writel (void *opaque,
1396 target_phys_addr_t addr, uint32_t value)
1397 {
1398 ppc4xx_gpt_t *gpt;
1399 int idx;
1400
1401 #ifdef DEBUG_I2C
1402 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
1403 value);
1404 #endif
1405 gpt = opaque;
1406 switch (addr) {
1407 case 0x00:
1408 /* Time base counter */
1409 gpt->tb_offset = muldiv64(value, get_ticks_per_sec(), gpt->tb_freq)
1410 - qemu_get_clock_ns(vm_clock);
1411 ppc4xx_gpt_compute_timer(gpt);
1412 break;
1413 case 0x10:
1414 /* Output enable */
1415 gpt->oe = value & 0xF8000000;
1416 ppc4xx_gpt_set_outputs(gpt);
1417 break;
1418 case 0x14:
1419 /* Output level */
1420 gpt->ol = value & 0xF8000000;
1421 ppc4xx_gpt_set_outputs(gpt);
1422 break;
1423 case 0x18:
1424 /* Interrupt mask */
1425 gpt->im = value & 0x0000F800;
1426 break;
1427 case 0x1C:
1428 /* Interrupt status set */
1429 gpt->is |= value & 0x0000F800;
1430 ppc4xx_gpt_set_irqs(gpt);
1431 break;
1432 case 0x20:
1433 /* Interrupt status clear */
1434 gpt->is &= ~(value & 0x0000F800);
1435 ppc4xx_gpt_set_irqs(gpt);
1436 break;
1437 case 0x24:
1438 /* Interrupt enable */
1439 gpt->ie = value & 0x0000F800;
1440 ppc4xx_gpt_set_irqs(gpt);
1441 break;
1442 case 0x80 ... 0x90:
1443 /* Compare timer */
1444 idx = (addr - 0x80) >> 2;
1445 gpt->comp[idx] = value & 0xF8000000;
1446 ppc4xx_gpt_compute_timer(gpt);
1447 break;
1448 case 0xC0 ... 0xD0:
1449 /* Compare mask */
1450 idx = (addr - 0xC0) >> 2;
1451 gpt->mask[idx] = value & 0xF8000000;
1452 ppc4xx_gpt_compute_timer(gpt);
1453 break;
1454 }
1455 }
1456
1457 static CPUReadMemoryFunc * const gpt_read[] = {
1458 &ppc4xx_gpt_readb,
1459 &ppc4xx_gpt_readw,
1460 &ppc4xx_gpt_readl,
1461 };
1462
1463 static CPUWriteMemoryFunc * const gpt_write[] = {
1464 &ppc4xx_gpt_writeb,
1465 &ppc4xx_gpt_writew,
1466 &ppc4xx_gpt_writel,
1467 };
1468
1469 static void ppc4xx_gpt_cb (void *opaque)
1470 {
1471 ppc4xx_gpt_t *gpt;
1472
1473 gpt = opaque;
1474 ppc4xx_gpt_set_irqs(gpt);
1475 ppc4xx_gpt_set_outputs(gpt);
1476 ppc4xx_gpt_compute_timer(gpt);
1477 }
1478
1479 static void ppc4xx_gpt_reset (void *opaque)
1480 {
1481 ppc4xx_gpt_t *gpt;
1482 int i;
1483
1484 gpt = opaque;
1485 qemu_del_timer(gpt->timer);
1486 gpt->oe = 0x00000000;
1487 gpt->ol = 0x00000000;
1488 gpt->im = 0x00000000;
1489 gpt->is = 0x00000000;
1490 gpt->ie = 0x00000000;
1491 for (i = 0; i < 5; i++) {
1492 gpt->comp[i] = 0x00000000;
1493 gpt->mask[i] = 0x00000000;
1494 }
1495 }
1496
1497 static void ppc4xx_gpt_init(target_phys_addr_t base, qemu_irq irqs[5])
1498 {
1499 ppc4xx_gpt_t *gpt;
1500 int i;
1501 int io;
1502
1503 gpt = qemu_mallocz(sizeof(ppc4xx_gpt_t));
1504 for (i = 0; i < 5; i++) {
1505 gpt->irqs[i] = irqs[i];
1506 }
1507 gpt->timer = qemu_new_timer_ns(vm_clock, &ppc4xx_gpt_cb, gpt);
1508 #ifdef DEBUG_GPT
1509 printf("%s: offset " TARGET_FMT_plx "\n", __func__, base);
1510 #endif
1511 io = cpu_register_io_memory(gpt_read, gpt_write, gpt, DEVICE_NATIVE_ENDIAN);
1512 cpu_register_physical_memory(base, 0x0d4, io);
1513 qemu_register_reset(ppc4xx_gpt_reset, gpt);
1514 }
1515
1516 /*****************************************************************************/
1517 /* MAL */
1518 enum {
1519 MAL0_CFG = 0x180,
1520 MAL0_ESR = 0x181,
1521 MAL0_IER = 0x182,
1522 MAL0_TXCASR = 0x184,
1523 MAL0_TXCARR = 0x185,
1524 MAL0_TXEOBISR = 0x186,
1525 MAL0_TXDEIR = 0x187,
1526 MAL0_RXCASR = 0x190,
1527 MAL0_RXCARR = 0x191,
1528 MAL0_RXEOBISR = 0x192,
1529 MAL0_RXDEIR = 0x193,
1530 MAL0_TXCTP0R = 0x1A0,
1531 MAL0_TXCTP1R = 0x1A1,
1532 MAL0_TXCTP2R = 0x1A2,
1533 MAL0_TXCTP3R = 0x1A3,
1534 MAL0_RXCTP0R = 0x1C0,
1535 MAL0_RXCTP1R = 0x1C1,
1536 MAL0_RCBS0 = 0x1E0,
1537 MAL0_RCBS1 = 0x1E1,
1538 };
1539
1540 typedef struct ppc40x_mal_t ppc40x_mal_t;
1541 struct ppc40x_mal_t {
1542 qemu_irq irqs[4];
1543 uint32_t cfg;
1544 uint32_t esr;
1545 uint32_t ier;
1546 uint32_t txcasr;
1547 uint32_t txcarr;
1548 uint32_t txeobisr;
1549 uint32_t txdeir;
1550 uint32_t rxcasr;
1551 uint32_t rxcarr;
1552 uint32_t rxeobisr;
1553 uint32_t rxdeir;
1554 uint32_t txctpr[4];
1555 uint32_t rxctpr[2];
1556 uint32_t rcbs[2];
1557 };
1558
1559 static void ppc40x_mal_reset (void *opaque);
1560
1561 static uint32_t dcr_read_mal (void *opaque, int dcrn)
1562 {
1563 ppc40x_mal_t *mal;
1564 uint32_t ret;
1565
1566 mal = opaque;
1567 switch (dcrn) {
1568 case MAL0_CFG:
1569 ret = mal->cfg;
1570 break;
1571 case MAL0_ESR:
1572 ret = mal->esr;
1573 break;
1574 case MAL0_IER:
1575 ret = mal->ier;
1576 break;
1577 case MAL0_TXCASR:
1578 ret = mal->txcasr;
1579 break;
1580 case MAL0_TXCARR:
1581 ret = mal->txcarr;
1582 break;
1583 case MAL0_TXEOBISR:
1584 ret = mal->txeobisr;
1585 break;
1586 case MAL0_TXDEIR:
1587 ret = mal->txdeir;
1588 break;
1589 case MAL0_RXCASR:
1590 ret = mal->rxcasr;
1591 break;
1592 case MAL0_RXCARR:
1593 ret = mal->rxcarr;
1594 break;
1595 case MAL0_RXEOBISR:
1596 ret = mal->rxeobisr;
1597 break;
1598 case MAL0_RXDEIR:
1599 ret = mal->rxdeir;
1600 break;
1601 case MAL0_TXCTP0R:
1602 ret = mal->txctpr[0];
1603 break;
1604 case MAL0_TXCTP1R:
1605 ret = mal->txctpr[1];
1606 break;
1607 case MAL0_TXCTP2R:
1608 ret = mal->txctpr[2];
1609 break;
1610 case MAL0_TXCTP3R:
1611 ret = mal->txctpr[3];
1612 break;
1613 case MAL0_RXCTP0R:
1614 ret = mal->rxctpr[0];
1615 break;
1616 case MAL0_RXCTP1R:
1617 ret = mal->rxctpr[1];
1618 break;
1619 case MAL0_RCBS0:
1620 ret = mal->rcbs[0];
1621 break;
1622 case MAL0_RCBS1:
1623 ret = mal->rcbs[1];
1624 break;
1625 default:
1626 ret = 0;
1627 break;
1628 }
1629
1630 return ret;
1631 }
1632
1633 static void dcr_write_mal (void *opaque, int dcrn, uint32_t val)
1634 {
1635 ppc40x_mal_t *mal;
1636 int idx;
1637
1638 mal = opaque;
1639 switch (dcrn) {
1640 case MAL0_CFG:
1641 if (val & 0x80000000)
1642 ppc40x_mal_reset(mal);
1643 mal->cfg = val & 0x00FFC087;
1644 break;
1645 case MAL0_ESR:
1646 /* Read/clear */
1647 mal->esr &= ~val;
1648 break;
1649 case MAL0_IER:
1650 mal->ier = val & 0x0000001F;
1651 break;
1652 case MAL0_TXCASR:
1653 mal->txcasr = val & 0xF0000000;
1654 break;
1655 case MAL0_TXCARR:
1656 mal->txcarr = val & 0xF0000000;
1657 break;
1658 case MAL0_TXEOBISR:
1659 /* Read/clear */
1660 mal->txeobisr &= ~val;
1661 break;
1662 case MAL0_TXDEIR:
1663 /* Read/clear */
1664 mal->txdeir &= ~val;
1665 break;
1666 case MAL0_RXCASR:
1667 mal->rxcasr = val & 0xC0000000;
1668 break;
1669 case MAL0_RXCARR:
1670 mal->rxcarr = val & 0xC0000000;
1671 break;
1672 case MAL0_RXEOBISR:
1673 /* Read/clear */
1674 mal->rxeobisr &= ~val;
1675 break;
1676 case MAL0_RXDEIR:
1677 /* Read/clear */
1678 mal->rxdeir &= ~val;
1679 break;
1680 case MAL0_TXCTP0R:
1681 idx = 0;
1682 goto update_tx_ptr;
1683 case MAL0_TXCTP1R:
1684 idx = 1;
1685 goto update_tx_ptr;
1686 case MAL0_TXCTP2R:
1687 idx = 2;
1688 goto update_tx_ptr;
1689 case MAL0_TXCTP3R:
1690 idx = 3;
1691 update_tx_ptr:
1692 mal->txctpr[idx] = val;
1693 break;
1694 case MAL0_RXCTP0R:
1695 idx = 0;
1696 goto update_rx_ptr;
1697 case MAL0_RXCTP1R:
1698 idx = 1;
1699 update_rx_ptr:
1700 mal->rxctpr[idx] = val;
1701 break;
1702 case MAL0_RCBS0:
1703 idx = 0;
1704 goto update_rx_size;
1705 case MAL0_RCBS1:
1706 idx = 1;
1707 update_rx_size:
1708 mal->rcbs[idx] = val & 0x000000FF;
1709 break;
1710 }
1711 }
1712
1713 static void ppc40x_mal_reset (void *opaque)
1714 {
1715 ppc40x_mal_t *mal;
1716
1717 mal = opaque;
1718 mal->cfg = 0x0007C000;
1719 mal->esr = 0x00000000;
1720 mal->ier = 0x00000000;
1721 mal->rxcasr = 0x00000000;
1722 mal->rxdeir = 0x00000000;
1723 mal->rxeobisr = 0x00000000;
1724 mal->txcasr = 0x00000000;
1725 mal->txdeir = 0x00000000;
1726 mal->txeobisr = 0x00000000;
1727 }
1728
1729 static void ppc405_mal_init(CPUState *env, qemu_irq irqs[4])
1730 {
1731 ppc40x_mal_t *mal;
1732 int i;
1733
1734 mal = qemu_mallocz(sizeof(ppc40x_mal_t));
1735 for (i = 0; i < 4; i++)
1736 mal->irqs[i] = irqs[i];
1737 qemu_register_reset(&ppc40x_mal_reset, mal);
1738 ppc_dcr_register(env, MAL0_CFG,
1739 mal, &dcr_read_mal, &dcr_write_mal);
1740 ppc_dcr_register(env, MAL0_ESR,
1741 mal, &dcr_read_mal, &dcr_write_mal);
1742 ppc_dcr_register(env, MAL0_IER,
1743 mal, &dcr_read_mal, &dcr_write_mal);
1744 ppc_dcr_register(env, MAL0_TXCASR,
1745 mal, &dcr_read_mal, &dcr_write_mal);
1746 ppc_dcr_register(env, MAL0_TXCARR,
1747 mal, &dcr_read_mal, &dcr_write_mal);
1748 ppc_dcr_register(env, MAL0_TXEOBISR,
1749 mal, &dcr_read_mal, &dcr_write_mal);
1750 ppc_dcr_register(env, MAL0_TXDEIR,
1751 mal, &dcr_read_mal, &dcr_write_mal);
1752 ppc_dcr_register(env, MAL0_RXCASR,
1753 mal, &dcr_read_mal, &dcr_write_mal);
1754 ppc_dcr_register(env, MAL0_RXCARR,
1755 mal, &dcr_read_mal, &dcr_write_mal);
1756 ppc_dcr_register(env, MAL0_RXEOBISR,
1757 mal, &dcr_read_mal, &dcr_write_mal);
1758 ppc_dcr_register(env, MAL0_RXDEIR,
1759 mal, &dcr_read_mal, &dcr_write_mal);
1760 ppc_dcr_register(env, MAL0_TXCTP0R,
1761 mal, &dcr_read_mal, &dcr_write_mal);
1762 ppc_dcr_register(env, MAL0_TXCTP1R,
1763 mal, &dcr_read_mal, &dcr_write_mal);
1764 ppc_dcr_register(env, MAL0_TXCTP2R,
1765 mal, &dcr_read_mal, &dcr_write_mal);
1766 ppc_dcr_register(env, MAL0_TXCTP3R,
1767 mal, &dcr_read_mal, &dcr_write_mal);
1768 ppc_dcr_register(env, MAL0_RXCTP0R,
1769 mal, &dcr_read_mal, &dcr_write_mal);
1770 ppc_dcr_register(env, MAL0_RXCTP1R,
1771 mal, &dcr_read_mal, &dcr_write_mal);
1772 ppc_dcr_register(env, MAL0_RCBS0,
1773 mal, &dcr_read_mal, &dcr_write_mal);
1774 ppc_dcr_register(env, MAL0_RCBS1,
1775 mal, &dcr_read_mal, &dcr_write_mal);
1776 }
1777
1778 /*****************************************************************************/
1779 /* SPR */
1780 void ppc40x_core_reset (CPUState *env)
1781 {
1782 target_ulong dbsr;
1783
1784 printf("Reset PowerPC core\n");
1785 env->interrupt_request |= CPU_INTERRUPT_EXITTB;
1786 /* XXX: TOFIX */
1787 #if 0
1788 cpu_reset(env);
1789 #else
1790 qemu_system_reset_request();
1791 #endif
1792 dbsr = env->spr[SPR_40x_DBSR];
1793 dbsr &= ~0x00000300;
1794 dbsr |= 0x00000100;
1795 env->spr[SPR_40x_DBSR] = dbsr;
1796 }
1797
1798 void ppc40x_chip_reset (CPUState *env)
1799 {
1800 target_ulong dbsr;
1801
1802 printf("Reset PowerPC chip\n");
1803 env->interrupt_request |= CPU_INTERRUPT_EXITTB;
1804 /* XXX: TOFIX */
1805 #if 0
1806 cpu_reset(env);
1807 #else
1808 qemu_system_reset_request();
1809 #endif
1810 /* XXX: TODO reset all internal peripherals */
1811 dbsr = env->spr[SPR_40x_DBSR];
1812 dbsr &= ~0x00000300;
1813 dbsr |= 0x00000200;
1814 env->spr[SPR_40x_DBSR] = dbsr;
1815 }
1816
1817 void ppc40x_system_reset (CPUState *env)
1818 {
1819 printf("Reset PowerPC system\n");
1820 qemu_system_reset_request();
1821 }
1822
1823 void store_40x_dbcr0 (CPUState *env, uint32_t val)
1824 {
1825 switch ((val >> 28) & 0x3) {
1826 case 0x0:
1827 /* No action */
1828 break;
1829 case 0x1:
1830 /* Core reset */
1831 ppc40x_core_reset(env);
1832 break;
1833 case 0x2:
1834 /* Chip reset */
1835 ppc40x_chip_reset(env);
1836 break;
1837 case 0x3:
1838 /* System reset */
1839 ppc40x_system_reset(env);
1840 break;
1841 }
1842 }
1843
1844 /*****************************************************************************/
1845 /* PowerPC 405CR */
1846 enum {
1847 PPC405CR_CPC0_PLLMR = 0x0B0,
1848 PPC405CR_CPC0_CR0 = 0x0B1,
1849 PPC405CR_CPC0_CR1 = 0x0B2,
1850 PPC405CR_CPC0_PSR = 0x0B4,
1851 PPC405CR_CPC0_JTAGID = 0x0B5,
1852 PPC405CR_CPC0_ER = 0x0B9,
1853 PPC405CR_CPC0_FR = 0x0BA,
1854 PPC405CR_CPC0_SR = 0x0BB,
1855 };
1856
1857 enum {
1858 PPC405CR_CPU_CLK = 0,
1859 PPC405CR_TMR_CLK = 1,
1860 PPC405CR_PLB_CLK = 2,
1861 PPC405CR_SDRAM_CLK = 3,
1862 PPC405CR_OPB_CLK = 4,
1863 PPC405CR_EXT_CLK = 5,
1864 PPC405CR_UART_CLK = 6,
1865 PPC405CR_CLK_NB = 7,
1866 };
1867
1868 typedef struct ppc405cr_cpc_t ppc405cr_cpc_t;
1869 struct ppc405cr_cpc_t {
1870 clk_setup_t clk_setup[PPC405CR_CLK_NB];
1871 uint32_t sysclk;
1872 uint32_t psr;
1873 uint32_t cr0;
1874 uint32_t cr1;
1875 uint32_t jtagid;
1876 uint32_t pllmr;
1877 uint32_t er;
1878 uint32_t fr;
1879 };
1880
1881 static void ppc405cr_clk_setup (ppc405cr_cpc_t *cpc)
1882 {
1883 uint64_t VCO_out, PLL_out;
1884 uint32_t CPU_clk, TMR_clk, SDRAM_clk, PLB_clk, OPB_clk, EXT_clk, UART_clk;
1885 int M, D0, D1, D2;
1886
1887 D0 = ((cpc->pllmr >> 26) & 0x3) + 1; /* CBDV */
1888 if (cpc->pllmr & 0x80000000) {
1889 D1 = (((cpc->pllmr >> 20) - 1) & 0xF) + 1; /* FBDV */
1890 D2 = 8 - ((cpc->pllmr >> 16) & 0x7); /* FWDVA */
1891 M = D0 * D1 * D2;
1892 VCO_out = cpc->sysclk * M;
1893 if (VCO_out < 400000000 || VCO_out > 800000000) {
1894 /* PLL cannot lock */
1895 cpc->pllmr &= ~0x80000000;
1896 goto bypass_pll;
1897 }
1898 PLL_out = VCO_out / D2;
1899 } else {
1900 /* Bypass PLL */
1901 bypass_pll:
1902 M = D0;
1903 PLL_out = cpc->sysclk * M;
1904 }
1905 CPU_clk = PLL_out;
1906 if (cpc->cr1 & 0x00800000)
1907 TMR_clk = cpc->sysclk; /* Should have a separate clock */
1908 else
1909 TMR_clk = CPU_clk;
1910 PLB_clk = CPU_clk / D0;
1911 SDRAM_clk = PLB_clk;
1912 D0 = ((cpc->pllmr >> 10) & 0x3) + 1;
1913 OPB_clk = PLB_clk / D0;
1914 D0 = ((cpc->pllmr >> 24) & 0x3) + 2;
1915 EXT_clk = PLB_clk / D0;
1916 D0 = ((cpc->cr0 >> 1) & 0x1F) + 1;
1917 UART_clk = CPU_clk / D0;
1918 /* Setup CPU clocks */
1919 clk_setup(&cpc->clk_setup[PPC405CR_CPU_CLK], CPU_clk);
1920 /* Setup time-base clock */
1921 clk_setup(&cpc->clk_setup[PPC405CR_TMR_CLK], TMR_clk);
1922 /* Setup PLB clock */
1923 clk_setup(&cpc->clk_setup[PPC405CR_PLB_CLK], PLB_clk);
1924 /* Setup SDRAM clock */
1925 clk_setup(&cpc->clk_setup[PPC405CR_SDRAM_CLK], SDRAM_clk);
1926 /* Setup OPB clock */
1927 clk_setup(&cpc->clk_setup[PPC405CR_OPB_CLK], OPB_clk);
1928 /* Setup external clock */
1929 clk_setup(&cpc->clk_setup[PPC405CR_EXT_CLK], EXT_clk);
1930 /* Setup UART clock */
1931 clk_setup(&cpc->clk_setup[PPC405CR_UART_CLK], UART_clk);
1932 }
1933
1934 static uint32_t dcr_read_crcpc (void *opaque, int dcrn)
1935 {
1936 ppc405cr_cpc_t *cpc;
1937 uint32_t ret;
1938
1939 cpc = opaque;
1940 switch (dcrn) {
1941 case PPC405CR_CPC0_PLLMR:
1942 ret = cpc->pllmr;
1943 break;
1944 case PPC405CR_CPC0_CR0:
1945 ret = cpc->cr0;
1946 break;
1947 case PPC405CR_CPC0_CR1:
1948 ret = cpc->cr1;
1949 break;
1950 case PPC405CR_CPC0_PSR:
1951 ret = cpc->psr;
1952 break;
1953 case PPC405CR_CPC0_JTAGID:
1954 ret = cpc->jtagid;
1955 break;
1956 case PPC405CR_CPC0_ER:
1957 ret = cpc->er;
1958 break;
1959 case PPC405CR_CPC0_FR:
1960 ret = cpc->fr;
1961 break;
1962 case PPC405CR_CPC0_SR:
1963 ret = ~(cpc->er | cpc->fr) & 0xFFFF0000;
1964 break;
1965 default:
1966 /* Avoid gcc warning */
1967 ret = 0;
1968 break;
1969 }
1970
1971 return ret;
1972 }
1973
1974 static void dcr_write_crcpc (void *opaque, int dcrn, uint32_t val)
1975 {
1976 ppc405cr_cpc_t *cpc;
1977
1978 cpc = opaque;
1979 switch (dcrn) {
1980 case PPC405CR_CPC0_PLLMR:
1981 cpc->pllmr = val & 0xFFF77C3F;
1982 break;
1983 case PPC405CR_CPC0_CR0:
1984 cpc->cr0 = val & 0x0FFFFFFE;
1985 break;
1986 case PPC405CR_CPC0_CR1:
1987 cpc->cr1 = val & 0x00800000;
1988 break;
1989 case PPC405CR_CPC0_PSR:
1990 /* Read-only */
1991 break;
1992 case PPC405CR_CPC0_JTAGID:
1993 /* Read-only */
1994 break;
1995 case PPC405CR_CPC0_ER:
1996 cpc->er = val & 0xBFFC0000;
1997 break;
1998 case PPC405CR_CPC0_FR:
1999 cpc->fr = val & 0xBFFC0000;
2000 break;
2001 case PPC405CR_CPC0_SR:
2002 /* Read-only */
2003 break;
2004 }
2005 }
2006
2007 static void ppc405cr_cpc_reset (void *opaque)
2008 {
2009 ppc405cr_cpc_t *cpc;
2010 int D;
2011
2012 cpc = opaque;
2013 /* Compute PLLMR value from PSR settings */
2014 cpc->pllmr = 0x80000000;
2015 /* PFWD */
2016 switch ((cpc->psr >> 30) & 3) {
2017 case 0:
2018 /* Bypass */
2019 cpc->pllmr &= ~0x80000000;
2020 break;
2021 case 1:
2022 /* Divide by 3 */
2023 cpc->pllmr |= 5 << 16;
2024 break;
2025 case 2:
2026 /* Divide by 4 */
2027 cpc->pllmr |= 4 << 16;
2028 break;
2029 case 3:
2030 /* Divide by 6 */
2031 cpc->pllmr |= 2 << 16;
2032 break;
2033 }
2034 /* PFBD */
2035 D = (cpc->psr >> 28) & 3;
2036 cpc->pllmr |= (D + 1) << 20;
2037 /* PT */
2038 D = (cpc->psr >> 25) & 7;
2039 switch (D) {
2040 case 0x2:
2041 cpc->pllmr |= 0x13;
2042 break;
2043 case 0x4:
2044 cpc->pllmr |= 0x15;
2045 break;
2046 case 0x5:
2047 cpc->pllmr |= 0x16;
2048 break;
2049 default:
2050 break;
2051 }
2052 /* PDC */
2053 D = (cpc->psr >> 23) & 3;
2054 cpc->pllmr |= D << 26;
2055 /* ODP */
2056 D = (cpc->psr >> 21) & 3;
2057 cpc->pllmr |= D << 10;
2058 /* EBPD */
2059 D = (cpc->psr >> 17) & 3;
2060 cpc->pllmr |= D << 24;
2061 cpc->cr0 = 0x0000003C;
2062 cpc->cr1 = 0x2B0D8800;
2063 cpc->er = 0x00000000;
2064 cpc->fr = 0x00000000;
2065 ppc405cr_clk_setup(cpc);
2066 }
2067
2068 static void ppc405cr_clk_init (ppc405cr_cpc_t *cpc)
2069 {
2070 int D;
2071
2072 /* XXX: this should be read from IO pins */
2073 cpc->psr = 0x00000000; /* 8 bits ROM */
2074 /* PFWD */
2075 D = 0x2; /* Divide by 4 */
2076 cpc->psr |= D << 30;
2077 /* PFBD */
2078 D = 0x1; /* Divide by 2 */
2079 cpc->psr |= D << 28;
2080 /* PDC */
2081 D = 0x1; /* Divide by 2 */
2082 cpc->psr |= D << 23;
2083 /* PT */
2084 D = 0x5; /* M = 16 */
2085 cpc->psr |= D << 25;
2086 /* ODP */
2087 D = 0x1; /* Divide by 2 */
2088 cpc->psr |= D << 21;
2089 /* EBDP */
2090 D = 0x2; /* Divide by 4 */
2091 cpc->psr |= D << 17;
2092 }
2093
2094 static void ppc405cr_cpc_init (CPUState *env, clk_setup_t clk_setup[7],
2095 uint32_t sysclk)
2096 {
2097 ppc405cr_cpc_t *cpc;
2098
2099 cpc = qemu_mallocz(sizeof(ppc405cr_cpc_t));
2100 memcpy(cpc->clk_setup, clk_setup,
2101 PPC405CR_CLK_NB * sizeof(clk_setup_t));
2102 cpc->sysclk = sysclk;
2103 cpc->jtagid = 0x42051049;
2104 ppc_dcr_register(env, PPC405CR_CPC0_PSR, cpc,
2105 &dcr_read_crcpc, &dcr_write_crcpc);
2106 ppc_dcr_register(env, PPC405CR_CPC0_CR0, cpc,
2107 &dcr_read_crcpc, &dcr_write_crcpc);
2108 ppc_dcr_register(env, PPC405CR_CPC0_CR1, cpc,
2109 &dcr_read_crcpc, &dcr_write_crcpc);
2110 ppc_dcr_register(env, PPC405CR_CPC0_JTAGID, cpc,
2111 &dcr_read_crcpc, &dcr_write_crcpc);
2112 ppc_dcr_register(env, PPC405CR_CPC0_PLLMR, cpc,
2113 &dcr_read_crcpc, &dcr_write_crcpc);
2114 ppc_dcr_register(env, PPC405CR_CPC0_ER, cpc,
2115 &dcr_read_crcpc, &dcr_write_crcpc);
2116 ppc_dcr_register(env, PPC405CR_CPC0_FR, cpc,
2117 &dcr_read_crcpc, &dcr_write_crcpc);
2118 ppc_dcr_register(env, PPC405CR_CPC0_SR, cpc,
2119 &dcr_read_crcpc, &dcr_write_crcpc);
2120 ppc405cr_clk_init(cpc);
2121 qemu_register_reset(ppc405cr_cpc_reset, cpc);
2122 }
2123
2124 CPUState *ppc405cr_init (target_phys_addr_t ram_bases[4],
2125 target_phys_addr_t ram_sizes[4],
2126 uint32_t sysclk, qemu_irq **picp,
2127 int do_init)
2128 {
2129 clk_setup_t clk_setup[PPC405CR_CLK_NB];
2130 qemu_irq dma_irqs[4];
2131 CPUState *env;
2132 qemu_irq *pic, *irqs;
2133
2134 memset(clk_setup, 0, sizeof(clk_setup));
2135 env = ppc4xx_init("405cr", &clk_setup[PPC405CR_CPU_CLK],
2136 &clk_setup[PPC405CR_TMR_CLK], sysclk);
2137 /* Memory mapped devices registers */
2138 /* PLB arbitrer */
2139 ppc4xx_plb_init(env);
2140 /* PLB to OPB bridge */
2141 ppc4xx_pob_init(env);
2142 /* OBP arbitrer */
2143 ppc4xx_opba_init(0xef600600);
2144 /* Universal interrupt controller */
2145 irqs = qemu_mallocz(sizeof(qemu_irq) * PPCUIC_OUTPUT_NB);
2146 irqs[PPCUIC_OUTPUT_INT] =
2147 ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_INT];
2148 irqs[PPCUIC_OUTPUT_CINT] =
2149 ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_CINT];
2150 pic = ppcuic_init(env, irqs, 0x0C0, 0, 1);
2151 *picp = pic;
2152 /* SDRAM controller */
2153 ppc4xx_sdram_init(env, pic[14], 1, ram_bases, ram_sizes, do_init);
2154 /* External bus controller */
2155 ppc405_ebc_init(env);
2156 /* DMA controller */
2157 dma_irqs[0] = pic[26];
2158 dma_irqs[1] = pic[25];
2159 dma_irqs[2] = pic[24];
2160 dma_irqs[3] = pic[23];
2161 ppc405_dma_init(env, dma_irqs);
2162 /* Serial ports */
2163 if (serial_hds[0] != NULL) {
2164 serial_mm_init(0xef600300, 0, pic[0], PPC_SERIAL_MM_BAUDBASE,
2165 serial_hds[0], 1, 1);
2166 }
2167 if (serial_hds[1] != NULL) {
2168 serial_mm_init(0xef600400, 0, pic[1], PPC_SERIAL_MM_BAUDBASE,
2169 serial_hds[1], 1, 1);
2170 }
2171 /* IIC controller */
2172 ppc405_i2c_init(0xef600500, pic[2]);
2173 /* GPIO */
2174 ppc405_gpio_init(0xef600700);
2175 /* CPU control */
2176 ppc405cr_cpc_init(env, clk_setup, sysclk);
2177
2178 return env;
2179 }
2180
2181 /*****************************************************************************/
2182 /* PowerPC 405EP */
2183 /* CPU control */
2184 enum {
2185 PPC405EP_CPC0_PLLMR0 = 0x0F0,
2186 PPC405EP_CPC0_BOOT = 0x0F1,
2187 PPC405EP_CPC0_EPCTL = 0x0F3,
2188 PPC405EP_CPC0_PLLMR1 = 0x0F4,
2189 PPC405EP_CPC0_UCR = 0x0F5,
2190 PPC405EP_CPC0_SRR = 0x0F6,
2191 PPC405EP_CPC0_JTAGID = 0x0F7,
2192 PPC405EP_CPC0_PCI = 0x0F9,
2193 #if 0
2194 PPC405EP_CPC0_ER = xxx,
2195 PPC405EP_CPC0_FR = xxx,
2196 PPC405EP_CPC0_SR = xxx,
2197 #endif
2198 };
2199
2200 enum {
2201 PPC405EP_CPU_CLK = 0,
2202 PPC405EP_PLB_CLK = 1,
2203 PPC405EP_OPB_CLK = 2,
2204 PPC405EP_EBC_CLK = 3,
2205 PPC405EP_MAL_CLK = 4,
2206 PPC405EP_PCI_CLK = 5,
2207 PPC405EP_UART0_CLK = 6,
2208 PPC405EP_UART1_CLK = 7,
2209 PPC405EP_CLK_NB = 8,
2210 };
2211
2212 typedef struct ppc405ep_cpc_t ppc405ep_cpc_t;
2213 struct ppc405ep_cpc_t {
2214 uint32_t sysclk;
2215 clk_setup_t clk_setup[PPC405EP_CLK_NB];
2216 uint32_t boot;
2217 uint32_t epctl;
2218 uint32_t pllmr[2];
2219 uint32_t ucr;
2220 uint32_t srr;
2221 uint32_t jtagid;
2222 uint32_t pci;
2223 /* Clock and power management */
2224 uint32_t er;
2225 uint32_t fr;
2226 uint32_t sr;
2227 };
2228
2229 static void ppc405ep_compute_clocks (ppc405ep_cpc_t *cpc)
2230 {
2231 uint32_t CPU_clk, PLB_clk, OPB_clk, EBC_clk, MAL_clk, PCI_clk;
2232 uint32_t UART0_clk, UART1_clk;
2233 uint64_t VCO_out, PLL_out;
2234 int M, D;
2235
2236 VCO_out = 0;
2237 if ((cpc->pllmr[1] & 0x80000000) && !(cpc->pllmr[1] & 0x40000000)) {
2238 M = (((cpc->pllmr[1] >> 20) - 1) & 0xF) + 1; /* FBMUL */
2239 #ifdef DEBUG_CLOCKS_LL
2240 printf("FBMUL %01" PRIx32 " %d\n", (cpc->pllmr[1] >> 20) & 0xF, M);
2241 #endif
2242 D = 8 - ((cpc->pllmr[1] >> 16) & 0x7); /* FWDA */
2243 #ifdef DEBUG_CLOCKS_LL
2244 printf("FWDA %01" PRIx32 " %d\n", (cpc->pllmr[1] >> 16) & 0x7, D);
2245 #endif
2246 VCO_out = cpc->sysclk * M * D;
2247 if (VCO_out < 500000000UL || VCO_out > 1000000000UL) {
2248 /* Error - unlock the PLL */
2249 printf("VCO out of range %" PRIu64 "\n", VCO_out);
2250 #if 0
2251 cpc->pllmr[1] &= ~0x80000000;
2252 goto pll_bypass;
2253 #endif
2254 }
2255 PLL_out = VCO_out / D;
2256 /* Pretend the PLL is locked */
2257 cpc->boot |= 0x00000001;
2258 } else {
2259 #if 0
2260 pll_bypass:
2261 #endif
2262 PLL_out = cpc->sysclk;
2263 if (cpc->pllmr[1] & 0x40000000) {
2264 /* Pretend the PLL is not locked */
2265 cpc->boot &= ~0x00000001;
2266 }
2267 }
2268 /* Now, compute all other clocks */
2269 D = ((cpc->pllmr[0] >> 20) & 0x3) + 1; /* CCDV */
2270 #ifdef DEBUG_CLOCKS_LL
2271 printf("CCDV %01" PRIx32 " %d\n", (cpc->pllmr[0] >> 20) & 0x3, D);
2272 #endif
2273 CPU_clk = PLL_out / D;
2274 D = ((cpc->pllmr[0] >> 16) & 0x3) + 1; /* CBDV */
2275 #ifdef DEBUG_CLOCKS_LL
2276 printf("CBDV %01" PRIx32 " %d\n", (cpc->pllmr[0] >> 16) & 0x3, D);
2277 #endif
2278 PLB_clk = CPU_clk / D;
2279 D = ((cpc->pllmr[0] >> 12) & 0x3) + 1; /* OPDV */
2280 #ifdef DEBUG_CLOCKS_LL
2281 printf("OPDV %01" PRIx32 " %d\n", (cpc->pllmr[0] >> 12) & 0x3, D);
2282 #endif
2283 OPB_clk = PLB_clk / D;
2284 D = ((cpc->pllmr[0] >> 8) & 0x3) + 2; /* EPDV */
2285 #ifdef DEBUG_CLOCKS_LL
2286 printf("EPDV %01" PRIx32 " %d\n", (cpc->pllmr[0] >> 8) & 0x3, D);
2287 #endif
2288 EBC_clk = PLB_clk / D;
2289 D = ((cpc->pllmr[0] >> 4) & 0x3) + 1; /* MPDV */
2290 #ifdef DEBUG_CLOCKS_LL
2291 printf("MPDV %01" PRIx32 " %d\n", (cpc->pllmr[0] >> 4) & 0x3, D);
2292 #endif
2293 MAL_clk = PLB_clk / D;
2294 D = (cpc->pllmr[0] & 0x3) + 1; /* PPDV */
2295 #ifdef DEBUG_CLOCKS_LL
2296 printf("PPDV %01" PRIx32 " %d\n", cpc->pllmr[0] & 0x3, D);
2297 #endif
2298 PCI_clk = PLB_clk / D;
2299 D = ((cpc->ucr - 1) & 0x7F) + 1; /* U0DIV */
2300 #ifdef DEBUG_CLOCKS_LL
2301 printf("U0DIV %01" PRIx32 " %d\n", cpc->ucr & 0x7F, D);
2302 #endif
2303 UART0_clk = PLL_out / D;
2304 D = (((cpc->ucr >> 8) - 1) & 0x7F) + 1; /* U1DIV */
2305 #ifdef DEBUG_CLOCKS_LL
2306 printf("U1DIV %01" PRIx32 " %d\n", (cpc->ucr >> 8) & 0x7F, D);
2307 #endif
2308 UART1_clk = PLL_out / D;
2309 #ifdef DEBUG_CLOCKS
2310 printf("Setup PPC405EP clocks - sysclk %" PRIu32 " VCO %" PRIu64
2311 " PLL out %" PRIu64 " Hz\n", cpc->sysclk, VCO_out, PLL_out);
2312 printf("CPU %" PRIu32 " PLB %" PRIu32 " OPB %" PRIu32 " EBC %" PRIu32
2313 " MAL %" PRIu32 " PCI %" PRIu32 " UART0 %" PRIu32
2314 " UART1 %" PRIu32 "\n",
2315 CPU_clk, PLB_clk, OPB_clk, EBC_clk, MAL_clk, PCI_clk,
2316 UART0_clk, UART1_clk);
2317 #endif
2318 /* Setup CPU clocks */
2319 clk_setup(&cpc->clk_setup[PPC405EP_CPU_CLK], CPU_clk);
2320 /* Setup PLB clock */
2321 clk_setup(&cpc->clk_setup[PPC405EP_PLB_CLK], PLB_clk);
2322 /* Setup OPB clock */
2323 clk_setup(&cpc->clk_setup[PPC405EP_OPB_CLK], OPB_clk);
2324 /* Setup external clock */
2325 clk_setup(&cpc->clk_setup[PPC405EP_EBC_CLK], EBC_clk);
2326 /* Setup MAL clock */
2327 clk_setup(&cpc->clk_setup[PPC405EP_MAL_CLK], MAL_clk);
2328 /* Setup PCI clock */
2329 clk_setup(&cpc->clk_setup[PPC405EP_PCI_CLK], PCI_clk);
2330 /* Setup UART0 clock */
2331 clk_setup(&cpc->clk_setup[PPC405EP_UART0_CLK], UART0_clk);
2332 /* Setup UART1 clock */
2333 clk_setup(&cpc->clk_setup[PPC405EP_UART1_CLK], UART1_clk);
2334 }
2335
2336 static uint32_t dcr_read_epcpc (void *opaque, int dcrn)
2337 {
2338 ppc405ep_cpc_t *cpc;
2339 uint32_t ret;
2340
2341 cpc = opaque;
2342 switch (dcrn) {
2343 case PPC405EP_CPC0_BOOT:
2344 ret = cpc->boot;
2345 break;
2346 case PPC405EP_CPC0_EPCTL:
2347 ret = cpc->epctl;
2348 break;
2349 case PPC405EP_CPC0_PLLMR0:
2350 ret = cpc->pllmr[0];
2351 break;
2352 case PPC405EP_CPC0_PLLMR1:
2353 ret = cpc->pllmr[1];
2354 break;
2355 case PPC405EP_CPC0_UCR:
2356 ret = cpc->ucr;
2357 break;
2358 case PPC405EP_CPC0_SRR:
2359 ret = cpc->srr;
2360 break;
2361 case PPC405EP_CPC0_JTAGID:
2362 ret = cpc->jtagid;
2363 break;
2364 case PPC405EP_CPC0_PCI:
2365 ret = cpc->pci;
2366 break;
2367 default:
2368 /* Avoid gcc warning */
2369 ret = 0;
2370 break;
2371 }
2372
2373 return ret;
2374 }
2375
2376 static void dcr_write_epcpc (void *opaque, int dcrn, uint32_t val)
2377 {
2378 ppc405ep_cpc_t *cpc;
2379
2380 cpc = opaque;
2381 switch (dcrn) {
2382 case PPC405EP_CPC0_BOOT:
2383 /* Read-only register */
2384 break;
2385 case PPC405EP_CPC0_EPCTL:
2386 /* Don't care for now */
2387 cpc->epctl = val & 0xC00000F3;
2388 break;
2389 case PPC405EP_CPC0_PLLMR0:
2390 cpc->pllmr[0] = val & 0x00633333;
2391 ppc405ep_compute_clocks(cpc);
2392 break;
2393 case PPC405EP_CPC0_PLLMR1:
2394 cpc->pllmr[1] = val & 0xC0F73FFF;
2395 ppc405ep_compute_clocks(cpc);
2396 break;
2397 case PPC405EP_CPC0_UCR:
2398 /* UART control - don't care for now */
2399 cpc->ucr = val & 0x003F7F7F;
2400 break;
2401 case PPC405EP_CPC0_SRR:
2402 cpc->srr = val;
2403 break;
2404 case PPC405EP_CPC0_JTAGID:
2405 /* Read-only */
2406 break;
2407 case PPC405EP_CPC0_PCI:
2408 cpc->pci = val;
2409 break;
2410 }
2411 }
2412
2413 static void ppc405ep_cpc_reset (void *opaque)
2414 {
2415 ppc405ep_cpc_t *cpc = opaque;
2416
2417 cpc->boot = 0x00000010; /* Boot from PCI - IIC EEPROM disabled */
2418 cpc->epctl = 0x00000000;
2419 cpc->pllmr[0] = 0x00011010;
2420 cpc->pllmr[1] = 0x40000000;
2421 cpc->ucr = 0x00000000;
2422 cpc->srr = 0x00040000;
2423 cpc->pci = 0x00000000;
2424 cpc->er = 0x00000000;
2425 cpc->fr = 0x00000000;
2426 cpc->sr = 0x00000000;
2427 ppc405ep_compute_clocks(cpc);
2428 }
2429
2430 /* XXX: sysclk should be between 25 and 100 MHz */
2431 static void ppc405ep_cpc_init (CPUState *env, clk_setup_t clk_setup[8],
2432 uint32_t sysclk)
2433 {
2434 ppc405ep_cpc_t *cpc;
2435
2436 cpc = qemu_mallocz(sizeof(ppc405ep_cpc_t));
2437 memcpy(cpc->clk_setup, clk_setup,
2438 PPC405EP_CLK_NB * sizeof(clk_setup_t));
2439 cpc->jtagid = 0x20267049;
2440 cpc->sysclk = sysclk;
2441 qemu_register_reset(&ppc405ep_cpc_reset, cpc);
2442 ppc_dcr_register(env, PPC405EP_CPC0_BOOT, cpc,
2443 &dcr_read_epcpc, &dcr_write_epcpc);
2444 ppc_dcr_register(env, PPC405EP_CPC0_EPCTL, cpc,
2445 &dcr_read_epcpc, &dcr_write_epcpc);
2446 ppc_dcr_register(env, PPC405EP_CPC0_PLLMR0, cpc,
2447 &dcr_read_epcpc, &dcr_write_epcpc);
2448 ppc_dcr_register(env, PPC405EP_CPC0_PLLMR1, cpc,
2449 &dcr_read_epcpc, &dcr_write_epcpc);
2450 ppc_dcr_register(env, PPC405EP_CPC0_UCR, cpc,
2451 &dcr_read_epcpc, &dcr_write_epcpc);
2452 ppc_dcr_register(env, PPC405EP_CPC0_SRR, cpc,
2453 &dcr_read_epcpc, &dcr_write_epcpc);
2454 ppc_dcr_register(env, PPC405EP_CPC0_JTAGID, cpc,
2455 &dcr_read_epcpc, &dcr_write_epcpc);
2456 ppc_dcr_register(env, PPC405EP_CPC0_PCI, cpc,
2457 &dcr_read_epcpc, &dcr_write_epcpc);
2458 #if 0
2459 ppc_dcr_register(env, PPC405EP_CPC0_ER, cpc,
2460 &dcr_read_epcpc, &dcr_write_epcpc);
2461 ppc_dcr_register(env, PPC405EP_CPC0_FR, cpc,
2462 &dcr_read_epcpc, &dcr_write_epcpc);
2463 ppc_dcr_register(env, PPC405EP_CPC0_SR, cpc,
2464 &dcr_read_epcpc, &dcr_write_epcpc);
2465 #endif
2466 }
2467
2468 CPUState *ppc405ep_init (target_phys_addr_t ram_bases[2],
2469 target_phys_addr_t ram_sizes[2],
2470 uint32_t sysclk, qemu_irq **picp,
2471 int do_init)
2472 {
2473 clk_setup_t clk_setup[PPC405EP_CLK_NB], tlb_clk_setup;
2474 qemu_irq dma_irqs[4], gpt_irqs[5], mal_irqs[4];
2475 CPUState *env;
2476 qemu_irq *pic, *irqs;
2477
2478 memset(clk_setup, 0, sizeof(clk_setup));
2479 /* init CPUs */
2480 env = ppc4xx_init("405ep", &clk_setup[PPC405EP_CPU_CLK],
2481 &tlb_clk_setup, sysclk);
2482 clk_setup[PPC405EP_CPU_CLK].cb = tlb_clk_setup.cb;
2483 clk_setup[PPC405EP_CPU_CLK].opaque = tlb_clk_setup.opaque;
2484 /* Internal devices init */
2485 /* Memory mapped devices registers */
2486 /* PLB arbitrer */
2487 ppc4xx_plb_init(env);
2488 /* PLB to OPB bridge */
2489 ppc4xx_pob_init(env);
2490 /* OBP arbitrer */
2491 ppc4xx_opba_init(0xef600600);
2492 /* Universal interrupt controller */
2493 irqs = qemu_mallocz(sizeof(qemu_irq) * PPCUIC_OUTPUT_NB);
2494 irqs[PPCUIC_OUTPUT_INT] =
2495 ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_INT];
2496 irqs[PPCUIC_OUTPUT_CINT] =
2497 ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_CINT];
2498 pic = ppcuic_init(env, irqs, 0x0C0, 0, 1);
2499 *picp = pic;
2500 /* SDRAM controller */
2501 /* XXX 405EP has no ECC interrupt */
2502 ppc4xx_sdram_init(env, pic[17], 2, ram_bases, ram_sizes, do_init);
2503 /* External bus controller */
2504 ppc405_ebc_init(env);
2505 /* DMA controller */
2506 dma_irqs[0] = pic[5];
2507 dma_irqs[1] = pic[6];
2508 dma_irqs[2] = pic[7];
2509 dma_irqs[3] = pic[8];
2510 ppc405_dma_init(env, dma_irqs);
2511 /* IIC controller */
2512 ppc405_i2c_init(0xef600500, pic[2]);
2513 /* GPIO */
2514 ppc405_gpio_init(0xef600700);
2515 /* Serial ports */
2516 if (serial_hds[0] != NULL) {
2517 serial_mm_init(0xef600300, 0, pic[0], PPC_SERIAL_MM_BAUDBASE,
2518 serial_hds[0], 1, 1);
2519 }
2520 if (serial_hds[1] != NULL) {
2521 serial_mm_init(0xef600400, 0, pic[1], PPC_SERIAL_MM_BAUDBASE,
2522 serial_hds[1], 1, 1);
2523 }
2524 /* OCM */
2525 ppc405_ocm_init(env);
2526 /* GPT */
2527 gpt_irqs[0] = pic[19];
2528 gpt_irqs[1] = pic[20];
2529 gpt_irqs[2] = pic[21];
2530 gpt_irqs[3] = pic[22];
2531 gpt_irqs[4] = pic[23];
2532 ppc4xx_gpt_init(0xef600000, gpt_irqs);
2533 /* PCI */
2534 /* Uses pic[3], pic[16], pic[18] */
2535 /* MAL */
2536 mal_irqs[0] = pic[11];
2537 mal_irqs[1] = pic[12];
2538 mal_irqs[2] = pic[13];
2539 mal_irqs[3] = pic[14];
2540 ppc405_mal_init(env, mal_irqs);
2541 /* Ethernet */
2542 /* Uses pic[9], pic[15], pic[17] */
2543 /* CPU control */
2544 ppc405ep_cpc_init(env, clk_setup, sysclk);
2545
2546 return env;
2547 }
Anthony Liguori's QEMU tree