hw/ppc_prep.c

   1 /*
   2  * QEMU PPC PREP hardware System Emulator
   3  *
   4  * Copyright (c) 2003-2007 Jocelyn Mayer
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "hw.h"
  25 #include "nvram.h"
  26 #include "pc.h"
  27 #include "fdc.h"
  28 #include "net.h"
  29 #include "sysemu.h"
  30 #include "isa.h"
  31 #include "pci.h"
  32 #include "prep_pci.h"
  33 #include "usb-ohci.h"
  34 #include "ppc.h"
  35 #include "boards.h"
  36 #include "qemu-log.h"
  37 #include "ide.h"
  38 #include "loader.h"
  39 #include "mc146818rtc.h"
  40 #include "blockdev.h"
  41 #include "exec-memory.h"
  42
  43 //#define HARD_DEBUG_PPC_IO
  44 //#define DEBUG_PPC_IO
  45
  46 /* SMP is not enabled, for now */
  47 #define MAX_CPUS 1
  48
  49 #define MAX_IDE_BUS 2
  50
  51 #define BIOS_SIZE (1024 * 1024)
  52 #define BIOS_FILENAME "ppc_rom.bin"
  53 #define KERNEL_LOAD_ADDR 0x01000000
  54 #define INITRD_LOAD_ADDR 0x01800000
  55
  56 #if defined (HARD_DEBUG_PPC_IO) && !defined (DEBUG_PPC_IO)
  57 #define DEBUG_PPC_IO
  58 #endif
  59
  60 #if defined (HARD_DEBUG_PPC_IO)
  61 #define PPC_IO_DPRINTF(fmt, ...)                         \
  62 do {                                                     \
  63     if (qemu_loglevel_mask(CPU_LOG_IOPORT)) {            \
  64         qemu_log("%s: " fmt, __func__ , ## __VA_ARGS__); \
  65     } else {                                             \
  66         printf("%s : " fmt, __func__ , ## __VA_ARGS__);  \
  67     }                                                    \
  68 } while (0)
  69 #elif defined (DEBUG_PPC_IO)
  70 #define PPC_IO_DPRINTF(fmt, ...) \
  71 qemu_log_mask(CPU_LOG_IOPORT, fmt, ## __VA_ARGS__)
  72 #else
  73 #define PPC_IO_DPRINTF(fmt, ...) do { } while (0)
  74 #endif
  75
  76 /* Constants for devices init */
  77 static const int ide_iobase[2] = { 0x1f0, 0x170 };
  78 static const int ide_iobase2[2] = { 0x3f6, 0x376 };
  79 static const int ide_irq[2] = { 13, 13 };
  80
  81 #define NE2000_NB_MAX 6
  82
  83 static uint32_t ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, 0x280, 0x380 };
  84 static int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 };
  85
  86 //static ISADevice *pit;
  87
  88 /* ISA IO ports bridge */
  89 #define PPC_IO_BASE 0x80000000
  90
  91 #if 0
  92 /* Speaker port 0x61 */
  93 static int speaker_data_on;
  94 static int dummy_refresh_clock;
  95 #endif
  96
  97 static void speaker_ioport_write (void *opaque, uint32_t addr, uint32_t val)
  98 {
  99 #if 0
 100     speaker_data_on = (val >> 1) & 1;
 101     pit_set_gate(pit, 2, val & 1);
 102 #endif
 103 }
 104
 105 static uint32_t speaker_ioport_read (void *opaque, uint32_t addr)
 106 {
 107 #if 0
 108     int out;
 109     out = pit_get_out(pit, 2, qemu_get_clock_ns(vm_clock));
 110     dummy_refresh_clock ^= 1;
 111     return (speaker_data_on << 1) | pit_get_gate(pit, 2) | (out << 5) |
 112         (dummy_refresh_clock << 4);
 113 #endif
 114     return 0;
 115 }
 116
 117 /* PCI intack register */
 118 /* Read-only register (?) */
 119 static void _PPC_intack_write (void *opaque,
 120                                target_phys_addr_t addr, uint32_t value)
 121 {
 122 #if 0
 123     printf("%s: 0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", __func__, addr,
 124            value);
 125 #endif
 126 }
 127
 128 static inline uint32_t _PPC_intack_read(target_phys_addr_t addr)
 129 {
 130     uint32_t retval = 0;
 131
 132     if ((addr & 0xf) == 0)
 133         retval = pic_intack_read(isa_pic);
 134 #if 0
 135     printf("%s: 0x" TARGET_FMT_plx " <= %08" PRIx32 "\n", __func__, addr,
 136            retval);
 137 #endif
 138
 139     return retval;
 140 }
 141
 142 static uint32_t PPC_intack_readb (void *opaque, target_phys_addr_t addr)
 143 {
 144     return _PPC_intack_read(addr);
 145 }
 146
 147 static uint32_t PPC_intack_readw (void *opaque, target_phys_addr_t addr)
 148 {
 149     return _PPC_intack_read(addr);
 150 }
 151
 152 static uint32_t PPC_intack_readl (void *opaque, target_phys_addr_t addr)
 153 {
 154     return _PPC_intack_read(addr);
 155 }
 156
 157 static CPUWriteMemoryFunc * const PPC_intack_write[] = {
 158     &_PPC_intack_write,
 159     &_PPC_intack_write,
 160     &_PPC_intack_write,
 161 };
 162
 163 static CPUReadMemoryFunc * const PPC_intack_read[] = {
 164     &PPC_intack_readb,
 165     &PPC_intack_readw,
 166     &PPC_intack_readl,
 167 };
 168
 169 /* PowerPC control and status registers */
 170 #if 0 // Not used
 171 static struct {
 172     /* IDs */
 173     uint32_t veni_devi;
 174     uint32_t revi;
 175     /* Control and status */
 176     uint32_t gcsr;
 177     uint32_t xcfr;
 178     uint32_t ct32;
 179     uint32_t mcsr;
 180     /* General purpose registers */
 181     uint32_t gprg[6];
 182     /* Exceptions */
 183     uint32_t feen;
 184     uint32_t fest;
 185     uint32_t fema;
 186     uint32_t fecl;
 187     uint32_t eeen;
 188     uint32_t eest;
 189     uint32_t eecl;
 190     uint32_t eeint;
 191     uint32_t eemck0;
 192     uint32_t eemck1;
 193     /* Error diagnostic */
 194 } XCSR;
 195
 196 static void PPC_XCSR_writeb (void *opaque,
 197                              target_phys_addr_t addr, uint32_t value)
 198 {
 199     printf("%s: 0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", __func__, addr,
 200            value);
 201 }
 202
 203 static void PPC_XCSR_writew (void *opaque,
 204                              target_phys_addr_t addr, uint32_t value)
 205 {
 206     printf("%s: 0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", __func__, addr,
 207            value);
 208 }
 209
 210 static void PPC_XCSR_writel (void *opaque,
 211                              target_phys_addr_t addr, uint32_t value)
 212 {
 213     printf("%s: 0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", __func__, addr,
 214            value);
 215 }
 216
 217 static uint32_t PPC_XCSR_readb (void *opaque, target_phys_addr_t addr)
 218 {
 219     uint32_t retval = 0;
 220
 221     printf("%s: 0x" TARGET_FMT_plx " <= %08" PRIx32 "\n", __func__, addr,
 222            retval);
 223
 224     return retval;
 225 }
 226
 227 static uint32_t PPC_XCSR_readw (void *opaque, target_phys_addr_t addr)
 228 {
 229     uint32_t retval = 0;
 230
 231     printf("%s: 0x" TARGET_FMT_plx " <= %08" PRIx32 "\n", __func__, addr,
 232            retval);
 233
 234     return retval;
 235 }
 236
 237 static uint32_t PPC_XCSR_readl (void *opaque, target_phys_addr_t addr)
 238 {
 239     uint32_t retval = 0;
 240
 241     printf("%s: 0x" TARGET_FMT_plx " <= %08" PRIx32 "\n", __func__, addr,
 242            retval);
 243
 244     return retval;
 245 }
 246
 247 static CPUWriteMemoryFunc * const PPC_XCSR_write[] = {
 248     &PPC_XCSR_writeb,
 249     &PPC_XCSR_writew,
 250     &PPC_XCSR_writel,
 251 };
 252
 253 static CPUReadMemoryFunc * const PPC_XCSR_read[] = {
 254     &PPC_XCSR_readb,
 255     &PPC_XCSR_readw,
 256     &PPC_XCSR_readl,
 257 };
 258 #endif
 259
 260 /* Fake super-io ports for PREP platform (Intel 82378ZB) */
 261 typedef struct sysctrl_t {
 262     qemu_irq reset_irq;
 263     M48t59State *nvram;
 264     uint8_t state;
 265     uint8_t syscontrol;
 266     uint8_t fake_io[2];
 267     int contiguous_map;
 268     int endian;
 269 } sysctrl_t;
 270
 271 enum {
 272     STATE_HARDFILE = 0x01,
 273 };
 274
 275 static sysctrl_t *sysctrl;
 276
 277 static void PREP_io_write (void *opaque, uint32_t addr, uint32_t val)
 278 {
 279     sysctrl_t *sysctrl = opaque;
 280
 281     PPC_IO_DPRINTF("0x%08" PRIx32 " => 0x%02" PRIx32 "\n", addr - PPC_IO_BASE,
 282                    val);
 283     sysctrl->fake_io[addr - 0x0398] = val;
 284 }
 285
 286 static uint32_t PREP_io_read (void *opaque, uint32_t addr)
 287 {
 288     sysctrl_t *sysctrl = opaque;
 289
 290     PPC_IO_DPRINTF("0x%08" PRIx32 " <= 0x%02" PRIx32 "\n", addr - PPC_IO_BASE,
 291                    sysctrl->fake_io[addr - 0x0398]);
 292     return sysctrl->fake_io[addr - 0x0398];
 293 }
 294
 295 static void PREP_io_800_writeb (void *opaque, uint32_t addr, uint32_t val)
 296 {
 297     sysctrl_t *sysctrl = opaque;
 298
 299     PPC_IO_DPRINTF("0x%08" PRIx32 " => 0x%02" PRIx32 "\n",
 300                    addr - PPC_IO_BASE, val);
 301     switch (addr) {
 302     case 0x0092:
 303         /* Special port 92 */
 304         /* Check soft reset asked */
 305         if (val & 0x01) {
 306             qemu_irq_raise(sysctrl->reset_irq);
 307         } else {
 308             qemu_irq_lower(sysctrl->reset_irq);
 309         }
 310         /* Check LE mode */
 311         if (val & 0x02) {
 312             sysctrl->endian = 1;
 313         } else {
 314             sysctrl->endian = 0;
 315         }
 316         break;
 317     case 0x0800:
 318         /* Motorola CPU configuration register : read-only */
 319         break;
 320     case 0x0802:
 321         /* Motorola base module feature register : read-only */
 322         break;
 323     case 0x0803:
 324         /* Motorola base module status register : read-only */
 325         break;
 326     case 0x0808:
 327         /* Hardfile light register */
 328         if (val & 1)
 329             sysctrl->state |= STATE_HARDFILE;
 330         else
 331             sysctrl->state &= ~STATE_HARDFILE;
 332         break;
 333     case 0x0810:
 334         /* Password protect 1 register */
 335         if (sysctrl->nvram != NULL)
 336             m48t59_toggle_lock(sysctrl->nvram, 1);
 337         break;
 338     case 0x0812:
 339         /* Password protect 2 register */
 340         if (sysctrl->nvram != NULL)
 341             m48t59_toggle_lock(sysctrl->nvram, 2);
 342         break;
 343     case 0x0814:
 344         /* L2 invalidate register */
 345         //        tlb_flush(first_cpu, 1);
 346         break;
 347     case 0x081C:
 348         /* system control register */
 349         sysctrl->syscontrol = val & 0x0F;
 350         break;
 351     case 0x0850:
 352         /* I/O map type register */
 353         sysctrl->contiguous_map = val & 0x01;
 354         break;
 355     default:
 356         printf("ERROR: unaffected IO port write: %04" PRIx32
 357                " => %02" PRIx32"\n", addr, val);
 358         break;
 359     }
 360 }
 361
 362 static uint32_t PREP_io_800_readb (void *opaque, uint32_t addr)
 363 {
 364     sysctrl_t *sysctrl = opaque;
 365     uint32_t retval = 0xFF;
 366
 367     switch (addr) {
 368     case 0x0092:
 369         /* Special port 92 */
 370         retval = 0x00;
 371         break;
 372     case 0x0800:
 373         /* Motorola CPU configuration register */
 374         retval = 0xEF; /* MPC750 */
 375         break;
 376     case 0x0802:
 377         /* Motorola Base module feature register */
 378         retval = 0xAD; /* No ESCC, PMC slot neither ethernet */
 379         break;
 380     case 0x0803:
 381         /* Motorola base module status register */
 382         retval = 0xE0; /* Standard MPC750 */
 383         break;
 384     case 0x080C:
 385         /* Equipment present register:
 386          *  no L2 cache
 387          *  no upgrade processor
 388          *  no cards in PCI slots
 389          *  SCSI fuse is bad
 390          */
 391         retval = 0x3C;
 392         break;
 393     case 0x0810:
 394         /* Motorola base module extended feature register */
 395         retval = 0x39; /* No USB, CF and PCI bridge. NVRAM present */
 396         break;
 397     case 0x0814:
 398         /* L2 invalidate: don't care */
 399         break;
 400     case 0x0818:
 401         /* Keylock */
 402         retval = 0x00;
 403         break;
 404     case 0x081C:
 405         /* system control register
 406          * 7 - 6 / 1 - 0: L2 cache enable
 407          */
 408         retval = sysctrl->syscontrol;
 409         break;
 410     case 0x0823:
 411         /* */
 412         retval = 0x03; /* no L2 cache */
 413         break;
 414     case 0x0850:
 415         /* I/O map type register */
 416         retval = sysctrl->contiguous_map;
 417         break;
 418     default:
 419         printf("ERROR: unaffected IO port: %04" PRIx32 " read\n", addr);
 420         break;
 421     }
 422     PPC_IO_DPRINTF("0x%08" PRIx32 " <= 0x%02" PRIx32 "\n",
 423                    addr - PPC_IO_BASE, retval);
 424
 425     return retval;
 426 }
 427
 428 static inline target_phys_addr_t prep_IO_address(sysctrl_t *sysctrl,
 429                                                  target_phys_addr_t addr)
 430 {
 431     if (sysctrl->contiguous_map == 0) {
 432         /* 64 KB contiguous space for IOs */
 433         addr &= 0xFFFF;
 434     } else {
 435         /* 8 MB non-contiguous space for IOs */
 436         addr = (addr & 0x1F) | ((addr & 0x007FFF000) >> 7);
 437     }
 438
 439     return addr;
 440 }
 441
 442 static void PPC_prep_io_writeb (void *opaque, target_phys_addr_t addr,
 443                                 uint32_t value)
 444 {
 445     sysctrl_t *sysctrl = opaque;
 446
 447     addr = prep_IO_address(sysctrl, addr);
 448     cpu_outb(addr, value);
 449 }
 450
 451 static uint32_t PPC_prep_io_readb (void *opaque, target_phys_addr_t addr)
 452 {
 453     sysctrl_t *sysctrl = opaque;
 454     uint32_t ret;
 455
 456     addr = prep_IO_address(sysctrl, addr);
 457     ret = cpu_inb(addr);
 458
 459     return ret;
 460 }
 461
 462 static void PPC_prep_io_writew (void *opaque, target_phys_addr_t addr,
 463                                 uint32_t value)
 464 {
 465     sysctrl_t *sysctrl = opaque;
 466
 467     addr = prep_IO_address(sysctrl, addr);
 468     PPC_IO_DPRINTF("0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", addr, value);
 469     cpu_outw(addr, value);
 470 }
 471
 472 static uint32_t PPC_prep_io_readw (void *opaque, target_phys_addr_t addr)
 473 {
 474     sysctrl_t *sysctrl = opaque;
 475     uint32_t ret;
 476
 477     addr = prep_IO_address(sysctrl, addr);
 478     ret = cpu_inw(addr);
 479     PPC_IO_DPRINTF("0x" TARGET_FMT_plx " <= 0x%08" PRIx32 "\n", addr, ret);
 480
 481     return ret;
 482 }
 483
 484 static void PPC_prep_io_writel (void *opaque, target_phys_addr_t addr,
 485                                 uint32_t value)
 486 {
 487     sysctrl_t *sysctrl = opaque;
 488
 489     addr = prep_IO_address(sysctrl, addr);
 490     PPC_IO_DPRINTF("0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", addr, value);
 491     cpu_outl(addr, value);
 492 }
 493
 494 static uint32_t PPC_prep_io_readl (void *opaque, target_phys_addr_t addr)
 495 {
 496     sysctrl_t *sysctrl = opaque;
 497     uint32_t ret;
 498
 499     addr = prep_IO_address(sysctrl, addr);
 500     ret = cpu_inl(addr);
 501     PPC_IO_DPRINTF("0x" TARGET_FMT_plx " <= 0x%08" PRIx32 "\n", addr, ret);
 502
 503     return ret;
 504 }
 505
 506 static CPUWriteMemoryFunc * const PPC_prep_io_write[] = {
 507     &PPC_prep_io_writeb,
 508     &PPC_prep_io_writew,
 509     &PPC_prep_io_writel,
 510 };
 511
 512 static CPUReadMemoryFunc * const PPC_prep_io_read[] = {
 513     &PPC_prep_io_readb,
 514     &PPC_prep_io_readw,
 515     &PPC_prep_io_readl,
 516 };
 517
 518 #define NVRAM_SIZE        0x2000
 519
 520 static void cpu_request_exit(void *opaque, int irq, int level)
 521 {
 522     CPUState *env = cpu_single_env;
 523
 524     if (env && level) {
 525         cpu_exit(env);
 526     }
 527 }
 528
 529 /* PowerPC PREP hardware initialisation */
 530 static void ppc_prep_init (ram_addr_t ram_size,
 531                            const char *boot_device,
 532                            const char *kernel_filename,
 533                            const char *kernel_cmdline,
 534                            const char *initrd_filename,
 535                            const char *cpu_model)
 536 {
 537     CPUState *env = NULL;
 538     char *filename;
 539     nvram_t nvram;
 540     M48t59State *m48t59;
 541     int PPC_io_memory;
 542     int linux_boot, i, nb_nics1, bios_size;
 543     ram_addr_t ram_offset, bios_offset;
 544     uint32_t kernel_base, initrd_base;
 545     long kernel_size, initrd_size;
 546     PCIBus *pci_bus;
 547     qemu_irq *i8259;
 548     qemu_irq *cpu_exit_irq;
 549     int ppc_boot_device;
 550     DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
 551     DriveInfo *fd[MAX_FD];
 552
 553     sysctrl = qemu_mallocz(sizeof(sysctrl_t));
 554
 555     linux_boot = (kernel_filename != NULL);
 556
 557     /* init CPUs */
 558     if (cpu_model == NULL)
 559         cpu_model = "602";
 560     for (i = 0; i < smp_cpus; i++) {
 561         env = cpu_init(cpu_model);
 562         if (!env) {
 563             fprintf(stderr, "Unable to find PowerPC CPU definition\n");
 564             exit(1);
 565         }
 566         if (env->flags & POWERPC_FLAG_RTC_CLK) {
 567             /* POWER / PowerPC 601 RTC clock frequency is 7.8125 MHz */
 568             cpu_ppc_tb_init(env, 7812500UL);
 569         } else {
 570             /* Set time-base frequency to 100 Mhz */
 571             cpu_ppc_tb_init(env, 100UL * 1000UL * 1000UL);
 572         }
 573         qemu_register_reset((QEMUResetHandler*)&cpu_reset, env);
 574     }
 575
 576     /* allocate RAM */
 577     ram_offset = qemu_ram_alloc(NULL, "ppc_prep.ram", ram_size);
 578     cpu_register_physical_memory(0, ram_size, ram_offset);
 579
 580     /* allocate and load BIOS */
 581     bios_offset = qemu_ram_alloc(NULL, "ppc_prep.bios", BIOS_SIZE);
 582     if (bios_name == NULL)
 583         bios_name = BIOS_FILENAME;
 584     filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
 585     if (filename) {
 586         bios_size = get_image_size(filename);
 587     } else {
 588         bios_size = -1;
 589     }
 590     if (bios_size > 0 && bios_size <= BIOS_SIZE) {
 591         target_phys_addr_t bios_addr;
 592         bios_size = (bios_size + 0xfff) & ~0xfff;
 593         bios_addr = (uint32_t)(-bios_size);
 594         cpu_register_physical_memory(bios_addr, bios_size,
 595                                      bios_offset | IO_MEM_ROM);
 596         bios_size = load_image_targphys(filename, bios_addr, bios_size);
 597     }
 598     if (bios_size < 0 || bios_size > BIOS_SIZE) {
 599         hw_error("qemu: could not load PPC PREP bios '%s'\n", bios_name);
 600     }
 601     if (filename) {
 602         qemu_free(filename);
 603     }
 604
 605     if (linux_boot) {
 606         kernel_base = KERNEL_LOAD_ADDR;
 607         /* now we can load the kernel */
 608         kernel_size = load_image_targphys(kernel_filename, kernel_base,
 609                                           ram_size - kernel_base);
 610         if (kernel_size < 0) {
 611             hw_error("qemu: could not load kernel '%s'\n", kernel_filename);
 612             exit(1);
 613         }
 614         /* load initrd */
 615         if (initrd_filename) {
 616             initrd_base = INITRD_LOAD_ADDR;
 617             initrd_size = load_image_targphys(initrd_filename, initrd_base,
 618                                               ram_size - initrd_base);
 619             if (initrd_size < 0) {
 620                 hw_error("qemu: could not load initial ram disk '%s'\n",
 621                           initrd_filename);
 622             }
 623         } else {
 624             initrd_base = 0;
 625             initrd_size = 0;
 626         }
 627         ppc_boot_device = 'm';
 628     } else {
 629         kernel_base = 0;
 630         kernel_size = 0;
 631         initrd_base = 0;
 632         initrd_size = 0;
 633         ppc_boot_device = '\0';
 634         /* For now, OHW cannot boot from the network. */
 635         for (i = 0; boot_device[i] != '\0'; i++) {
 636             if (boot_device[i] >= 'a' && boot_device[i] <= 'f') {
 637                 ppc_boot_device = boot_device[i];
 638                 break;
 639             }
 640         }
 641         if (ppc_boot_device == '\0') {
 642             fprintf(stderr, "No valid boot device for Mac99 machine\n");
 643             exit(1);
 644         }
 645     }
 646
 647     isa_mem_base = 0xc0000000;
 648     if (PPC_INPUT(env) != PPC_FLAGS_INPUT_6xx) {
 649         hw_error("Only 6xx bus is supported on PREP machine\n");
 650     }
 651     i8259 = i8259_init(first_cpu->irq_inputs[PPC6xx_INPUT_INT]);
 652     pci_bus = pci_prep_init(i8259, get_system_memory(), get_system_io());
 653     /* Hmm, prep has no pci-isa bridge ??? */
 654     isa_bus_new(NULL);
 655     isa_bus_irqs(i8259);
 656     //    pci_bus = i440fx_init();
 657     /* Register 8 MB of ISA IO space (needed for non-contiguous map) */
 658     PPC_io_memory = cpu_register_io_memory(PPC_prep_io_read,
 659                                            PPC_prep_io_write, sysctrl,
 660                                            DEVICE_LITTLE_ENDIAN);
 661     cpu_register_physical_memory(0x80000000, 0x00800000, PPC_io_memory);
 662
 663     /* init basic PC hardware */
 664     pci_vga_init(pci_bus);
 665     //    openpic = openpic_init(0x00000000, 0xF0000000, 1);
 666     //    pit = pit_init(0x40, 0);
 667     rtc_init(2000, NULL);
 668
 669     if (serial_hds[0])
 670         serial_isa_init(0, serial_hds[0]);
 671     nb_nics1 = nb_nics;
 672     if (nb_nics1 > NE2000_NB_MAX)
 673         nb_nics1 = NE2000_NB_MAX;
 674     for(i = 0; i < nb_nics1; i++) {
 675         if (nd_table[i].model == NULL) {
 676             nd_table[i].model = qemu_strdup("ne2k_isa");
 677         }
 678         if (strcmp(nd_table[i].model, "ne2k_isa") == 0) {
 679             isa_ne2000_init(ne2000_io[i], ne2000_irq[i], &nd_table[i]);
 680         } else {
 681             pci_nic_init_nofail(&nd_table[i], "ne2k_pci", NULL);
 682         }
 683     }
 684
 685     ide_drive_get(hd, MAX_IDE_BUS);
 686     for(i = 0; i < MAX_IDE_BUS; i++) {
 687         isa_ide_init(ide_iobase[i], ide_iobase2[i], ide_irq[i],
 688                      hd[2 * i],
 689                      hd[2 * i + 1]);
 690     }
 691     isa_create_simple("i8042");
 692
 693     cpu_exit_irq = qemu_allocate_irqs(cpu_request_exit, NULL, 1);
 694     DMA_init(1, cpu_exit_irq);
 695
 696     //    SB16_init();
 697
 698     for(i = 0; i < MAX_FD; i++) {
 699         fd[i] = drive_get(IF_FLOPPY, 0, i);
 700     }
 701     fdctrl_init_isa(fd);
 702
 703     /* Register speaker port */
 704     register_ioport_read(0x61, 1, 1, speaker_ioport_read, NULL);
 705     register_ioport_write(0x61, 1, 1, speaker_ioport_write, NULL);
 706     /* Register fake IO ports for PREP */
 707     sysctrl->reset_irq = first_cpu->irq_inputs[PPC6xx_INPUT_HRESET];
 708     register_ioport_read(0x398, 2, 1, &PREP_io_read, sysctrl);
 709     register_ioport_write(0x398, 2, 1, &PREP_io_write, sysctrl);
 710     /* System control ports */
 711     register_ioport_read(0x0092, 0x01, 1, &PREP_io_800_readb, sysctrl);
 712     register_ioport_write(0x0092, 0x01, 1, &PREP_io_800_writeb, sysctrl);
 713     register_ioport_read(0x0800, 0x52, 1, &PREP_io_800_readb, sysctrl);
 714     register_ioport_write(0x0800, 0x52, 1, &PREP_io_800_writeb, sysctrl);
 715     /* PCI intack location */
 716     PPC_io_memory = cpu_register_io_memory(PPC_intack_read,
 717                                            PPC_intack_write, NULL,
 718                                            DEVICE_LITTLE_ENDIAN);
 719     cpu_register_physical_memory(0xBFFFFFF0, 0x4, PPC_io_memory);
 720     /* PowerPC control and status register group */
 721 #if 0
 722     PPC_io_memory = cpu_register_io_memory(PPC_XCSR_read, PPC_XCSR_write,
 723                                            NULL, DEVICE_LITTLE_ENDIAN);
 724     cpu_register_physical_memory(0xFEFF0000, 0x1000, PPC_io_memory);
 725 #endif
 726
 727     if (usb_enabled) {
 728         usb_ohci_init_pci(pci_bus, -1);
 729     }
 730
 731     m48t59 = m48t59_init(i8259[8], 0, 0x0074, NVRAM_SIZE, 59);
 732     if (m48t59 == NULL)
 733         return;
 734     sysctrl->nvram = m48t59;
 735
 736     /* Initialise NVRAM */
 737     nvram.opaque = m48t59;
 738     nvram.read_fn = &m48t59_read;
 739     nvram.write_fn = &m48t59_write;
 740     PPC_NVRAM_set_params(&nvram, NVRAM_SIZE, "PREP", ram_size, ppc_boot_device,
 741                          kernel_base, kernel_size,
 742                          kernel_cmdline,
 743                          initrd_base, initrd_size,
 744                          /* XXX: need an option to load a NVRAM image */
 745                          0,
 746                          graphic_width, graphic_height, graphic_depth);
 747
 748     /* Special port to get debug messages from Open-Firmware */
 749     register_ioport_write(0x0F00, 4, 1, &PPC_debug_write, NULL);
 750 }
 751
 752 static QEMUMachine prep_machine = {
 753     .name = "prep",
 754     .desc = "PowerPC PREP platform",
 755     .init = ppc_prep_init,
 756     .max_cpus = MAX_CPUS,
 757 };
 758
 759 static void prep_machine_init(void)
 760 {
 761     qemu_register_machine(&prep_machine);
 762 }
 763
 764 machine_init(prep_machine_init);