hw/grlib_apbuart.c

   1 /*
   2  * QEMU GRLIB APB UART Emulator
   3  *
   4  * Copyright (c) 2010-2011 AdaCore
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #include "sysbus.h"
  26 #include "qemu-char.h"
  27
  28 #include "trace.h"
  29
  30 #define UART_REG_SIZE 20     /* Size of memory mapped registers */
  31
  32 /* UART status register fields */
  33 #define UART_DATA_READY           (1 <<  0)
  34 #define UART_TRANSMIT_SHIFT_EMPTY (1 <<  1)
  35 #define UART_TRANSMIT_FIFO_EMPTY  (1 <<  2)
  36 #define UART_BREAK_RECEIVED       (1 <<  3)
  37 #define UART_OVERRUN              (1 <<  4)
  38 #define UART_PARITY_ERROR         (1 <<  5)
  39 #define UART_FRAMING_ERROR        (1 <<  6)
  40 #define UART_TRANSMIT_FIFO_HALF   (1 <<  7)
  41 #define UART_RECEIVE_FIFO_HALF    (1 <<  8)
  42 #define UART_TRANSMIT_FIFO_FULL   (1 <<  9)
  43 #define UART_RECEIVE_FIFO_FULL    (1 << 10)
  44
  45 /* UART control register fields */
  46 #define UART_RECEIVE_ENABLE          (1 <<  0)
  47 #define UART_TRANSMIT_ENABLE         (1 <<  1)
  48 #define UART_RECEIVE_INTERRUPT       (1 <<  2)
  49 #define UART_TRANSMIT_INTERRUPT      (1 <<  3)
  50 #define UART_PARITY_SELECT           (1 <<  4)
  51 #define UART_PARITY_ENABLE           (1 <<  5)
  52 #define UART_FLOW_CONTROL            (1 <<  6)
  53 #define UART_LOOPBACK                (1 <<  7)
  54 #define UART_EXTERNAL_CLOCK          (1 <<  8)
  55 #define UART_RECEIVE_FIFO_INTERRUPT  (1 <<  9)
  56 #define UART_TRANSMIT_FIFO_INTERRUPT (1 << 10)
  57 #define UART_FIFO_DEBUG_MODE         (1 << 11)
  58 #define UART_OUTPUT_ENABLE           (1 << 12)
  59 #define UART_FIFO_AVAILABLE          (1 << 31)
  60
  61 /* Memory mapped register offsets */
  62 #define DATA_OFFSET       0x00
  63 #define STATUS_OFFSET     0x04
  64 #define CONTROL_OFFSET    0x08
  65 #define SCALER_OFFSET     0x0C  /* not supported */
  66 #define FIFO_DEBUG_OFFSET 0x10  /* not supported */
  67
  68 typedef struct UART {
  69     SysBusDevice busdev;
  70
  71     qemu_irq irq;
  72
  73     CharDriverState *chr;
  74
  75     /* registers */
  76     uint32_t receive;
  77     uint32_t status;
  78     uint32_t control;
  79 } UART;
  80
  81 static void grlib_apbuart_update_handlers(UART *uart);
  82
  83 static int grlib_apbuart_can_receive(UART *uart)
  84 {
  85     return !!(uart->status & UART_DATA_READY);
  86 }
  87
  88 static void grlib_apbuart_receive(UART *uart, const uint8_t *buf, int size)
  89 {
  90     uart->receive  = *buf;
  91     uart->status  |= UART_DATA_READY;
  92
  93     grlib_apbuart_update_handlers(uart);
  94
  95     if (uart->control & UART_RECEIVE_INTERRUPT) {
  96         qemu_irq_pulse(uart->irq);
  97     }
  98 }
  99
 100 static void grlib_apbuart_event(void *opaque, int event)
 101 {
 102     trace_grlib_apbuart_event(event);
 103 }
 104
 105 static void grlib_apbuart_receive_handler(void *opaque)
 106 {
 107     UART *uart = opaque;
 108     uint8_t buf[32];
 109     int size;
 110
 111     size = grlib_apbuart_can_receive(uart);
 112     size = MIN(size, sizeof(buf));
 113     size = qemu_chr_fe_read(uart->chr, buf, size);
 114
 115     grlib_apbuart_receive(uart, buf, size);
 116 }
 117
 118 static void grlib_apbuart_update_handlers(UART *uart)
 119 {
 120     if (grlib_apbuart_can_receive(uart) > 0) {
 121         qemu_chr_fe_set_handlers(uart->chr,
 122                                  grlib_apbuart_receive_handler,
 123                                  NULL,
 124                                  grlib_apbuart_event,
 125                                  uart);
 126     } else {
 127         qemu_chr_fe_set_handlers(uart->chr,
 128                                  NULL,
 129                                  NULL,
 130                                  grlib_apbuart_event,
 131                                  uart);
 132     }
 133 }
 134
 135 static void
 136 grlib_apbuart_writel(void *opaque, target_phys_addr_t addr, uint32_t value)
 137 {
 138     UART          *uart = opaque;
 139     unsigned char  c    = 0;
 140
 141     addr &= 0xff;
 142
 143     /* Unit registers */
 144     switch (addr) {
 145     case DATA_OFFSET:
 146         c = value & 0xFF;
 147         qemu_chr_fe_write(uart->chr, &c, 1);
 148         return;
 149
 150     case STATUS_OFFSET:
 151         /* Read Only */
 152         return;
 153
 154     case CONTROL_OFFSET:
 155         /* Not supported */
 156         return;
 157
 158     case SCALER_OFFSET:
 159         /* Not supported */
 160         return;
 161
 162     default:
 163         break;
 164     }
 165
 166     trace_grlib_apbuart_writel_unknown(addr, value);
 167 }
 168
 169 static CPUReadMemoryFunc * const grlib_apbuart_read[] = {
 170     NULL, NULL, NULL,
 171 };
 172
 173 static CPUWriteMemoryFunc * const grlib_apbuart_write[] = {
 174     NULL, NULL, grlib_apbuart_writel,
 175 };
 176
 177 static int grlib_apbuart_init(SysBusDevice *dev)
 178 {
 179     UART *uart      = FROM_SYSBUS(typeof(*uart), dev);
 180     int   uart_regs = 0;
 181
 182     qemu_chr_fe_open(uart->chr);
 183     grlib_apbuart_update_handlers(uart);
 184
 185     sysbus_init_irq(dev, &uart->irq);
 186
 187     uart_regs = cpu_register_io_memory(grlib_apbuart_read,
 188                                        grlib_apbuart_write,
 189                                        uart, DEVICE_NATIVE_ENDIAN);
 190     if (uart_regs < 0) {
 191         return -1;
 192     }
 193
 194     sysbus_init_mmio(dev, UART_REG_SIZE, uart_regs);
 195
 196     return 0;
 197 }
 198
 199 static SysBusDeviceInfo grlib_gptimer_info = {
 200     .init       = grlib_apbuart_init,
 201     .qdev.name  = "grlib,apbuart",
 202     .qdev.size  = sizeof(UART),
 203     .qdev.props = (Property[]) {
 204         DEFINE_PROP_CHR("chrdev", UART, chr),
 205         DEFINE_PROP_END_OF_LIST()
 206     }
 207 };
 208
 209 static void grlib_gptimer_register(void)
 210 {
 211     sysbus_register_withprop(&grlib_gptimer_info);
 212 }
 213
 214 device_init(grlib_gptimer_register)