hw/integratorcp.c

   1 /*
   2  * ARM Integrator CP System emulation.
   3  *
   4  * Copyright (c) 2005-2007 CodeSourcery.
   5  * Written by Paul Brook
   6  *
   7  * This code is licensed under the GPL
   8  */
   9
  10 #include "sysbus.h"
  11 #include "primecell.h"
  12 #include "devices.h"
  13 #include "boards.h"
  14 #include "arm-misc.h"
  15 #include "net.h"
  16
  17 typedef struct {
  18     SysBusDevice busdev;
  19     uint32_t memsz;
  20     uint32_t flash_offset;
  21     uint32_t cm_osc;
  22     uint32_t cm_ctrl;
  23     uint32_t cm_lock;
  24     uint32_t cm_auxosc;
  25     uint32_t cm_sdram;
  26     uint32_t cm_init;
  27     uint32_t cm_flags;
  28     uint32_t cm_nvflags;
  29     uint32_t int_level;
  30     uint32_t irq_enabled;
  31     uint32_t fiq_enabled;
  32 } integratorcm_state;
  33
  34 static uint8_t integrator_spd[128] = {
  35    128, 8, 4, 11, 9, 1, 64, 0,  2, 0xa0, 0xa0, 0, 0, 8, 0, 1,
  36    0xe, 4, 0x1c, 1, 2, 0x20, 0xc0, 0, 0, 0, 0, 0x30, 0x28, 0x30, 0x28, 0x40
  37 };
  38
  39 static uint32_t integratorcm_read(void *opaque, target_phys_addr_t offset)
  40 {
  41     integratorcm_state *s = (integratorcm_state *)opaque;
  42     if (offset >= 0x100 && offset < 0x200) {
  43         /* CM_SPD */
  44         if (offset >= 0x180)
  45             return 0;
  46         return integrator_spd[offset >> 2];
  47     }
  48     switch (offset >> 2) {
  49     case 0: /* CM_ID */
  50         return 0x411a3001;
  51     case 1: /* CM_PROC */
  52         return 0;
  53     case 2: /* CM_OSC */
  54         return s->cm_osc;
  55     case 3: /* CM_CTRL */
  56         return s->cm_ctrl;
  57     case 4: /* CM_STAT */
  58         return 0x00100000;
  59     case 5: /* CM_LOCK */
  60         if (s->cm_lock == 0xa05f) {
  61             return 0x1a05f;
  62         } else {
  63             return s->cm_lock;
  64         }
  65     case 6: /* CM_LMBUSCNT */
  66         /* ??? High frequency timer.  */
  67         hw_error("integratorcm_read: CM_LMBUSCNT");
  68     case 7: /* CM_AUXOSC */
  69         return s->cm_auxosc;
  70     case 8: /* CM_SDRAM */
  71         return s->cm_sdram;
  72     case 9: /* CM_INIT */
  73         return s->cm_init;
  74     case 10: /* CM_REFCT */
  75         /* ??? High frequency timer.  */
  76         hw_error("integratorcm_read: CM_REFCT");
  77     case 12: /* CM_FLAGS */
  78         return s->cm_flags;
  79     case 14: /* CM_NVFLAGS */
  80         return s->cm_nvflags;
  81     case 16: /* CM_IRQ_STAT */
  82         return s->int_level & s->irq_enabled;
  83     case 17: /* CM_IRQ_RSTAT */
  84         return s->int_level;
  85     case 18: /* CM_IRQ_ENSET */
  86         return s->irq_enabled;
  87     case 20: /* CM_SOFT_INTSET */
  88         return s->int_level & 1;
  89     case 24: /* CM_FIQ_STAT */
  90         return s->int_level & s->fiq_enabled;
  91     case 25: /* CM_FIQ_RSTAT */
  92         return s->int_level;
  93     case 26: /* CM_FIQ_ENSET */
  94         return s->fiq_enabled;
  95     case 32: /* CM_VOLTAGE_CTL0 */
  96     case 33: /* CM_VOLTAGE_CTL1 */
  97     case 34: /* CM_VOLTAGE_CTL2 */
  98     case 35: /* CM_VOLTAGE_CTL3 */
  99         /* ??? Voltage control unimplemented.  */
 100         return 0;
 101     default:
 102         hw_error("integratorcm_read: Unimplemented offset 0x%x\n",
 103                  (int)offset);
 104         return 0;
 105     }
 106 }
 107
 108 static void integratorcm_do_remap(integratorcm_state *s, int flash)
 109 {
 110     if (flash) {
 111         cpu_register_physical_memory(0, 0x100000, IO_MEM_RAM);
 112     } else {
 113         cpu_register_physical_memory(0, 0x100000, s->flash_offset | IO_MEM_RAM);
 114     }
 115     //??? tlb_flush (cpu_single_env, 1);
 116 }
 117
 118 static void integratorcm_set_ctrl(integratorcm_state *s, uint32_t value)
 119 {
 120     if (value & 8) {
 121         hw_error("Board reset\n");
 122     }
 123     if ((s->cm_init ^ value) & 4) {
 124         integratorcm_do_remap(s, (value & 4) == 0);
 125     }
 126     if ((s->cm_init ^ value) & 1) {
 127         printf("Green LED %s\n", (value & 1) ? "on" : "off");
 128     }
 129     s->cm_init = (s->cm_init & ~ 5) | (value ^ 5);
 130 }
 131
 132 static void integratorcm_update(integratorcm_state *s)
 133 {
 134     /* ??? The CPU irq/fiq is raised when either the core module or base PIC
 135        are active.  */
 136     if (s->int_level & (s->irq_enabled | s->fiq_enabled))
 137         hw_error("Core module interrupt\n");
 138 }
 139
 140 static void integratorcm_write(void *opaque, target_phys_addr_t offset,
 141                                uint32_t value)
 142 {
 143     integratorcm_state *s = (integratorcm_state *)opaque;
 144     switch (offset >> 2) {
 145     case 2: /* CM_OSC */
 146         if (s->cm_lock == 0xa05f)
 147             s->cm_osc = value;
 148         break;
 149     case 3: /* CM_CTRL */
 150         integratorcm_set_ctrl(s, value);
 151         break;
 152     case 5: /* CM_LOCK */
 153         s->cm_lock = value & 0xffff;
 154         break;
 155     case 7: /* CM_AUXOSC */
 156         if (s->cm_lock == 0xa05f)
 157             s->cm_auxosc = value;
 158         break;
 159     case 8: /* CM_SDRAM */
 160         s->cm_sdram = value;
 161         break;
 162     case 9: /* CM_INIT */
 163         /* ??? This can change the memory bus frequency.  */
 164         s->cm_init = value;
 165         break;
 166     case 12: /* CM_FLAGSS */
 167         s->cm_flags |= value;
 168         break;
 169     case 13: /* CM_FLAGSC */
 170         s->cm_flags &= ~value;
 171         break;
 172     case 14: /* CM_NVFLAGSS */
 173         s->cm_nvflags |= value;
 174         break;
 175     case 15: /* CM_NVFLAGSS */
 176         s->cm_nvflags &= ~value;
 177         break;
 178     case 18: /* CM_IRQ_ENSET */
 179         s->irq_enabled |= value;
 180         integratorcm_update(s);
 181         break;
 182     case 19: /* CM_IRQ_ENCLR */
 183         s->irq_enabled &= ~value;
 184         integratorcm_update(s);
 185         break;
 186     case 20: /* CM_SOFT_INTSET */
 187         s->int_level |= (value & 1);
 188         integratorcm_update(s);
 189         break;
 190     case 21: /* CM_SOFT_INTCLR */
 191         s->int_level &= ~(value & 1);
 192         integratorcm_update(s);
 193         break;
 194     case 26: /* CM_FIQ_ENSET */
 195         s->fiq_enabled |= value;
 196         integratorcm_update(s);
 197         break;
 198     case 27: /* CM_FIQ_ENCLR */
 199         s->fiq_enabled &= ~value;
 200         integratorcm_update(s);
 201         break;
 202     case 32: /* CM_VOLTAGE_CTL0 */
 203     case 33: /* CM_VOLTAGE_CTL1 */
 204     case 34: /* CM_VOLTAGE_CTL2 */
 205     case 35: /* CM_VOLTAGE_CTL3 */
 206         /* ??? Voltage control unimplemented.  */
 207         break;
 208     default:
 209         hw_error("integratorcm_write: Unimplemented offset 0x%x\n",
 210                  (int)offset);
 211         break;
 212     }
 213 }
 214
 215 /* Integrator/CM control registers.  */
 216
 217 static CPUReadMemoryFunc * const integratorcm_readfn[] = {
 218    integratorcm_read,
 219    integratorcm_read,
 220    integratorcm_read
 221 };
 222
 223 static CPUWriteMemoryFunc * const integratorcm_writefn[] = {
 224    integratorcm_write,
 225    integratorcm_write,
 226    integratorcm_write
 227 };
 228
 229 static int integratorcm_init(SysBusDevice *dev)
 230 {
 231     int iomemtype;
 232     integratorcm_state *s = FROM_SYSBUS(integratorcm_state, dev);
 233
 234     s->cm_osc = 0x01000048;
 235     /* ??? What should the high bits of this value be?  */
 236     s->cm_auxosc = 0x0007feff;
 237     s->cm_sdram = 0x00011122;
 238     if (s->memsz >= 256) {
 239         integrator_spd[31] = 64;
 240         s->cm_sdram |= 0x10;
 241     } else if (s->memsz >= 128) {
 242         integrator_spd[31] = 32;
 243         s->cm_sdram |= 0x0c;
 244     } else if (s->memsz >= 64) {
 245         integrator_spd[31] = 16;
 246         s->cm_sdram |= 0x08;
 247     } else if (s->memsz >= 32) {
 248         integrator_spd[31] = 4;
 249         s->cm_sdram |= 0x04;
 250     } else {
 251         integrator_spd[31] = 2;
 252     }
 253     memcpy(integrator_spd + 73, "QEMU-MEMORY", 11);
 254     s->cm_init = 0x00000112;
 255     s->flash_offset = qemu_ram_alloc(NULL, "integrator.flash", 0x100000);
 256
 257     iomemtype = cpu_register_io_memory(integratorcm_readfn,
 258                                        integratorcm_writefn, s,
 259                                        DEVICE_NATIVE_ENDIAN);
 260     sysbus_init_mmio(dev, 0x00800000, iomemtype);
 261     integratorcm_do_remap(s, 1);
 262     /* ??? Save/restore.  */
 263     return 0;
 264 }
 265
 266 /* Integrator/CP hardware emulation.  */
 267 /* Primary interrupt controller.  */
 268
 269 typedef struct icp_pic_state
 270 {
 271   SysBusDevice busdev;
 272   uint32_t level;
 273   uint32_t irq_enabled;
 274   uint32_t fiq_enabled;
 275   qemu_irq parent_irq;
 276   qemu_irq parent_fiq;
 277 } icp_pic_state;
 278
 279 static void icp_pic_update(icp_pic_state *s)
 280 {
 281     uint32_t flags;
 282
 283     flags = (s->level & s->irq_enabled);
 284     qemu_set_irq(s->parent_irq, flags != 0);
 285     flags = (s->level & s->fiq_enabled);
 286     qemu_set_irq(s->parent_fiq, flags != 0);
 287 }
 288
 289 static void icp_pic_set_irq(void *opaque, int irq, int level)
 290 {
 291     icp_pic_state *s = (icp_pic_state *)opaque;
 292     if (level)
 293         s->level |= 1 << irq;
 294     else
 295         s->level &= ~(1 << irq);
 296     icp_pic_update(s);
 297 }
 298
 299 static uint32_t icp_pic_read(void *opaque, target_phys_addr_t offset)
 300 {
 301     icp_pic_state *s = (icp_pic_state *)opaque;
 302
 303     switch (offset >> 2) {
 304     case 0: /* IRQ_STATUS */
 305         return s->level & s->irq_enabled;
 306     case 1: /* IRQ_RAWSTAT */
 307         return s->level;
 308     case 2: /* IRQ_ENABLESET */
 309         return s->irq_enabled;
 310     case 4: /* INT_SOFTSET */
 311         return s->level & 1;
 312     case 8: /* FRQ_STATUS */
 313         return s->level & s->fiq_enabled;
 314     case 9: /* FRQ_RAWSTAT */
 315         return s->level;
 316     case 10: /* FRQ_ENABLESET */
 317         return s->fiq_enabled;
 318     case 3: /* IRQ_ENABLECLR */
 319     case 5: /* INT_SOFTCLR */
 320     case 11: /* FRQ_ENABLECLR */
 321     default:
 322         printf ("icp_pic_read: Bad register offset 0x%x\n", (int)offset);
 323         return 0;
 324     }
 325 }
 326
 327 static void icp_pic_write(void *opaque, target_phys_addr_t offset,
 328                           uint32_t value)
 329 {
 330     icp_pic_state *s = (icp_pic_state *)opaque;
 331
 332     switch (offset >> 2) {
 333     case 2: /* IRQ_ENABLESET */
 334         s->irq_enabled |= value;
 335         break;
 336     case 3: /* IRQ_ENABLECLR */
 337         s->irq_enabled &= ~value;
 338         break;
 339     case 4: /* INT_SOFTSET */
 340         if (value & 1)
 341             icp_pic_set_irq(s, 0, 1);
 342         break;
 343     case 5: /* INT_SOFTCLR */
 344         if (value & 1)
 345             icp_pic_set_irq(s, 0, 0);
 346         break;
 347     case 10: /* FRQ_ENABLESET */
 348         s->fiq_enabled |= value;
 349         break;
 350     case 11: /* FRQ_ENABLECLR */
 351         s->fiq_enabled &= ~value;
 352         break;
 353     case 0: /* IRQ_STATUS */
 354     case 1: /* IRQ_RAWSTAT */
 355     case 8: /* FRQ_STATUS */
 356     case 9: /* FRQ_RAWSTAT */
 357     default:
 358         printf ("icp_pic_write: Bad register offset 0x%x\n", (int)offset);
 359         return;
 360     }
 361     icp_pic_update(s);
 362 }
 363
 364 static CPUReadMemoryFunc * const icp_pic_readfn[] = {
 365    icp_pic_read,
 366    icp_pic_read,
 367    icp_pic_read
 368 };
 369
 370 static CPUWriteMemoryFunc * const icp_pic_writefn[] = {
 371    icp_pic_write,
 372    icp_pic_write,
 373    icp_pic_write
 374 };
 375
 376 static int icp_pic_init(SysBusDevice *dev)
 377 {
 378     icp_pic_state *s = FROM_SYSBUS(icp_pic_state, dev);
 379     int iomemtype;
 380
 381     qdev_init_gpio_in(&dev->qdev, icp_pic_set_irq, 32);
 382     sysbus_init_irq(dev, &s->parent_irq);
 383     sysbus_init_irq(dev, &s->parent_fiq);
 384     iomemtype = cpu_register_io_memory(icp_pic_readfn,
 385                                        icp_pic_writefn, s,
 386                                        DEVICE_NATIVE_ENDIAN);
 387     sysbus_init_mmio(dev, 0x00800000, iomemtype);
 388     return 0;
 389 }
 390
 391 /* CP control registers.  */
 392 static uint32_t icp_control_read(void *opaque, target_phys_addr_t offset)
 393 {
 394     switch (offset >> 2) {
 395     case 0: /* CP_IDFIELD */
 396         return 0x41034003;
 397     case 1: /* CP_FLASHPROG */
 398         return 0;
 399     case 2: /* CP_INTREG */
 400         return 0;
 401     case 3: /* CP_DECODE */
 402         return 0x11;
 403     default:
 404         hw_error("icp_control_read: Bad offset %x\n", (int)offset);
 405         return 0;
 406     }
 407 }
 408
 409 static void icp_control_write(void *opaque, target_phys_addr_t offset,
 410                           uint32_t value)
 411 {
 412     switch (offset >> 2) {
 413     case 1: /* CP_FLASHPROG */
 414     case 2: /* CP_INTREG */
 415     case 3: /* CP_DECODE */
 416         /* Nothing interesting implemented yet.  */
 417         break;
 418     default:
 419         hw_error("icp_control_write: Bad offset %x\n", (int)offset);
 420     }
 421 }
 422 static CPUReadMemoryFunc * const icp_control_readfn[] = {
 423    icp_control_read,
 424    icp_control_read,
 425    icp_control_read
 426 };
 427
 428 static CPUWriteMemoryFunc * const icp_control_writefn[] = {
 429    icp_control_write,
 430    icp_control_write,
 431    icp_control_write
 432 };
 433
 434 static void icp_control_init(uint32_t base)
 435 {
 436     int iomemtype;
 437
 438     iomemtype = cpu_register_io_memory(icp_control_readfn,
 439                                        icp_control_writefn, NULL,
 440                                        DEVICE_NATIVE_ENDIAN);
 441     cpu_register_physical_memory(base, 0x00800000, iomemtype);
 442     /* ??? Save/restore.  */
 443 }
 444
 445
 446 /* Board init.  */
 447
 448 static struct arm_boot_info integrator_binfo = {
 449     .loader_start = 0x0,
 450     .board_id = 0x113,
 451 };
 452
 453 static void integratorcp_init(ram_addr_t ram_size,
 454                      const char *boot_device,
 455                      const char *kernel_filename, const char *kernel_cmdline,
 456                      const char *initrd_filename, const char *cpu_model)
 457 {
 458     CPUState *env;
 459     ram_addr_t ram_offset;
 460     qemu_irq pic[32];
 461     qemu_irq *cpu_pic;
 462     DeviceState *dev;
 463     int i;
 464
 465     if (!cpu_model)
 466         cpu_model = "arm926";
 467     env = cpu_init(cpu_model);
 468     if (!env) {
 469         fprintf(stderr, "Unable to find CPU definition\n");
 470         exit(1);
 471     }
 472     ram_offset = qemu_ram_alloc(NULL, "integrator.ram", ram_size);
 473     /* ??? On a real system the first 1Mb is mapped as SSRAM or boot flash.  */
 474     /* ??? RAM should repeat to fill physical memory space.  */
 475     /* SDRAM at address zero*/
 476     cpu_register_physical_memory(0, ram_size, ram_offset | IO_MEM_RAM);
 477     /* And again at address 0x80000000 */
 478     cpu_register_physical_memory(0x80000000, ram_size, ram_offset | IO_MEM_RAM);
 479
 480     dev = qdev_create(NULL, "integrator_core");
 481     qdev_prop_set_uint32(dev, "memsz", ram_size >> 20);
 482     qdev_init_nofail(dev);
 483     sysbus_mmio_map((SysBusDevice *)dev, 0, 0x10000000);
 484
 485     cpu_pic = arm_pic_init_cpu(env);
 486     dev = sysbus_create_varargs("integrator_pic", 0x14000000,
 487                                 cpu_pic[ARM_PIC_CPU_IRQ],
 488                                 cpu_pic[ARM_PIC_CPU_FIQ], NULL);
 489     for (i = 0; i < 32; i++) {
 490         pic[i] = qdev_get_gpio_in(dev, i);
 491     }
 492     sysbus_create_simple("integrator_pic", 0xca000000, pic[26]);
 493     sysbus_create_varargs("integrator_pit", 0x13000000,
 494                           pic[5], pic[6], pic[7], NULL);
 495     sysbus_create_simple("pl031", 0x15000000, pic[8]);
 496     sysbus_create_simple("pl011", 0x16000000, pic[1]);
 497     sysbus_create_simple("pl011", 0x17000000, pic[2]);
 498     icp_control_init(0xcb000000);
 499     sysbus_create_simple("pl050_keyboard", 0x18000000, pic[3]);
 500     sysbus_create_simple("pl050_mouse", 0x19000000, pic[4]);
 501     sysbus_create_varargs("pl181", 0x1c000000, pic[23], pic[24], NULL);
 502     if (nd_table[0].vlan)
 503         smc91c111_init(&nd_table[0], 0xc8000000, pic[27]);
 504
 505     sysbus_create_simple("pl110", 0xc0000000, pic[22]);
 506
 507     integrator_binfo.ram_size = ram_size;
 508     integrator_binfo.kernel_filename = kernel_filename;
 509     integrator_binfo.kernel_cmdline = kernel_cmdline;
 510     integrator_binfo.initrd_filename = initrd_filename;
 511     arm_load_kernel(env, &integrator_binfo);
 512 }
 513
 514 static QEMUMachine integratorcp_machine = {
 515     .name = "integratorcp",
 516     .desc = "ARM Integrator/CP (ARM926EJ-S)",
 517     .init = integratorcp_init,
 518     .is_default = 1,
 519 };
 520
 521 static void integratorcp_machine_init(void)
 522 {
 523     qemu_register_machine(&integratorcp_machine);
 524 }
 525
 526 machine_init(integratorcp_machine_init);
 527
 528 static SysBusDeviceInfo core_info = {
 529     .init = integratorcm_init,
 530     .qdev.name  = "integrator_core",
 531     .qdev.size  = sizeof(integratorcm_state),
 532     .qdev.props = (Property[]) {
 533         DEFINE_PROP_UINT32("memsz", integratorcm_state, memsz, 0),
 534         DEFINE_PROP_END_OF_LIST(),
 535     }
 536 };
 537
 538 static void integratorcp_register_devices(void)
 539 {
 540     sysbus_register_dev("integrator_pic", sizeof(icp_pic_state), icp_pic_init);
 541     sysbus_register_withprop(&core_info);
 542 }
 543
 544 device_init(integratorcp_register_devices)