hw/lm32_uart.c

   1 /*
   2  *  QEMU model of the LatticeMico32 UART block.
   3  *
   4  *  Copyright (c) 2010 Michael Walle <michael@walle.cc>
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  *
  19  *
  20  * Specification available at:
  21  *   http://www.latticesemi.com/documents/mico32uart.pdf
  22  */
  23
  24
  25 #include "hw.h"
  26 #include "sysbus.h"
  27 #include "trace.h"
  28 #include "qemu-char.h"
  29 #include "qemu-error.h"
  30
  31 enum {
  32     R_RXTX = 0,
  33     R_IER,
  34     R_IIR,
  35     R_LCR,
  36     R_MCR,
  37     R_LSR,
  38     R_MSR,
  39     R_DIV,
  40     R_MAX
  41 };
  42
  43 enum {
  44     IER_RBRI = (1<<0),
  45     IER_THRI = (1<<1),
  46     IER_RLSI = (1<<2),
  47     IER_MSI  = (1<<3),
  48 };
  49
  50 enum {
  51     IIR_STAT = (1<<0),
  52     IIR_ID0  = (1<<1),
  53     IIR_ID1  = (1<<2),
  54 };
  55
  56 enum {
  57     LCR_WLS0 = (1<<0),
  58     LCR_WLS1 = (1<<1),
  59     LCR_STB  = (1<<2),
  60     LCR_PEN  = (1<<3),
  61     LCR_EPS  = (1<<4),
  62     LCR_SP   = (1<<5),
  63     LCR_SB   = (1<<6),
  64 };
  65
  66 enum {
  67     MCR_DTR  = (1<<0),
  68     MCR_RTS  = (1<<1),
  69 };
  70
  71 enum {
  72     LSR_DR   = (1<<0),
  73     LSR_OE   = (1<<1),
  74     LSR_PE   = (1<<2),
  75     LSR_FE   = (1<<3),
  76     LSR_BI   = (1<<4),
  77     LSR_THRE = (1<<5),
  78     LSR_TEMT = (1<<6),
  79 };
  80
  81 enum {
  82     MSR_DCTS = (1<<0),
  83     MSR_DDSR = (1<<1),
  84     MSR_TERI = (1<<2),
  85     MSR_DDCD = (1<<3),
  86     MSR_CTS  = (1<<4),
  87     MSR_DSR  = (1<<5),
  88     MSR_RI   = (1<<6),
  89     MSR_DCD  = (1<<7),
  90 };
  91
  92 struct LM32UartState {
  93     SysBusDevice busdev;
  94     CharDriverState *chr;
  95     qemu_irq irq;
  96
  97     uint32_t regs[R_MAX];
  98 };
  99 typedef struct LM32UartState LM32UartState;
 100
 101 static void uart_update_handlers(LM32UartState *s);
 102
 103 static void uart_update_irq(LM32UartState *s)
 104 {
 105     unsigned int irq;
 106
 107     if ((s->regs[R_LSR] & (LSR_OE | LSR_PE | LSR_FE | LSR_BI))
 108             && (s->regs[R_IER] & IER_RLSI)) {
 109         irq = 1;
 110         s->regs[R_IIR] = IIR_ID1 | IIR_ID0;
 111     } else if ((s->regs[R_LSR] & LSR_DR) && (s->regs[R_IER] & IER_RBRI)) {
 112         irq = 1;
 113         s->regs[R_IIR] = IIR_ID1;
 114     } else if ((s->regs[R_LSR] & LSR_THRE) && (s->regs[R_IER] & IER_THRI)) {
 115         irq = 1;
 116         s->regs[R_IIR] = IIR_ID0;
 117     } else if ((s->regs[R_MSR] & 0x0f) && (s->regs[R_IER] & IER_MSI)) {
 118         irq = 1;
 119         s->regs[R_IIR] = 0;
 120     } else {
 121         irq = 0;
 122         s->regs[R_IIR] = IIR_STAT;
 123     }
 124
 125     trace_lm32_uart_irq_state(irq);
 126     qemu_set_irq(s->irq, irq);
 127 }
 128
 129 static uint32_t uart_read(void *opaque, target_phys_addr_t addr)
 130 {
 131     LM32UartState *s = opaque;
 132     uint32_t r = 0;
 133
 134     addr >>= 2;
 135     switch (addr) {
 136     case R_RXTX:
 137         r = s->regs[R_RXTX];
 138         s->regs[R_LSR] &= ~LSR_DR;
 139         uart_update_irq(s);
 140         uart_update_handlers(s);
 141         break;
 142     case R_IIR:
 143     case R_LSR:
 144     case R_MSR:
 145         r = s->regs[addr];
 146         break;
 147     case R_IER:
 148     case R_LCR:
 149     case R_MCR:
 150     case R_DIV:
 151         error_report("lm32_uart: read access to write only register 0x"
 152                 TARGET_FMT_plx, addr << 2);
 153         break;
 154     default:
 155         error_report("lm32_uart: read access to unknown register 0x"
 156                 TARGET_FMT_plx, addr << 2);
 157         break;
 158     }
 159
 160     trace_lm32_uart_memory_read(addr << 2, r);
 161     return r;
 162 }
 163
 164 static void uart_write(void *opaque, target_phys_addr_t addr, uint32_t value)
 165 {
 166     LM32UartState *s = opaque;
 167     unsigned char ch = value;
 168
 169     trace_lm32_uart_memory_write(addr, value);
 170
 171     addr >>= 2;
 172     switch (addr) {
 173     case R_RXTX:
 174         if (s->chr) {
 175             qemu_chr_fe_write(s->chr, &ch, 1);
 176         }
 177         break;
 178     case R_IER:
 179     case R_LCR:
 180     case R_MCR:
 181     case R_DIV:
 182         s->regs[addr] = value;
 183         break;
 184     case R_IIR:
 185     case R_LSR:
 186     case R_MSR:
 187         error_report("lm32_uart: write access to read only register 0x"
 188                 TARGET_FMT_plx, addr << 2);
 189         break;
 190     default:
 191         error_report("lm32_uart: write access to unknown register 0x"
 192                 TARGET_FMT_plx, addr << 2);
 193         break;
 194     }
 195     uart_update_irq(s);
 196 }
 197
 198 static CPUReadMemoryFunc * const uart_read_fn[] = {
 199     NULL,
 200     NULL,
 201     &uart_read,
 202 };
 203
 204 static CPUWriteMemoryFunc * const uart_write_fn[] = {
 205     NULL,
 206     NULL,
 207     &uart_write,
 208 };
 209
 210 static void uart_rx(LM32UartState *s, const uint8_t *buf, int size)
 211 {
 212     if (s->regs[R_LSR] & LSR_DR) {
 213         s->regs[R_LSR] |= LSR_OE;
 214     }
 215
 216     s->regs[R_LSR] |= LSR_DR;
 217     s->regs[R_RXTX] = *buf;
 218
 219     uart_update_irq(s);
 220     uart_update_handlers(s);
 221 }
 222
 223 static int uart_can_rx(LM32UartState *s)
 224 {
 225     return !(s->regs[R_LSR] & LSR_DR);
 226 }
 227
 228 static void uart_event(void *opaque, int event)
 229 {
 230 }
 231
 232 static void uart_rx_handler(void *opaque)
 233 {
 234     LM32UartState *s = opaque;
 235     uint8_t buf[32];
 236     int size;
 237
 238     size = uart_can_rx(s);
 239     size = MIN(size, sizeof(buf));
 240     size = qemu_chr_fe_read(s->chr, buf, size);
 241
 242     uart_rx(s, buf, size);
 243 }
 244
 245 static void uart_update_handlers(LM32UartState *s)
 246 {
 247     if (uart_can_rx(s) > 0) {
 248         qemu_chr_fe_set_handlers(s->chr, uart_rx_handler, NULL, uart_event, s);
 249     } else {
 250         qemu_chr_fe_set_handlers(s->chr, NULL, NULL, uart_event, s);
 251     }
 252 }
 253
 254 static void uart_reset(DeviceState *d)
 255 {
 256     LM32UartState *s = container_of(d, LM32UartState, busdev.qdev);
 257     int i;
 258
 259     for (i = 0; i < R_MAX; i++) {
 260         s->regs[i] = 0;
 261     }
 262
 263     /* defaults */
 264     s->regs[R_LSR] = LSR_THRE | LSR_TEMT;
 265     uart_update_handlers(s);
 266 }
 267
 268 static int lm32_uart_init(SysBusDevice *dev)
 269 {
 270     LM32UartState *s = FROM_SYSBUS(typeof(*s), dev);
 271     int uart_regs;
 272
 273     sysbus_init_irq(dev, &s->irq);
 274
 275     uart_regs = cpu_register_io_memory(uart_read_fn, uart_write_fn, s,
 276             DEVICE_NATIVE_ENDIAN);
 277     sysbus_init_mmio(dev, R_MAX * 4, uart_regs);
 278
 279     s->chr = qdev_init_chardev(&dev->qdev);
 280     if (s->chr) {
 281         qemu_chr_fe_open(s->chr);
 282         uart_update_handlers(s);
 283     }
 284
 285     return 0;
 286 }
 287
 288 static const VMStateDescription vmstate_lm32_uart = {
 289     .name = "lm32-uart",
 290     .version_id = 1,
 291     .minimum_version_id = 1,
 292     .minimum_version_id_old = 1,
 293     .fields      = (VMStateField[]) {
 294         VMSTATE_UINT32_ARRAY(regs, LM32UartState, R_MAX),
 295         VMSTATE_END_OF_LIST()
 296     }
 297 };
 298
 299 static SysBusDeviceInfo lm32_uart_info = {
 300     .init = lm32_uart_init,
 301     .qdev.name  = "lm32-uart",
 302     .qdev.size  = sizeof(LM32UartState),
 303     .qdev.vmsd  = &vmstate_lm32_uart,
 304     .qdev.reset = uart_reset,
 305 };
 306
 307 static void lm32_uart_register(void)
 308 {
 309     sysbus_register_withprop(&lm32_uart_info);
 310 }
 311
 312 device_init(lm32_uart_register)