hw/mc146818rtc.c

   1 /*
   2  * QEMU MC146818 RTC emulation
   3  *
   4  * Copyright (c) 2003-2004 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "hw.h"
  25 #include "qemu-timer.h"
  26 #include "sysemu.h"
  27 #include "pc.h"
  28 #include "apic.h"
  29 #include "isa.h"
  30 #include "mc146818rtc.h"
  31
  32 //#define DEBUG_CMOS
  33 //#define DEBUG_COALESCED
  34
  35 #ifdef DEBUG_CMOS
  36 # define CMOS_DPRINTF(format, ...)      printf(format, ## __VA_ARGS__)
  37 #else
  38 # define CMOS_DPRINTF(format, ...)      do { } while (0)
  39 #endif
  40
  41 #ifdef DEBUG_COALESCED
  42 # define DPRINTF_C(format, ...)      printf(format, ## __VA_ARGS__)
  43 #else
  44 # define DPRINTF_C(format, ...)      do { } while (0)
  45 #endif
  46
  47 #define RTC_REINJECT_ON_ACK_COUNT 20
  48
  49 #define RTC_SECONDS             0
  50 #define RTC_SECONDS_ALARM       1
  51 #define RTC_MINUTES             2
  52 #define RTC_MINUTES_ALARM       3
  53 #define RTC_HOURS               4
  54 #define RTC_HOURS_ALARM         5
  55 #define RTC_ALARM_DONT_CARE    0xC0
  56
  57 #define RTC_DAY_OF_WEEK         6
  58 #define RTC_DAY_OF_MONTH        7
  59 #define RTC_MONTH               8
  60 #define RTC_YEAR                9
  61
  62 #define RTC_REG_A               10
  63 #define RTC_REG_B               11
  64 #define RTC_REG_C               12
  65 #define RTC_REG_D               13
  66
  67 #define REG_A_UIP 0x80
  68
  69 #define REG_B_SET  0x80
  70 #define REG_B_PIE  0x40
  71 #define REG_B_AIE  0x20
  72 #define REG_B_UIE  0x10
  73 #define REG_B_SQWE 0x08
  74 #define REG_B_DM   0x04
  75 #define REG_B_24H  0x02
  76
  77 #define REG_C_UF   0x10
  78 #define REG_C_IRQF 0x80
  79 #define REG_C_PF   0x40
  80 #define REG_C_AF   0x20
  81
  82 typedef struct RTCState {
  83     ISADevice dev;
  84     uint8_t cmos_data[128];
  85     uint8_t cmos_index;
  86     struct tm current_tm;
  87     int32_t base_year;
  88     qemu_irq irq;
  89     qemu_irq sqw_irq;
  90     int it_shift;
  91     /* periodic timer */
  92     QEMUTimer *periodic_timer;
  93     int64_t next_periodic_time;
  94     /* second update */
  95     int64_t next_second_time;
  96     uint16_t irq_reinject_on_ack_count;
  97     uint32_t irq_coalesced;
  98     uint32_t period;
  99     QEMUTimer *coalesced_timer;
 100     QEMUTimer *second_timer;
 101     QEMUTimer *second_timer2;
 102     Notifier clock_reset_notifier;
 103 } RTCState;
 104
 105 static void rtc_set_time(RTCState *s);
 106 static void rtc_copy_date(RTCState *s);
 107
 108 #ifdef TARGET_I386
 109 static void rtc_coalesced_timer_update(RTCState *s)
 110 {
 111     if (s->irq_coalesced == 0) {
 112         qemu_del_timer(s->coalesced_timer);
 113     } else {
 114         /* divide each RTC interval to 2 - 8 smaller intervals */
 115         int c = MIN(s->irq_coalesced, 7) + 1;
 116         int64_t next_clock = qemu_get_clock_ns(rtc_clock) +
 117             muldiv64(s->period / c, get_ticks_per_sec(), 32768);
 118         qemu_mod_timer(s->coalesced_timer, next_clock);
 119     }
 120 }
 121
 122 static void rtc_coalesced_timer(void *opaque)
 123 {
 124     RTCState *s = opaque;
 125
 126     if (s->irq_coalesced != 0) {
 127         apic_reset_irq_delivered();
 128         s->cmos_data[RTC_REG_C] |= 0xc0;
 129         DPRINTF_C("cmos: injecting from timer\n");
 130         qemu_irq_raise(s->irq);
 131         if (apic_get_irq_delivered()) {
 132             s->irq_coalesced--;
 133             DPRINTF_C("cmos: coalesced irqs decreased to %d\n",
 134                       s->irq_coalesced);
 135         }
 136     }
 137
 138     rtc_coalesced_timer_update(s);
 139 }
 140 #endif
 141
 142 static void rtc_timer_update(RTCState *s, int64_t current_time)
 143 {
 144     int period_code, period;
 145     int64_t cur_clock, next_irq_clock;
 146
 147     period_code = s->cmos_data[RTC_REG_A] & 0x0f;
 148     if (period_code != 0
 149         && ((s->cmos_data[RTC_REG_B] & REG_B_PIE)
 150             || ((s->cmos_data[RTC_REG_B] & REG_B_SQWE) && s->sqw_irq))) {
 151         if (period_code <= 2)
 152             period_code += 7;
 153         /* period in 32 Khz cycles */
 154         period = 1 << (period_code - 1);
 155 #ifdef TARGET_I386
 156         if (period != s->period) {
 157             s->irq_coalesced = (s->irq_coalesced * s->period) / period;
 158             DPRINTF_C("cmos: coalesced irqs scaled to %d\n", s->irq_coalesced);
 159         }
 160         s->period = period;
 161 #endif
 162         /* compute 32 khz clock */
 163         cur_clock = muldiv64(current_time, 32768, get_ticks_per_sec());
 164         next_irq_clock = (cur_clock & ~(period - 1)) + period;
 165         s->next_periodic_time =
 166             muldiv64(next_irq_clock, get_ticks_per_sec(), 32768) + 1;
 167         qemu_mod_timer(s->periodic_timer, s->next_periodic_time);
 168     } else {
 169 #ifdef TARGET_I386
 170         s->irq_coalesced = 0;
 171 #endif
 172         qemu_del_timer(s->periodic_timer);
 173     }
 174 }
 175
 176 static void rtc_periodic_timer(void *opaque)
 177 {
 178     RTCState *s = opaque;
 179
 180     rtc_timer_update(s, s->next_periodic_time);
 181     if (s->cmos_data[RTC_REG_B] & REG_B_PIE) {
 182         s->cmos_data[RTC_REG_C] |= 0xc0;
 183 #ifdef TARGET_I386
 184         if(rtc_td_hack) {
 185             if (s->irq_reinject_on_ack_count >= RTC_REINJECT_ON_ACK_COUNT)
 186                 s->irq_reinject_on_ack_count = 0;
 187             apic_reset_irq_delivered();
 188             qemu_irq_raise(s->irq);
 189             if (!apic_get_irq_delivered()) {
 190                 s->irq_coalesced++;
 191                 rtc_coalesced_timer_update(s);
 192                 DPRINTF_C("cmos: coalesced irqs increased to %d\n",
 193                           s->irq_coalesced);
 194             }
 195         } else
 196 #endif
 197         qemu_irq_raise(s->irq);
 198     }
 199     if (s->cmos_data[RTC_REG_B] & REG_B_SQWE) {
 200         /* Not square wave at all but we don't want 2048Hz interrupts!
 201            Must be seen as a pulse.  */
 202         qemu_irq_raise(s->sqw_irq);
 203     }
 204 }
 205
 206 static void cmos_ioport_write(void *opaque, uint32_t addr, uint32_t data)
 207 {
 208     RTCState *s = opaque;
 209
 210     if ((addr & 1) == 0) {
 211         s->cmos_index = data & 0x7f;
 212     } else {
 213         CMOS_DPRINTF("cmos: write index=0x%02x val=0x%02x\n",
 214                      s->cmos_index, data);
 215         switch(s->cmos_index) {
 216         case RTC_SECONDS_ALARM:
 217         case RTC_MINUTES_ALARM:
 218         case RTC_HOURS_ALARM:
 219             s->cmos_data[s->cmos_index] = data;
 220             break;
 221         case RTC_SECONDS:
 222         case RTC_MINUTES:
 223         case RTC_HOURS:
 224         case RTC_DAY_OF_WEEK:
 225         case RTC_DAY_OF_MONTH:
 226         case RTC_MONTH:
 227         case RTC_YEAR:
 228             s->cmos_data[s->cmos_index] = data;
 229             /* if in set mode, do not update the time */
 230             if (!(s->cmos_data[RTC_REG_B] & REG_B_SET)) {
 231                 rtc_set_time(s);
 232             }
 233             break;
 234         case RTC_REG_A:
 235             /* UIP bit is read only */
 236             s->cmos_data[RTC_REG_A] = (data & ~REG_A_UIP) |
 237                 (s->cmos_data[RTC_REG_A] & REG_A_UIP);
 238             rtc_timer_update(s, qemu_get_clock_ns(rtc_clock));
 239             break;
 240         case RTC_REG_B:
 241             if (data & REG_B_SET) {
 242                 /* set mode: reset UIP mode */
 243                 s->cmos_data[RTC_REG_A] &= ~REG_A_UIP;
 244                 data &= ~REG_B_UIE;
 245             } else {
 246                 /* if disabling set mode, update the time */
 247                 if (s->cmos_data[RTC_REG_B] & REG_B_SET) {
 248                     rtc_set_time(s);
 249                 }
 250             }
 251             if (((s->cmos_data[RTC_REG_B] ^ data) & (REG_B_DM | REG_B_24H)) &&
 252                 !(data & REG_B_SET)) {
 253                 /* If the time format has changed and not in set mode,
 254                    update the registers immediately. */
 255                 s->cmos_data[RTC_REG_B] = data;
 256                 rtc_copy_date(s);
 257             } else {
 258                 s->cmos_data[RTC_REG_B] = data;
 259             }
 260             rtc_timer_update(s, qemu_get_clock_ns(rtc_clock));
 261             break;
 262         case RTC_REG_C:
 263         case RTC_REG_D:
 264             /* cannot write to them */
 265             break;
 266         default:
 267             s->cmos_data[s->cmos_index] = data;
 268             break;
 269         }
 270     }
 271 }
 272
 273 static inline int rtc_to_bcd(RTCState *s, int a)
 274 {
 275     if (s->cmos_data[RTC_REG_B] & REG_B_DM) {
 276         return a;
 277     } else {
 278         return ((a / 10) << 4) | (a % 10);
 279     }
 280 }
 281
 282 static inline int rtc_from_bcd(RTCState *s, int a)
 283 {
 284     if (s->cmos_data[RTC_REG_B] & REG_B_DM) {
 285         return a;
 286     } else {
 287         return ((a >> 4) * 10) + (a & 0x0f);
 288     }
 289 }
 290
 291 static void rtc_set_time(RTCState *s)
 292 {
 293     struct tm *tm = &s->current_tm;
 294
 295     tm->tm_sec = rtc_from_bcd(s, s->cmos_data[RTC_SECONDS]);
 296     tm->tm_min = rtc_from_bcd(s, s->cmos_data[RTC_MINUTES]);
 297     tm->tm_hour = rtc_from_bcd(s, s->cmos_data[RTC_HOURS] & 0x7f);
 298     if (!(s->cmos_data[RTC_REG_B] & REG_B_24H) &&
 299         (s->cmos_data[RTC_HOURS] & 0x80)) {
 300         tm->tm_hour += 12;
 301     }
 302     tm->tm_wday = rtc_from_bcd(s, s->cmos_data[RTC_DAY_OF_WEEK]) - 1;
 303     tm->tm_mday = rtc_from_bcd(s, s->cmos_data[RTC_DAY_OF_MONTH]);
 304     tm->tm_mon = rtc_from_bcd(s, s->cmos_data[RTC_MONTH]) - 1;
 305     tm->tm_year = rtc_from_bcd(s, s->cmos_data[RTC_YEAR]) + s->base_year - 1900;
 306
 307     rtc_change_mon_event(tm);
 308 }
 309
 310 static void rtc_copy_date(RTCState *s)
 311 {
 312     const struct tm *tm = &s->current_tm;
 313     int year;
 314
 315     s->cmos_data[RTC_SECONDS] = rtc_to_bcd(s, tm->tm_sec);
 316     s->cmos_data[RTC_MINUTES] = rtc_to_bcd(s, tm->tm_min);
 317     if (s->cmos_data[RTC_REG_B] & REG_B_24H) {
 318         /* 24 hour format */
 319         s->cmos_data[RTC_HOURS] = rtc_to_bcd(s, tm->tm_hour);
 320     } else {
 321         /* 12 hour format */
 322         s->cmos_data[RTC_HOURS] = rtc_to_bcd(s, tm->tm_hour % 12);
 323         if (tm->tm_hour >= 12)
 324             s->cmos_data[RTC_HOURS] |= 0x80;
 325     }
 326     s->cmos_data[RTC_DAY_OF_WEEK] = rtc_to_bcd(s, tm->tm_wday + 1);
 327     s->cmos_data[RTC_DAY_OF_MONTH] = rtc_to_bcd(s, tm->tm_mday);
 328     s->cmos_data[RTC_MONTH] = rtc_to_bcd(s, tm->tm_mon + 1);
 329     year = (tm->tm_year - s->base_year) % 100;
 330     if (year < 0)
 331         year += 100;
 332     s->cmos_data[RTC_YEAR] = rtc_to_bcd(s, year);
 333 }
 334
 335 /* month is between 0 and 11. */
 336 static int get_days_in_month(int month, int year)
 337 {
 338     static const int days_tab[12] = {
 339         31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31
 340     };
 341     int d;
 342     if ((unsigned )month >= 12)
 343         return 31;
 344     d = days_tab[month];
 345     if (month == 1) {
 346         if ((year % 4) == 0 && ((year % 100) != 0 || (year % 400) == 0))
 347             d++;
 348     }
 349     return d;
 350 }
 351
 352 /* update 'tm' to the next second */
 353 static void rtc_next_second(struct tm *tm)
 354 {
 355     int days_in_month;
 356
 357     tm->tm_sec++;
 358     if ((unsigned)tm->tm_sec >= 60) {
 359         tm->tm_sec = 0;
 360         tm->tm_min++;
 361         if ((unsigned)tm->tm_min >= 60) {
 362             tm->tm_min = 0;
 363             tm->tm_hour++;
 364             if ((unsigned)tm->tm_hour >= 24) {
 365                 tm->tm_hour = 0;
 366                 /* next day */
 367                 tm->tm_wday++;
 368                 if ((unsigned)tm->tm_wday >= 7)
 369                     tm->tm_wday = 0;
 370                 days_in_month = get_days_in_month(tm->tm_mon,
 371                                                   tm->tm_year + 1900);
 372                 tm->tm_mday++;
 373                 if (tm->tm_mday < 1) {
 374                     tm->tm_mday = 1;
 375                 } else if (tm->tm_mday > days_in_month) {
 376                     tm->tm_mday = 1;
 377                     tm->tm_mon++;
 378                     if (tm->tm_mon >= 12) {
 379                         tm->tm_mon = 0;
 380                         tm->tm_year++;
 381                     }
 382                 }
 383             }
 384         }
 385     }
 386 }
 387
 388
 389 static void rtc_update_second(void *opaque)
 390 {
 391     RTCState *s = opaque;
 392     int64_t delay;
 393
 394     /* if the oscillator is not in normal operation, we do not update */
 395     if ((s->cmos_data[RTC_REG_A] & 0x70) != 0x20) {
 396         s->next_second_time += get_ticks_per_sec();
 397         qemu_mod_timer(s->second_timer, s->next_second_time);
 398     } else {
 399         rtc_next_second(&s->current_tm);
 400
 401         if (!(s->cmos_data[RTC_REG_B] & REG_B_SET)) {
 402             /* update in progress bit */
 403             s->cmos_data[RTC_REG_A] |= REG_A_UIP;
 404         }
 405         /* should be 244 us = 8 / 32768 seconds, but currently the
 406            timers do not have the necessary resolution. */
 407         delay = (get_ticks_per_sec() * 1) / 100;
 408         if (delay < 1)
 409             delay = 1;
 410         qemu_mod_timer(s->second_timer2,
 411                        s->next_second_time + delay);
 412     }
 413 }
 414
 415 static void rtc_update_second2(void *opaque)
 416 {
 417     RTCState *s = opaque;
 418
 419     if (!(s->cmos_data[RTC_REG_B] & REG_B_SET)) {
 420         rtc_copy_date(s);
 421     }
 422
 423     /* check alarm */
 424     if (s->cmos_data[RTC_REG_B] & REG_B_AIE) {
 425         if (((s->cmos_data[RTC_SECONDS_ALARM] & 0xc0) == 0xc0 ||
 426              rtc_from_bcd(s, s->cmos_data[RTC_SECONDS_ALARM]) == s->current_tm.tm_sec) &&
 427             ((s->cmos_data[RTC_MINUTES_ALARM] & 0xc0) == 0xc0 ||
 428              rtc_from_bcd(s, s->cmos_data[RTC_MINUTES_ALARM]) == s->current_tm.tm_min) &&
 429             ((s->cmos_data[RTC_HOURS_ALARM] & 0xc0) == 0xc0 ||
 430              rtc_from_bcd(s, s->cmos_data[RTC_HOURS_ALARM]) == s->current_tm.tm_hour)) {
 431
 432             s->cmos_data[RTC_REG_C] |= 0xa0;
 433             qemu_irq_raise(s->irq);
 434         }
 435     }
 436
 437     /* update ended interrupt */
 438     s->cmos_data[RTC_REG_C] |= REG_C_UF;
 439     if (s->cmos_data[RTC_REG_B] & REG_B_UIE) {
 440         s->cmos_data[RTC_REG_C] |= REG_C_IRQF;
 441         qemu_irq_raise(s->irq);
 442     }
 443
 444     /* clear update in progress bit */
 445     s->cmos_data[RTC_REG_A] &= ~REG_A_UIP;
 446
 447     s->next_second_time += get_ticks_per_sec();
 448     qemu_mod_timer(s->second_timer, s->next_second_time);
 449 }
 450
 451 static uint32_t cmos_ioport_read(void *opaque, uint32_t addr)
 452 {
 453     RTCState *s = opaque;
 454     int ret;
 455     if ((addr & 1) == 0) {
 456         return 0xff;
 457     } else {
 458         switch(s->cmos_index) {
 459         case RTC_SECONDS:
 460         case RTC_MINUTES:
 461         case RTC_HOURS:
 462         case RTC_DAY_OF_WEEK:
 463         case RTC_DAY_OF_MONTH:
 464         case RTC_MONTH:
 465         case RTC_YEAR:
 466             ret = s->cmos_data[s->cmos_index];
 467             break;
 468         case RTC_REG_A:
 469             ret = s->cmos_data[s->cmos_index];
 470             break;
 471         case RTC_REG_C:
 472             ret = s->cmos_data[s->cmos_index];
 473             qemu_irq_lower(s->irq);
 474 #ifdef TARGET_I386
 475             if(s->irq_coalesced &&
 476                     s->irq_reinject_on_ack_count < RTC_REINJECT_ON_ACK_COUNT) {
 477                 s->irq_reinject_on_ack_count++;
 478                 apic_reset_irq_delivered();
 479                 DPRINTF_C("cmos: injecting on ack\n");
 480                 qemu_irq_raise(s->irq);
 481                 if (apic_get_irq_delivered()) {
 482                     s->irq_coalesced--;
 483                     DPRINTF_C("cmos: coalesced irqs decreased to %d\n",
 484                               s->irq_coalesced);
 485                 }
 486                 break;
 487             }
 488 #endif
 489
 490             s->cmos_data[RTC_REG_C] = 0x00;
 491             break;
 492         default:
 493             ret = s->cmos_data[s->cmos_index];
 494             break;
 495         }
 496         CMOS_DPRINTF("cmos: read index=0x%02x val=0x%02x\n",
 497                      s->cmos_index, ret);
 498         return ret;
 499     }
 500 }
 501
 502 void rtc_set_memory(ISADevice *dev, int addr, int val)
 503 {
 504     RTCState *s = DO_UPCAST(RTCState, dev, dev);
 505     if (addr >= 0 && addr <= 127)
 506         s->cmos_data[addr] = val;
 507 }
 508
 509 void rtc_set_date(ISADevice *dev, const struct tm *tm)
 510 {
 511     RTCState *s = DO_UPCAST(RTCState, dev, dev);
 512     s->current_tm = *tm;
 513     rtc_copy_date(s);
 514 }
 515
 516 /* PC cmos mappings */
 517 #define REG_IBM_CENTURY_BYTE        0x32
 518 #define REG_IBM_PS2_CENTURY_BYTE    0x37
 519
 520 static void rtc_set_date_from_host(ISADevice *dev)
 521 {
 522     RTCState *s = DO_UPCAST(RTCState, dev, dev);
 523     struct tm tm;
 524     int val;
 525
 526     /* set the CMOS date */
 527     qemu_get_timedate(&tm, 0);
 528     rtc_set_date(dev, &tm);
 529
 530     val = rtc_to_bcd(s, (tm.tm_year / 100) + 19);
 531     rtc_set_memory(dev, REG_IBM_CENTURY_BYTE, val);
 532     rtc_set_memory(dev, REG_IBM_PS2_CENTURY_BYTE, val);
 533 }
 534
 535 static int rtc_post_load(void *opaque, int version_id)
 536 {
 537 #ifdef TARGET_I386
 538     RTCState *s = opaque;
 539
 540     if (version_id >= 2) {
 541         if (rtc_td_hack) {
 542             rtc_coalesced_timer_update(s);
 543         }
 544     }
 545 #endif
 546     return 0;
 547 }
 548
 549 static const VMStateDescription vmstate_rtc = {
 550     .name = "mc146818rtc",
 551     .version_id = 2,
 552     .minimum_version_id = 1,
 553     .minimum_version_id_old = 1,
 554     .post_load = rtc_post_load,
 555     .fields      = (VMStateField []) {
 556         VMSTATE_BUFFER(cmos_data, RTCState),
 557         VMSTATE_UINT8(cmos_index, RTCState),
 558         VMSTATE_INT32(current_tm.tm_sec, RTCState),
 559         VMSTATE_INT32(current_tm.tm_min, RTCState),
 560         VMSTATE_INT32(current_tm.tm_hour, RTCState),
 561         VMSTATE_INT32(current_tm.tm_wday, RTCState),
 562         VMSTATE_INT32(current_tm.tm_mday, RTCState),
 563         VMSTATE_INT32(current_tm.tm_mon, RTCState),
 564         VMSTATE_INT32(current_tm.tm_year, RTCState),
 565         VMSTATE_TIMER(periodic_timer, RTCState),
 566         VMSTATE_INT64(next_periodic_time, RTCState),
 567         VMSTATE_INT64(next_second_time, RTCState),
 568         VMSTATE_TIMER(second_timer, RTCState),
 569         VMSTATE_TIMER(second_timer2, RTCState),
 570         VMSTATE_UINT32_V(irq_coalesced, RTCState, 2),
 571         VMSTATE_UINT32_V(period, RTCState, 2),
 572         VMSTATE_END_OF_LIST()
 573     }
 574 };
 575
 576 static void rtc_notify_clock_reset(Notifier *notifier, void *data)
 577 {
 578     RTCState *s = container_of(notifier, RTCState, clock_reset_notifier);
 579     int64_t now = *(int64_t *)data;
 580
 581     rtc_set_date_from_host(&s->dev);
 582     s->next_second_time = now + (get_ticks_per_sec() * 99) / 100;
 583     qemu_mod_timer(s->second_timer2, s->next_second_time);
 584     rtc_timer_update(s, now);
 585 #ifdef TARGET_I386
 586     if (rtc_td_hack) {
 587         rtc_coalesced_timer_update(s);
 588     }
 589 #endif
 590 }
 591
 592 static void rtc_reset(void *opaque)
 593 {
 594     RTCState *s = opaque;
 595
 596     s->cmos_data[RTC_REG_B] &= ~(REG_B_PIE | REG_B_AIE | REG_B_SQWE);
 597     s->cmos_data[RTC_REG_C] &= ~(REG_C_UF | REG_C_IRQF | REG_C_PF | REG_C_AF);
 598
 599     qemu_irq_lower(s->irq);
 600
 601 #ifdef TARGET_I386
 602     if (rtc_td_hack)
 603             s->irq_coalesced = 0;
 604 #endif
 605 }
 606
 607 static int rtc_initfn(ISADevice *dev)
 608 {
 609     RTCState *s = DO_UPCAST(RTCState, dev, dev);
 610     int base = 0x70;
 611
 612     s->cmos_data[RTC_REG_A] = 0x26;
 613     s->cmos_data[RTC_REG_B] = 0x02;
 614     s->cmos_data[RTC_REG_C] = 0x00;
 615     s->cmos_data[RTC_REG_D] = 0x80;
 616
 617     rtc_set_date_from_host(dev);
 618
 619     s->periodic_timer = qemu_new_timer_ns(rtc_clock, rtc_periodic_timer, s);
 620 #ifdef TARGET_I386
 621     if (rtc_td_hack)
 622         s->coalesced_timer =
 623             qemu_new_timer_ns(rtc_clock, rtc_coalesced_timer, s);
 624 #endif
 625     s->second_timer = qemu_new_timer_ns(rtc_clock, rtc_update_second, s);
 626     s->second_timer2 = qemu_new_timer_ns(rtc_clock, rtc_update_second2, s);
 627
 628     s->clock_reset_notifier.notify = rtc_notify_clock_reset;
 629     qemu_register_clock_reset_notifier(rtc_clock, &s->clock_reset_notifier);
 630
 631     s->next_second_time =
 632         qemu_get_clock_ns(rtc_clock) + (get_ticks_per_sec() * 99) / 100;
 633     qemu_mod_timer(s->second_timer2, s->next_second_time);
 634
 635     register_ioport_write(base, 2, 1, cmos_ioport_write, s);
 636     register_ioport_read(base, 2, 1, cmos_ioport_read, s);
 637     isa_init_ioport_range(dev, base, 2);
 638
 639     qdev_set_legacy_instance_id(&dev->qdev, base, 2);
 640     qemu_register_reset(rtc_reset, s);
 641     return 0;
 642 }
 643
 644 ISADevice *rtc_init(int base_year, qemu_irq intercept_irq)
 645 {
 646     ISADevice *dev;
 647     RTCState *s;
 648
 649     dev = isa_create("mc146818rtc");
 650     s = DO_UPCAST(RTCState, dev, dev);
 651     qdev_prop_set_int32(&dev->qdev, "base_year", base_year);
 652     qdev_init_nofail(&dev->qdev);
 653     if (intercept_irq) {
 654         s->irq = intercept_irq;
 655     } else {
 656         isa_init_irq(dev, &s->irq, RTC_ISA_IRQ);
 657     }
 658     return dev;
 659 }
 660
 661 static ISADeviceInfo mc146818rtc_info = {
 662     .qdev.name     = "mc146818rtc",
 663     .qdev.size     = sizeof(RTCState),
 664     .qdev.no_user  = 1,
 665     .qdev.vmsd     = &vmstate_rtc,
 666     .init          = rtc_initfn,
 667     .qdev.props    = (Property[]) {
 668         DEFINE_PROP_INT32("base_year", RTCState, base_year, 1980),
 669         DEFINE_PROP_END_OF_LIST(),
 670     }
 671 };
 672
 673 static void mc146818rtc_register(void)
 674 {
 675     isa_qdev_register(&mc146818rtc_info);
 676 }
 677 device_init(mc146818rtc_register)