hw/pcie.h

   1 /*
   2  * pcie.h
   3  *
   4  * Copyright (c) 2010 Isaku Yamahata <yamahata at valinux co jp>
   5  *                    VA Linux Systems Japan K.K.
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License along
  18  * with this program; if not, see <http://www.gnu.org/licenses/>.
  19  */
  20
  21 #ifndef QEMU_PCIE_H
  22 #define QEMU_PCIE_H
  23
  24 #include "hw.h"
  25 #include "pci_regs.h"
  26 #include "pcie_regs.h"
  27 #include "pcie_aer.h"
  28
  29 typedef enum {
  30     /* for attention and power indicator */
  31     PCI_EXP_HP_IND_RESERVED     = PCI_EXP_SLTCTL_IND_RESERVED,
  32     PCI_EXP_HP_IND_ON           = PCI_EXP_SLTCTL_IND_ON,
  33     PCI_EXP_HP_IND_BLINK        = PCI_EXP_SLTCTL_IND_BLINK,
  34     PCI_EXP_HP_IND_OFF          = PCI_EXP_SLTCTL_IND_OFF,
  35 } PCIExpressIndicator;
  36
  37 typedef enum {
  38     /* these bits must match the bits in Slot Control/Status registers.
  39      * PCI_EXP_HP_EV_xxx = PCI_EXP_SLTCTL_xxxE = PCI_EXP_SLTSTA_xxx
  40      *
  41      * Not all the bits of slot control register match with the ones of
  42      * slot status. Not some bits of slot status register is used to
  43      * show status, not to report event occurrence.
  44      * So such bits must be masked out when checking the software
  45      * notification condition.
  46      */
  47     PCI_EXP_HP_EV_ABP           = PCI_EXP_SLTCTL_ABPE,
  48                                         /* attention button pressed */
  49     PCI_EXP_HP_EV_PDC           = PCI_EXP_SLTCTL_PDCE,
  50                                         /* presence detect changed */
  51     PCI_EXP_HP_EV_CCI           = PCI_EXP_SLTCTL_CCIE,
  52                                         /* command completed */
  53
  54     PCI_EXP_HP_EV_SUPPORTED     = PCI_EXP_HP_EV_ABP |
  55                                   PCI_EXP_HP_EV_PDC |
  56                                   PCI_EXP_HP_EV_CCI,
  57                                                 /* supported event mask  */
  58
  59     /* events not listed aren't supported */
  60 } PCIExpressHotPlugEvent;
  61
  62 struct PCIExpressDevice {
  63     /* Offset of express capability in config space */
  64     uint8_t exp_cap;
  65
  66     /* SLOT */
  67     unsigned int hpev_intx;     /* INTx for hot plug event (0-3:INT[A-D]#)
  68                                  * default is 0 = INTA#
  69                                  * If the chip wants to use other interrupt
  70                                  * line, initialize this member with the
  71                                  * desired number.
  72                                  * If the chip dynamically changes this member,
  73                                  * also initialize it when loaded as
  74                                  * appropreately.
  75                                  */
  76     bool hpev_notified; /* Logical AND of conditions for hot plug event.
  77                          Following 6.7.3.4:
  78                          Software Notification of Hot-Plug Events, an interrupt
  79                          is sent whenever the logical and of these conditions
  80                          transitions from false to true. */
  81
  82     /* AER */
  83     uint16_t aer_cap;
  84     PCIEAERLog aer_log;
  85     unsigned int aer_intx;      /* INTx for error reporting
  86                                  * default is 0 = INTA#
  87                                  * If the chip wants to use other interrupt
  88                                  * line, initialize this member with the
  89                                  * desired number.
  90                                  * If the chip dynamically changes this member,
  91                                  * also initialize it when loaded as
  92                                  * appropreately.
  93                                  */
  94 };
  95
  96 /* PCI express capability helper functions */
  97 int pcie_cap_init(PCIDevice *dev, uint8_t offset, uint8_t type, uint8_t port);
  98 void pcie_cap_exit(PCIDevice *dev);
  99 uint8_t pcie_cap_get_type(const PCIDevice *dev);
 100 void pcie_cap_flags_set_vector(PCIDevice *dev, uint8_t vector);
 101 uint8_t pcie_cap_flags_get_vector(PCIDevice *dev);
 102
 103 void pcie_cap_deverr_init(PCIDevice *dev);
 104 void pcie_cap_deverr_reset(PCIDevice *dev);
 105
 106 void pcie_cap_slot_init(PCIDevice *dev, uint16_t slot);
 107 void pcie_cap_slot_reset(PCIDevice *dev);
 108 void pcie_cap_slot_write_config(PCIDevice *dev,
 109                                 uint32_t addr, uint32_t val, int len);
 110 int pcie_cap_slot_post_load(void *opaque, int version_id);
 111 void pcie_cap_slot_push_attention_button(PCIDevice *dev);
 112
 113 void pcie_cap_root_init(PCIDevice *dev);
 114 void pcie_cap_root_reset(PCIDevice *dev);
 115
 116 void pcie_cap_flr_init(PCIDevice *dev);
 117 void pcie_cap_flr_write_config(PCIDevice *dev,
 118                            uint32_t addr, uint32_t val, int len);
 119
 120 void pcie_cap_ari_init(PCIDevice *dev);
 121 void pcie_cap_ari_reset(PCIDevice *dev);
 122 bool pcie_cap_is_ari_enabled(const PCIDevice *dev);
 123
 124 /* PCI express extended capability helper functions */
 125 uint16_t pcie_find_capability(PCIDevice *dev, uint16_t cap_id);
 126 void pcie_add_capability(PCIDevice *dev,
 127                          uint16_t cap_id, uint8_t cap_ver,
 128                          uint16_t offset, uint16_t size);
 129
 130 void pcie_ari_init(PCIDevice *dev, uint16_t offset, uint16_t nextfn);
 131
 132 #endif /* QEMU_PCIE_H */