hw/serial.c

   1 /*
   2  * QEMU 16550A UART emulation
   3  *
   4  * Copyright (c) 2003-2004 Fabrice Bellard
   5  * Copyright (c) 2008 Citrix Systems, Inc.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a copy
   8  * of this software and associated documentation files (the "Software"), to deal
   9  * in the Software without restriction, including without limitation the rights
  10  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  11  * copies of the Software, and to permit persons to whom the Software is
  12  * furnished to do so, subject to the following conditions:
  13  *
  14  * The above copyright notice and this permission notice shall be included in
  15  * all copies or substantial portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  23  * THE SOFTWARE.
  24  */
  25 #include "hw.h"
  26 #include "qemu-char.h"
  27 #include "isa.h"
  28 #include "pc.h"
  29 #include "qemu-timer.h"
  30 #include "sysemu.h"
  31
  32 //#define DEBUG_SERIAL
  33
  34 #define UART_LCR_DLAB   0x80    /* Divisor latch access bit */
  35
  36 #define UART_IER_MSI    0x08    /* Enable Modem status interrupt */
  37 #define UART_IER_RLSI   0x04    /* Enable receiver line status interrupt */
  38 #define UART_IER_THRI   0x02    /* Enable Transmitter holding register int. */
  39 #define UART_IER_RDI    0x01    /* Enable receiver data interrupt */
  40
  41 #define UART_IIR_NO_INT 0x01    /* No interrupts pending */
  42 #define UART_IIR_ID     0x06    /* Mask for the interrupt ID */
  43
  44 #define UART_IIR_MSI    0x00    /* Modem status interrupt */
  45 #define UART_IIR_THRI   0x02    /* Transmitter holding register empty */
  46 #define UART_IIR_RDI    0x04    /* Receiver data interrupt */
  47 #define UART_IIR_RLSI   0x06    /* Receiver line status interrupt */
  48 #define UART_IIR_CTI    0x0C    /* Character Timeout Indication */
  49
  50 #define UART_IIR_FENF   0x80    /* Fifo enabled, but not functionning */
  51 #define UART_IIR_FE     0xC0    /* Fifo enabled */
  52
  53 /*
  54  * These are the definitions for the Modem Control Register
  55  */
  56 #define UART_MCR_LOOP   0x10    /* Enable loopback test mode */
  57 #define UART_MCR_OUT2   0x08    /* Out2 complement */
  58 #define UART_MCR_OUT1   0x04    /* Out1 complement */
  59 #define UART_MCR_RTS    0x02    /* RTS complement */
  60 #define UART_MCR_DTR    0x01    /* DTR complement */
  61
  62 /*
  63  * These are the definitions for the Modem Status Register
  64  */
  65 #define UART_MSR_DCD    0x80    /* Data Carrier Detect */
  66 #define UART_MSR_RI     0x40    /* Ring Indicator */
  67 #define UART_MSR_DSR    0x20    /* Data Set Ready */
  68 #define UART_MSR_CTS    0x10    /* Clear to Send */
  69 #define UART_MSR_DDCD   0x08    /* Delta DCD */
  70 #define UART_MSR_TERI   0x04    /* Trailing edge ring indicator */
  71 #define UART_MSR_DDSR   0x02    /* Delta DSR */
  72 #define UART_MSR_DCTS   0x01    /* Delta CTS */
  73 #define UART_MSR_ANY_DELTA 0x0F /* Any of the delta bits! */
  74
  75 #define UART_LSR_TEMT   0x40    /* Transmitter empty */
  76 #define UART_LSR_THRE   0x20    /* Transmit-hold-register empty */
  77 #define UART_LSR_BI     0x10    /* Break interrupt indicator */
  78 #define UART_LSR_FE     0x08    /* Frame error indicator */
  79 #define UART_LSR_PE     0x04    /* Parity error indicator */
  80 #define UART_LSR_OE     0x02    /* Overrun error indicator */
  81 #define UART_LSR_DR     0x01    /* Receiver data ready */
  82 #define UART_LSR_INT_ANY 0x1E   /* Any of the lsr-interrupt-triggering status bits */
  83
  84 /* Interrupt trigger levels. The byte-counts are for 16550A - in newer UARTs the byte-count for each ITL is higher. */
  85
  86 #define UART_FCR_ITL_1      0x00 /* 1 byte ITL */
  87 #define UART_FCR_ITL_2      0x40 /* 4 bytes ITL */
  88 #define UART_FCR_ITL_3      0x80 /* 8 bytes ITL */
  89 #define UART_FCR_ITL_4      0xC0 /* 14 bytes ITL */
  90
  91 #define UART_FCR_DMS        0x08    /* DMA Mode Select */
  92 #define UART_FCR_XFR        0x04    /* XMIT Fifo Reset */
  93 #define UART_FCR_RFR        0x02    /* RCVR Fifo Reset */
  94 #define UART_FCR_FE         0x01    /* FIFO Enable */
  95
  96 #define UART_FIFO_LENGTH    16      /* 16550A Fifo Length */
  97
  98 #define XMIT_FIFO           0
  99 #define RECV_FIFO           1
 100 #define MAX_XMIT_RETRY      4
 101
 102 #ifdef DEBUG_SERIAL
 103 #define DPRINTF(fmt, ...) \
 104 do { fprintf(stderr, "serial: " fmt , ## __VA_ARGS__); } while (0)
 105 #else
 106 #define DPRINTF(fmt, ...) \
 107 do {} while (0)
 108 #endif
 109
 110 typedef struct SerialFIFO {
 111     uint8_t data[UART_FIFO_LENGTH];
 112     uint8_t count;
 113     uint8_t itl;                        /* Interrupt Trigger Level */
 114     uint8_t tail;
 115     uint8_t head;
 116 } SerialFIFO;
 117
 118 struct SerialState {
 119     uint16_t divider;
 120     uint8_t rbr; /* receive register */
 121     uint8_t thr; /* transmit holding register */
 122     uint8_t tsr; /* transmit shift register */
 123     uint8_t ier;
 124     uint8_t iir; /* read only */
 125     uint8_t lcr;
 126     uint8_t mcr;
 127     uint8_t lsr; /* read only */
 128     uint8_t msr; /* read only */
 129     uint8_t scr;
 130     uint8_t fcr;
 131     uint8_t fcr_vmstate; /* we can't write directly this value
 132                             it has side effects */
 133     /* NOTE: this hidden state is necessary for tx irq generation as
 134        it can be reset while reading iir */
 135     int thr_ipending;
 136     qemu_irq irq;
 137     CharDriverState *chr;
 138     int last_break_enable;
 139     int it_shift;
 140     int baudbase;
 141     int tsr_retry;
 142
 143     uint64_t last_xmit_ts;              /* Time when the last byte was successfully sent out of the tsr */
 144     SerialFIFO recv_fifo;
 145     SerialFIFO xmit_fifo;
 146
 147     struct QEMUTimer *fifo_timeout_timer;
 148     int timeout_ipending;                   /* timeout interrupt pending state */
 149     struct QEMUTimer *transmit_timer;
 150
 151
 152     uint64_t char_transmit_time;               /* time to transmit a char in ticks*/
 153     int poll_msl;
 154
 155     struct QEMUTimer *modem_status_poll;
 156 };
 157
 158 typedef struct ISASerialState {
 159     ISADevice dev;
 160     uint32_t index;
 161     uint32_t iobase;
 162     uint32_t isairq;
 163     SerialState state;
 164 } ISASerialState;
 165
 166 static void serial_update_handlers(SerialState *s);
 167 static void serial_receive1(SerialState *s, const uint8_t *buf, int size);
 168
 169 static void fifo_clear(SerialState *s, int fifo)
 170 {
 171     SerialFIFO *f = (fifo) ? &s->recv_fifo : &s->xmit_fifo;
 172     memset(f->data, 0, UART_FIFO_LENGTH);
 173     f->count = 0;
 174     f->head = 0;
 175     f->tail = 0;
 176     serial_update_handlers(s);
 177 }
 178
 179 static int fifo_put(SerialState *s, int fifo, uint8_t chr)
 180 {
 181     SerialFIFO *f = (fifo) ? &s->recv_fifo : &s->xmit_fifo;
 182
 183     /* Receive overruns do not overwrite FIFO contents. */
 184     if (fifo == XMIT_FIFO || f->count < UART_FIFO_LENGTH) {
 185
 186         f->data[f->head++] = chr;
 187
 188         if (f->head == UART_FIFO_LENGTH)
 189             f->head = 0;
 190     }
 191
 192     if (f->count < UART_FIFO_LENGTH)
 193         f->count++;
 194     else if (fifo == RECV_FIFO)
 195         s->lsr |= UART_LSR_OE;
 196
 197     serial_update_handlers(s);
 198
 199     return 1;
 200 }
 201
 202 static uint8_t fifo_get(SerialState *s, int fifo)
 203 {
 204     SerialFIFO *f = (fifo) ? &s->recv_fifo : &s->xmit_fifo;
 205     uint8_t c;
 206
 207     if(f->count == 0)
 208         return 0;
 209
 210     c = f->data[f->tail++];
 211     if (f->tail == UART_FIFO_LENGTH)
 212         f->tail = 0;
 213     f->count--;
 214
 215     serial_update_handlers(s);
 216
 217     return c;
 218 }
 219
 220 static void serial_update_irq(SerialState *s)
 221 {
 222     uint8_t tmp_iir = UART_IIR_NO_INT;
 223
 224     if ((s->ier & UART_IER_RLSI) && (s->lsr & UART_LSR_INT_ANY)) {
 225         tmp_iir = UART_IIR_RLSI;
 226     } else if ((s->ier & UART_IER_RDI) && s->timeout_ipending) {
 227         /* Note that(s->ier & UART_IER_RDI) can mask this interrupt,
 228          * this is not in the specification but is observed on existing
 229          * hardware.  */
 230         tmp_iir = UART_IIR_CTI;
 231     } else if ((s->ier & UART_IER_RDI) && (s->lsr & UART_LSR_DR) &&
 232                (!(s->fcr & UART_FCR_FE) ||
 233                 s->recv_fifo.count >= s->recv_fifo.itl)) {
 234         tmp_iir = UART_IIR_RDI;
 235     } else if ((s->ier & UART_IER_THRI) && s->thr_ipending) {
 236         tmp_iir = UART_IIR_THRI;
 237     } else if ((s->ier & UART_IER_MSI) && (s->msr & UART_MSR_ANY_DELTA)) {
 238         tmp_iir = UART_IIR_MSI;
 239     }
 240
 241     s->iir = tmp_iir | (s->iir & 0xF0);
 242
 243     if (tmp_iir != UART_IIR_NO_INT) {
 244         qemu_irq_raise(s->irq);
 245     } else {
 246         qemu_irq_lower(s->irq);
 247     }
 248 }
 249
 250 static void serial_update_parameters(SerialState *s)
 251 {
 252     int speed, parity, data_bits, stop_bits, frame_size;
 253     QEMUSerialSetParams ssp;
 254
 255     if (s->divider == 0)
 256         return;
 257
 258     /* Start bit. */
 259     frame_size = 1;
 260     if (s->lcr & 0x08) {
 261         /* Parity bit. */
 262         frame_size++;
 263         if (s->lcr & 0x10)
 264             parity = 'E';
 265         else
 266             parity = 'O';
 267     } else {
 268             parity = 'N';
 269     }
 270     if (s->lcr & 0x04)
 271         stop_bits = 2;
 272     else
 273         stop_bits = 1;
 274
 275     data_bits = (s->lcr & 0x03) + 5;
 276     frame_size += data_bits + stop_bits;
 277     speed = s->baudbase / s->divider;
 278     ssp.speed = speed;
 279     ssp.parity = parity;
 280     ssp.data_bits = data_bits;
 281     ssp.stop_bits = stop_bits;
 282     s->char_transmit_time =  (get_ticks_per_sec() / speed) * frame_size;
 283     qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp);
 284
 285     DPRINTF("speed=%d parity=%c data=%d stop=%d\n",
 286            speed, parity, data_bits, stop_bits);
 287 }
 288
 289 static void serial_update_msl(SerialState *s)
 290 {
 291     uint8_t omsr;
 292     int flags;
 293
 294     qemu_del_timer(s->modem_status_poll);
 295
 296     if (qemu_chr_fe_ioctl(s->chr,CHR_IOCTL_SERIAL_GET_TIOCM, &flags) == -ENOTSUP) {
 297         s->poll_msl = -1;
 298         return;
 299     }
 300
 301     omsr = s->msr;
 302
 303     s->msr = (flags & CHR_TIOCM_CTS) ? s->msr | UART_MSR_CTS : s->msr & ~UART_MSR_CTS;
 304     s->msr = (flags & CHR_TIOCM_DSR) ? s->msr | UART_MSR_DSR : s->msr & ~UART_MSR_DSR;
 305     s->msr = (flags & CHR_TIOCM_CAR) ? s->msr | UART_MSR_DCD : s->msr & ~UART_MSR_DCD;
 306     s->msr = (flags & CHR_TIOCM_RI) ? s->msr | UART_MSR_RI : s->msr & ~UART_MSR_RI;
 307
 308     if (s->msr != omsr) {
 309          /* Set delta bits */
 310          s->msr = s->msr | ((s->msr >> 4) ^ (omsr >> 4));
 311          /* UART_MSR_TERI only if change was from 1 -> 0 */
 312          if ((s->msr & UART_MSR_TERI) && !(omsr & UART_MSR_RI))
 313              s->msr &= ~UART_MSR_TERI;
 314          serial_update_irq(s);
 315     }
 316
 317     /* The real 16550A apparently has a 250ns response latency to line status changes.
 318        We'll be lazy and poll only every 10ms, and only poll it at all if MSI interrupts are turned on */
 319
 320     if (s->poll_msl)
 321         qemu_mod_timer(s->modem_status_poll, qemu_get_clock_ns(vm_clock) + get_ticks_per_sec() / 100);
 322 }
 323
 324 static void serial_xmit(void *opaque)
 325 {
 326     SerialState *s = opaque;
 327     uint64_t new_xmit_ts = qemu_get_clock_ns(vm_clock);
 328
 329     if (s->tsr_retry <= 0) {
 330         if (s->fcr & UART_FCR_FE) {
 331             s->tsr = fifo_get(s,XMIT_FIFO);
 332             if (!s->xmit_fifo.count)
 333                 s->lsr |= UART_LSR_THRE;
 334         } else {
 335             s->tsr = s->thr;
 336             s->lsr |= UART_LSR_THRE;
 337         }
 338     }
 339
 340     if (s->mcr & UART_MCR_LOOP) {
 341         /* in loopback mode, say that we just received a char */
 342         serial_receive1(s, &s->tsr, 1);
 343     } else if (qemu_chr_fe_write(s->chr, &s->tsr, 1) != 1) {
 344         if ((s->tsr_retry > 0) && (s->tsr_retry <= MAX_XMIT_RETRY)) {
 345             s->tsr_retry++;
 346             qemu_mod_timer(s->transmit_timer,  new_xmit_ts + s->char_transmit_time);
 347             return;
 348         } else if (s->poll_msl < 0) {
 349             /* If we exceed MAX_XMIT_RETRY and the backend is not a real serial port, then
 350             drop any further failed writes instantly, until we get one that goes through.
 351             This is to prevent guests that log to unconnected pipes or pty's from stalling. */
 352             s->tsr_retry = -1;
 353         }
 354     }
 355     else {
 356         s->tsr_retry = 0;
 357     }
 358
 359     s->last_xmit_ts = qemu_get_clock_ns(vm_clock);
 360     if (!(s->lsr & UART_LSR_THRE))
 361         qemu_mod_timer(s->transmit_timer, s->last_xmit_ts + s->char_transmit_time);
 362
 363     if (s->lsr & UART_LSR_THRE) {
 364         s->lsr |= UART_LSR_TEMT;
 365         s->thr_ipending = 1;
 366         serial_update_irq(s);
 367     }
 368 }
 369
 370
 371 static void serial_ioport_write(void *opaque, uint32_t addr, uint32_t val)
 372 {
 373     SerialState *s = opaque;
 374
 375     addr &= 7;
 376     DPRINTF("write addr=0x%02x val=0x%02x\n", addr, val);
 377     switch(addr) {
 378     default:
 379     case 0:
 380         if (s->lcr & UART_LCR_DLAB) {
 381             s->divider = (s->divider & 0xff00) | val;
 382             serial_update_parameters(s);
 383         } else {
 384             s->thr = (uint8_t) val;
 385             if(s->fcr & UART_FCR_FE) {
 386                 fifo_put(s, XMIT_FIFO, s->thr);
 387                 s->thr_ipending = 0;
 388                 s->lsr &= ~UART_LSR_TEMT;
 389                 s->lsr &= ~UART_LSR_THRE;
 390                 serial_update_irq(s);
 391             } else {
 392                 s->thr_ipending = 0;
 393                 s->lsr &= ~UART_LSR_THRE;
 394                 serial_update_irq(s);
 395             }
 396             serial_xmit(s);
 397         }
 398         break;
 399     case 1:
 400         if (s->lcr & UART_LCR_DLAB) {
 401             s->divider = (s->divider & 0x00ff) | (val << 8);
 402             serial_update_parameters(s);
 403         } else {
 404             s->ier = val & 0x0f;
 405             /* If the backend device is a real serial port, turn polling of the modem
 406                status lines on physical port on or off depending on UART_IER_MSI state */
 407             if (s->poll_msl >= 0) {
 408                 if (s->ier & UART_IER_MSI) {
 409                      s->poll_msl = 1;
 410                      serial_update_msl(s);
 411                 } else {
 412                      qemu_del_timer(s->modem_status_poll);
 413                      s->poll_msl = 0;
 414                 }
 415             }
 416             if (s->lsr & UART_LSR_THRE) {
 417                 s->thr_ipending = 1;
 418                 serial_update_irq(s);
 419             }
 420         }
 421         break;
 422     case 2:
 423         val = val & 0xFF;
 424
 425         if (s->fcr == val)
 426             break;
 427
 428         /* Did the enable/disable flag change? If so, make sure FIFOs get flushed */
 429         if ((val ^ s->fcr) & UART_FCR_FE)
 430             val |= UART_FCR_XFR | UART_FCR_RFR;
 431
 432         /* FIFO clear */
 433
 434         if (val & UART_FCR_RFR) {
 435             qemu_del_timer(s->fifo_timeout_timer);
 436             s->timeout_ipending=0;
 437             fifo_clear(s,RECV_FIFO);
 438         }
 439
 440         if (val & UART_FCR_XFR) {
 441             fifo_clear(s,XMIT_FIFO);
 442         }
 443
 444         if (val & UART_FCR_FE) {
 445             s->iir |= UART_IIR_FE;
 446             /* Set RECV_FIFO trigger Level */
 447             switch (val & 0xC0) {
 448             case UART_FCR_ITL_1:
 449                 s->recv_fifo.itl = 1;
 450                 break;
 451             case UART_FCR_ITL_2:
 452                 s->recv_fifo.itl = 4;
 453                 break;
 454             case UART_FCR_ITL_3:
 455                 s->recv_fifo.itl = 8;
 456                 break;
 457             case UART_FCR_ITL_4:
 458                 s->recv_fifo.itl = 14;
 459                 break;
 460             }
 461         } else
 462             s->iir &= ~UART_IIR_FE;
 463
 464         /* Set fcr - or at least the bits in it that are supposed to "stick" */
 465         s->fcr = val & 0xC9;
 466         serial_update_irq(s);
 467         break;
 468     case 3:
 469         {
 470             int break_enable;
 471             s->lcr = val;
 472             serial_update_parameters(s);
 473             break_enable = (val >> 6) & 1;
 474             if (break_enable != s->last_break_enable) {
 475                 s->last_break_enable = break_enable;
 476                 qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_BREAK,
 477                                &break_enable);
 478             }
 479         }
 480         break;
 481     case 4:
 482         {
 483             int flags;
 484             int old_mcr = s->mcr;
 485             s->mcr = val & 0x1f;
 486             if (val & UART_MCR_LOOP)
 487                 break;
 488
 489             if (s->poll_msl >= 0 && old_mcr != s->mcr) {
 490
 491                 qemu_chr_fe_ioctl(s->chr,CHR_IOCTL_SERIAL_GET_TIOCM, &flags);
 492
 493                 flags &= ~(CHR_TIOCM_RTS | CHR_TIOCM_DTR);
 494
 495                 if (val & UART_MCR_RTS)
 496                     flags |= CHR_TIOCM_RTS;
 497                 if (val & UART_MCR_DTR)
 498                     flags |= CHR_TIOCM_DTR;
 499
 500                 qemu_chr_fe_ioctl(s->chr,CHR_IOCTL_SERIAL_SET_TIOCM, &flags);
 501                 /* Update the modem status after a one-character-send wait-time, since there may be a response
 502                    from the device/computer at the other end of the serial line */
 503                 qemu_mod_timer(s->modem_status_poll, qemu_get_clock_ns(vm_clock) + s->char_transmit_time);
 504             }
 505         }
 506         break;
 507     case 5:
 508         break;
 509     case 6:
 510         break;
 511     case 7:
 512         s->scr = val;
 513         break;
 514     }
 515 }
 516
 517 static uint32_t serial_ioport_read(void *opaque, uint32_t addr)
 518 {
 519     SerialState *s = opaque;
 520     uint32_t ret;
 521
 522     addr &= 7;
 523     switch(addr) {
 524     default:
 525     case 0:
 526         if (s->lcr & UART_LCR_DLAB) {
 527             ret = s->divider & 0xff;
 528         } else {
 529             if(s->fcr & UART_FCR_FE) {
 530                 ret = fifo_get(s,RECV_FIFO);
 531                 if (s->recv_fifo.count == 0)
 532                     s->lsr &= ~(UART_LSR_DR | UART_LSR_BI);
 533                 else
 534                     qemu_mod_timer(s->fifo_timeout_timer, qemu_get_clock_ns (vm_clock) + s->char_transmit_time * 4);
 535                 s->timeout_ipending = 0;
 536             } else {
 537                 ret = s->rbr;
 538                 s->lsr &= ~(UART_LSR_DR | UART_LSR_BI);
 539             }
 540             serial_update_handlers(s);
 541             serial_update_irq(s);
 542         }
 543         break;
 544     case 1:
 545         if (s->lcr & UART_LCR_DLAB) {
 546             ret = (s->divider >> 8) & 0xff;
 547         } else {
 548             ret = s->ier;
 549         }
 550         break;
 551     case 2:
 552         ret = s->iir;
 553         if ((ret & UART_IIR_ID) == UART_IIR_THRI) {
 554             s->thr_ipending = 0;
 555             serial_update_irq(s);
 556         }
 557         break;
 558     case 3:
 559         ret = s->lcr;
 560         break;
 561     case 4:
 562         ret = s->mcr;
 563         break;
 564     case 5:
 565         ret = s->lsr;
 566         /* Clear break and overrun interrupts */
 567         if (s->lsr & (UART_LSR_BI|UART_LSR_OE)) {
 568             s->lsr &= ~(UART_LSR_BI|UART_LSR_OE);
 569             serial_update_irq(s);
 570         }
 571         break;
 572     case 6:
 573         if (s->mcr & UART_MCR_LOOP) {
 574             /* in loopback, the modem output pins are connected to the
 575                inputs */
 576             ret = (s->mcr & 0x0c) << 4;
 577             ret |= (s->mcr & 0x02) << 3;
 578             ret |= (s->mcr & 0x01) << 5;
 579         } else {
 580             if (s->poll_msl >= 0)
 581                 serial_update_msl(s);
 582             ret = s->msr;
 583             /* Clear delta bits & msr int after read, if they were set */
 584             if (s->msr & UART_MSR_ANY_DELTA) {
 585                 s->msr &= 0xF0;
 586                 serial_update_irq(s);
 587             }
 588         }
 589         break;
 590     case 7:
 591         ret = s->scr;
 592         break;
 593     }
 594     DPRINTF("read addr=0x%02x val=0x%02x\n", addr, ret);
 595     return ret;
 596 }
 597
 598 static int serial_can_receive(SerialState *s)
 599 {
 600     if(s->fcr & UART_FCR_FE) {
 601         if(s->recv_fifo.count < UART_FIFO_LENGTH)
 602         /* Advertise (fifo.itl - fifo.count) bytes when count < ITL, and 1 if above. If UART_FIFO_LENGTH - fifo.count is
 603         advertised the effect will be to almost always fill the fifo completely before the guest has a chance to respond,
 604         effectively overriding the ITL that the guest has set. */
 605              return (s->recv_fifo.count <= s->recv_fifo.itl) ? s->recv_fifo.itl - s->recv_fifo.count : 1;
 606         else
 607              return 0;
 608     } else {
 609         return !(s->lsr & UART_LSR_DR);
 610     }
 611 }
 612
 613 static void serial_receive_break(SerialState *s)
 614 {
 615     s->rbr = 0;
 616     /* When the LSR_DR is set a null byte is pushed into the fifo */
 617     fifo_put(s, RECV_FIFO, '\0');
 618     s->lsr |= UART_LSR_BI | UART_LSR_DR;
 619     serial_update_handlers(s);
 620     serial_update_irq(s);
 621 }
 622
 623 /* There's data in recv_fifo and s->rbr has not been read for 4 char transmit times */
 624 static void fifo_timeout_int (void *opaque) {
 625     SerialState *s = opaque;
 626     if (s->recv_fifo.count) {
 627         s->timeout_ipending = 1;
 628         serial_update_irq(s);
 629     }
 630 }
 631
 632 static void serial_receive1(SerialState *s, const uint8_t *buf, int size)
 633 {
 634     if(s->fcr & UART_FCR_FE) {
 635         int i;
 636         for (i = 0; i < size; i++) {
 637             fifo_put(s, RECV_FIFO, buf[i]);
 638         }
 639         s->lsr |= UART_LSR_DR;
 640         /* call the timeout receive callback in 4 char transmit time */
 641         qemu_mod_timer(s->fifo_timeout_timer, qemu_get_clock_ns (vm_clock) + s->char_transmit_time * 4);
 642     } else {
 643         if (s->lsr & UART_LSR_DR)
 644             s->lsr |= UART_LSR_OE;
 645         s->rbr = buf[0];
 646         s->lsr |= UART_LSR_DR;
 647     }
 648     serial_update_handlers(s);
 649     serial_update_irq(s);
 650 }
 651
 652 static void serial_receive2(void *opaque)
 653 {
 654     SerialState *s = opaque;
 655     uint8_t buf[32];
 656     int max;
 657
 658     max = serial_can_receive(s);
 659     max = MAX(sizeof(buf), max);
 660
 661     max = qemu_chr_fe_read(s->chr, buf, max);
 662
 663     serial_receive1(s, buf, max);
 664 }
 665
 666 static int serial_event(void *opaque, int event, void *data)
 667 {
 668     SerialState *s = opaque;
 669     DPRINTF("event %x\n", event);
 670     if (event == CHR_EVENT_BREAK)
 671         serial_receive_break(s);
 672     return 0;
 673 }
 674
 675 static void serial_update_handlers(SerialState *s)
 676 {
 677     if (serial_can_receive(s) > 0) {
 678         qemu_chr_fe_set_handlers(s->chr, serial_receive2, NULL,
 679                                  serial_event, s);
 680     } else {
 681         qemu_chr_fe_set_handlers(s->chr, NULL, NULL, serial_event, s);
 682     }
 683 }
 684
 685 static void serial_pre_save(void *opaque)
 686 {
 687     SerialState *s = opaque;
 688     s->fcr_vmstate = s->fcr;
 689 }
 690
 691 static int serial_post_load(void *opaque, int version_id)
 692 {
 693     SerialState *s = opaque;
 694
 695     if (version_id < 3) {
 696         s->fcr_vmstate = 0;
 697     }
 698     /* Initialize fcr via setter to perform essential side-effects */
 699     serial_ioport_write(s, 0x02, s->fcr_vmstate);
 700     serial_update_parameters(s);
 701     return 0;
 702 }
 703
 704 static const VMStateDescription vmstate_serial = {
 705     .name = "serial",
 706     .version_id = 3,
 707     .minimum_version_id = 2,
 708     .pre_save = serial_pre_save,
 709     .post_load = serial_post_load,
 710     .fields      = (VMStateField []) {
 711         VMSTATE_UINT16_V(divider, SerialState, 2),
 712         VMSTATE_UINT8(rbr, SerialState),
 713         VMSTATE_UINT8(ier, SerialState),
 714         VMSTATE_UINT8(iir, SerialState),
 715         VMSTATE_UINT8(lcr, SerialState),
 716         VMSTATE_UINT8(mcr, SerialState),
 717         VMSTATE_UINT8(lsr, SerialState),
 718         VMSTATE_UINT8(msr, SerialState),
 719         VMSTATE_UINT8(scr, SerialState),
 720         VMSTATE_UINT8_V(fcr_vmstate, SerialState, 3),
 721         VMSTATE_END_OF_LIST()
 722     }
 723 };
 724
 725 static void serial_reset(void *opaque)
 726 {
 727     SerialState *s = opaque;
 728
 729     s->rbr = 0;
 730     s->ier = 0;
 731     s->iir = UART_IIR_NO_INT;
 732     s->lcr = 0;
 733     s->lsr = UART_LSR_TEMT | UART_LSR_THRE;
 734     s->msr = UART_MSR_DCD | UART_MSR_DSR | UART_MSR_CTS;
 735     /* Default to 9600 baud, 1 start bit, 8 data bits, 1 stop bit, no parity. */
 736     s->divider = 0x0C;
 737     s->mcr = UART_MCR_OUT2;
 738     s->scr = 0;
 739     s->tsr_retry = 0;
 740     s->char_transmit_time = (get_ticks_per_sec() / 9600) * 10;
 741     s->poll_msl = 0;
 742
 743     fifo_clear(s,RECV_FIFO);
 744     fifo_clear(s,XMIT_FIFO);
 745
 746     s->last_xmit_ts = qemu_get_clock_ns(vm_clock);
 747
 748     s->thr_ipending = 0;
 749     s->last_break_enable = 0;
 750     serial_update_handlers(s);
 751     qemu_irq_lower(s->irq);
 752 }
 753
 754 static void serial_init_core(SerialState *s)
 755 {
 756     if (!s->chr) {
 757         fprintf(stderr, "Can't create serial device, empty char device\n");
 758         exit(1);
 759     }
 760
 761     s->modem_status_poll = qemu_new_timer_ns(vm_clock, (QEMUTimerCB *) serial_update_msl, s);
 762
 763     s->fifo_timeout_timer = qemu_new_timer_ns(vm_clock, (QEMUTimerCB *) fifo_timeout_int, s);
 764     s->transmit_timer = qemu_new_timer_ns(vm_clock, (QEMUTimerCB *) serial_xmit, s);
 765
 766     qemu_register_reset(serial_reset, s);
 767
 768     qemu_chr_fe_open(s->chr);
 769
 770     serial_update_handlers(s);
 771 }
 772
 773 /* Change the main reference oscillator frequency. */
 774 void serial_set_frequency(SerialState *s, uint32_t frequency)
 775 {
 776     s->baudbase = frequency;
 777     serial_update_parameters(s);
 778 }
 779
 780 static const int isa_serial_io[MAX_SERIAL_PORTS] = { 0x3f8, 0x2f8, 0x3e8, 0x2e8 };
 781 static const int isa_serial_irq[MAX_SERIAL_PORTS] = { 4, 3, 4, 3 };
 782
 783 static int serial_isa_initfn(ISADevice *dev)
 784 {
 785     static int index;
 786     ISASerialState *isa = DO_UPCAST(ISASerialState, dev, dev);
 787     SerialState *s = &isa->state;
 788
 789     if (isa->index == -1)
 790         isa->index = index;
 791     if (isa->index >= MAX_SERIAL_PORTS)
 792         return -1;
 793     if (isa->iobase == -1)
 794         isa->iobase = isa_serial_io[isa->index];
 795     if (isa->isairq == -1)
 796         isa->isairq = isa_serial_irq[isa->index];
 797     index++;
 798
 799     s->baudbase = 115200;
 800     isa_init_irq(dev, &s->irq, isa->isairq);
 801     serial_init_core(s);
 802     qdev_set_legacy_instance_id(&dev->qdev, isa->iobase, 3);
 803
 804     register_ioport_write(isa->iobase, 8, 1, serial_ioport_write, s);
 805     register_ioport_read(isa->iobase, 8, 1, serial_ioport_read, s);
 806     isa_init_ioport_range(dev, isa->iobase, 8);
 807     return 0;
 808 }
 809
 810 static const VMStateDescription vmstate_isa_serial = {
 811     .name = "serial",
 812     .version_id = 3,
 813     .minimum_version_id = 2,
 814     .fields      = (VMStateField []) {
 815         VMSTATE_STRUCT(state, ISASerialState, 0, vmstate_serial, SerialState),
 816         VMSTATE_END_OF_LIST()
 817     }
 818 };
 819
 820 SerialState *serial_init(int base, qemu_irq irq, int baudbase,
 821                          CharDriverState *chr)
 822 {
 823     SerialState *s;
 824
 825     s = qemu_mallocz(sizeof(SerialState));
 826
 827     s->irq = irq;
 828     s->baudbase = baudbase;
 829     s->chr = chr;
 830     serial_init_core(s);
 831
 832     vmstate_register(NULL, base, &vmstate_serial, s);
 833
 834     register_ioport_write(base, 8, 1, serial_ioport_write, s);
 835     register_ioport_read(base, 8, 1, serial_ioport_read, s);
 836     return s;
 837 }
 838
 839 /* Memory mapped interface */
 840 static uint32_t serial_mm_readb(void *opaque, target_phys_addr_t addr)
 841 {
 842     SerialState *s = opaque;
 843
 844     return serial_ioport_read(s, addr >> s->it_shift) & 0xFF;
 845 }
 846
 847 static void serial_mm_writeb(void *opaque, target_phys_addr_t addr,
 848                              uint32_t value)
 849 {
 850     SerialState *s = opaque;
 851
 852     serial_ioport_write(s, addr >> s->it_shift, value & 0xFF);
 853 }
 854
 855 static uint32_t serial_mm_readw_be(void *opaque, target_phys_addr_t addr)
 856 {
 857     SerialState *s = opaque;
 858     uint32_t val;
 859
 860     val = serial_ioport_read(s, addr >> s->it_shift) & 0xFFFF;
 861     val = bswap16(val);
 862     return val;
 863 }
 864
 865 static uint32_t serial_mm_readw_le(void *opaque, target_phys_addr_t addr)
 866 {
 867     SerialState *s = opaque;
 868     uint32_t val;
 869
 870     val = serial_ioport_read(s, addr >> s->it_shift) & 0xFFFF;
 871     return val;
 872 }
 873
 874 static void serial_mm_writew_be(void *opaque, target_phys_addr_t addr,
 875                                 uint32_t value)
 876 {
 877     SerialState *s = opaque;
 878
 879     value = bswap16(value);
 880     serial_ioport_write(s, addr >> s->it_shift, value & 0xFFFF);
 881 }
 882
 883 static void serial_mm_writew_le(void *opaque, target_phys_addr_t addr,
 884                                 uint32_t value)
 885 {
 886     SerialState *s = opaque;
 887
 888     serial_ioport_write(s, addr >> s->it_shift, value & 0xFFFF);
 889 }
 890
 891 static uint32_t serial_mm_readl_be(void *opaque, target_phys_addr_t addr)
 892 {
 893     SerialState *s = opaque;
 894     uint32_t val;
 895
 896     val = serial_ioport_read(s, addr >> s->it_shift);
 897     val = bswap32(val);
 898     return val;
 899 }
 900
 901 static uint32_t serial_mm_readl_le(void *opaque, target_phys_addr_t addr)
 902 {
 903     SerialState *s = opaque;
 904     uint32_t val;
 905
 906     val = serial_ioport_read(s, addr >> s->it_shift);
 907     return val;
 908 }
 909
 910 static void serial_mm_writel_be(void *opaque, target_phys_addr_t addr,
 911                                 uint32_t value)
 912 {
 913     SerialState *s = opaque;
 914
 915     value = bswap32(value);
 916     serial_ioport_write(s, addr >> s->it_shift, value);
 917 }
 918
 919 static void serial_mm_writel_le(void *opaque, target_phys_addr_t addr,
 920                                 uint32_t value)
 921 {
 922     SerialState *s = opaque;
 923
 924     serial_ioport_write(s, addr >> s->it_shift, value);
 925 }
 926
 927 static CPUReadMemoryFunc * const serial_mm_read_be[] = {
 928     &serial_mm_readb,
 929     &serial_mm_readw_be,
 930     &serial_mm_readl_be,
 931 };
 932
 933 static CPUWriteMemoryFunc * const serial_mm_write_be[] = {
 934     &serial_mm_writeb,
 935     &serial_mm_writew_be,
 936     &serial_mm_writel_be,
 937 };
 938
 939 static CPUReadMemoryFunc * const serial_mm_read_le[] = {
 940     &serial_mm_readb,
 941     &serial_mm_readw_le,
 942     &serial_mm_readl_le,
 943 };
 944
 945 static CPUWriteMemoryFunc * const serial_mm_write_le[] = {
 946     &serial_mm_writeb,
 947     &serial_mm_writew_le,
 948     &serial_mm_writel_le,
 949 };
 950
 951 SerialState *serial_mm_init (target_phys_addr_t base, int it_shift,
 952                              qemu_irq irq, int baudbase,
 953                              CharDriverState *chr, int ioregister,
 954                              int be)
 955 {
 956     SerialState *s;
 957     int s_io_memory;
 958
 959     s = qemu_mallocz(sizeof(SerialState));
 960
 961     s->it_shift = it_shift;
 962     s->irq = irq;
 963     s->baudbase = baudbase;
 964     s->chr = chr;
 965
 966     serial_init_core(s);
 967     vmstate_register(NULL, base, &vmstate_serial, s);
 968
 969     if (ioregister) {
 970         if (be) {
 971             s_io_memory = cpu_register_io_memory(serial_mm_read_be,
 972                                                  serial_mm_write_be, s,
 973                                                  DEVICE_NATIVE_ENDIAN);
 974         } else {
 975             s_io_memory = cpu_register_io_memory(serial_mm_read_le,
 976                                                  serial_mm_write_le, s,
 977                                                  DEVICE_NATIVE_ENDIAN);
 978         }
 979         cpu_register_physical_memory(base, 8 << it_shift, s_io_memory);
 980     }
 981     serial_update_msl(s);
 982     return s;
 983 }
 984
 985 static ISADeviceInfo serial_isa_info = {
 986     .qdev.name  = "isa-serial",
 987     .qdev.size  = sizeof(ISASerialState),
 988     .qdev.vmsd  = &vmstate_isa_serial,
 989     .init       = serial_isa_initfn,
 990     .qdev.props = (Property[]) {
 991         DEFINE_PROP_UINT32("index", ISASerialState, index,   -1),
 992         DEFINE_PROP_HEX32("iobase", ISASerialState, iobase,  -1),
 993         DEFINE_PROP_UINT32("irq",   ISASerialState, isairq,  -1),
 994         DEFINE_PROP_CHR("chardev",  ISASerialState, state.chr),
 995         DEFINE_PROP_END_OF_LIST(),
 996     },
 997 };
 998
 999 static void serial_register_devices(void)
1000 {
1001     isa_qdev_register(&serial_isa_info);
1002 }
1003
1004 device_init(serial_register_devices)