hw/sh_serial.c

   1 /*
   2  * QEMU SCI/SCIF serial port emulation
   3  *
   4  * Copyright (c) 2007 Magnus Damm
   5  *
   6  * Based on serial.c - QEMU 16450 UART emulation
   7  * Copyright (c) 2003-2004 Fabrice Bellard
   8  *
   9  * Permission is hereby granted, free of charge, to any person obtaining a copy
  10  * of this software and associated documentation files (the "Software"), to deal
  11  * in the Software without restriction, including without limitation the rights
  12  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  13  * copies of the Software, and to permit persons to whom the Software is
  14  * furnished to do so, subject to the following conditions:
  15  *
  16  * The above copyright notice and this permission notice shall be included in
  17  * all copies or substantial portions of the Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  20  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  21  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  22  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  23  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  24  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  25  * THE SOFTWARE.
  26  */
  27 #include "hw.h"
  28 #include "sh.h"
  29 #include "qemu-char.h"
  30
  31 //#define DEBUG_SERIAL
  32
  33 #define SH_SERIAL_FLAG_TEND (1 << 0)
  34 #define SH_SERIAL_FLAG_TDE  (1 << 1)
  35 #define SH_SERIAL_FLAG_RDF  (1 << 2)
  36 #define SH_SERIAL_FLAG_BRK  (1 << 3)
  37 #define SH_SERIAL_FLAG_DR   (1 << 4)
  38
  39 #define SH_RX_FIFO_LENGTH (16)
  40
  41 typedef struct {
  42     uint8_t smr;
  43     uint8_t brr;
  44     uint8_t scr;
  45     uint8_t dr; /* ftdr / tdr */
  46     uint8_t sr; /* fsr / ssr */
  47     uint16_t fcr;
  48     uint8_t sptr;
  49
  50     uint8_t rx_fifo[SH_RX_FIFO_LENGTH]; /* frdr / rdr */
  51     uint8_t rx_cnt;
  52     uint8_t rx_tail;
  53     uint8_t rx_head;
  54
  55     int freq;
  56     int feat;
  57     int flags;
  58     int rtrg;
  59
  60     CharDriverState *chr;
  61
  62     qemu_irq eri;
  63     qemu_irq rxi;
  64     qemu_irq txi;
  65     qemu_irq tei;
  66     qemu_irq bri;
  67 } sh_serial_state;
  68
  69 static void sh_serial_update_handlers(sh_serial_state *s);
  70
  71 static void sh_serial_clear_fifo(sh_serial_state * s)
  72 {
  73     memset(s->rx_fifo, 0, SH_RX_FIFO_LENGTH);
  74     s->rx_cnt = 0;
  75     s->rx_head = 0;
  76     s->rx_tail = 0;
  77 }
  78
  79 static void sh_serial_write(void *opaque, uint32_t offs, uint32_t val)
  80 {
  81     sh_serial_state *s = opaque;
  82     unsigned char ch;
  83
  84 #ifdef DEBUG_SERIAL
  85     printf("sh_serial: write offs=0x%02x val=0x%02x\n",
  86            offs, val);
  87 #endif
  88     switch(offs) {
  89     case 0x00: /* SMR */
  90         s->smr = val & ((s->feat & SH_SERIAL_FEAT_SCIF) ? 0x7b : 0xff);
  91         return;
  92     case 0x04: /* BRR */
  93         s->brr = val;
  94         return;
  95     case 0x08: /* SCR */
  96         /* TODO : For SH7751, SCIF mask should be 0xfb. */
  97         s->scr = val & ((s->feat & SH_SERIAL_FEAT_SCIF) ? 0xfa : 0xff);
  98         sh_serial_update_handlers(s);
  99         if (!(val & (1 << 5)))
 100             s->flags |= SH_SERIAL_FLAG_TEND;
 101         if ((s->feat & SH_SERIAL_FEAT_SCIF) && s->txi) {
 102             qemu_set_irq(s->txi, val & (1 << 7));
 103         }
 104         if (!(val & (1 << 6))) {
 105             qemu_set_irq(s->rxi, 0);
 106         }
 107         return;
 108     case 0x0c: /* FTDR / TDR */
 109         if (s->chr) {
 110             ch = val;
 111             qemu_chr_fe_write(s->chr, &ch, 1);
 112         }
 113         s->dr = val;
 114         s->flags &= ~SH_SERIAL_FLAG_TDE;
 115         return;
 116 #if 0
 117     case 0x14: /* FRDR / RDR */
 118         ret = 0;
 119         break;
 120 #endif
 121     }
 122     if (s->feat & SH_SERIAL_FEAT_SCIF) {
 123         switch(offs) {
 124         case 0x10: /* FSR */
 125             if (!(val & (1 << 6)))
 126                 s->flags &= ~SH_SERIAL_FLAG_TEND;
 127             if (!(val & (1 << 5)))
 128                 s->flags &= ~SH_SERIAL_FLAG_TDE;
 129             if (!(val & (1 << 4)))
 130                 s->flags &= ~SH_SERIAL_FLAG_BRK;
 131             if (!(val & (1 << 1)))
 132                 s->flags &= ~SH_SERIAL_FLAG_RDF;
 133             if (!(val & (1 << 0)))
 134                 s->flags &= ~SH_SERIAL_FLAG_DR;
 135
 136             if (!(val & (1 << 1)) || !(val & (1 << 0))) {
 137                 if (s->rxi) {
 138                     qemu_set_irq(s->rxi, 0);
 139                 }
 140             }
 141             return;
 142         case 0x18: /* FCR */
 143             s->fcr = val;
 144             switch ((val >> 6) & 3) {
 145             case 0:
 146                 s->rtrg = 1;
 147                 break;
 148             case 1:
 149                 s->rtrg = 4;
 150                 break;
 151             case 2:
 152                 s->rtrg = 8;
 153                 break;
 154             case 3:
 155                 s->rtrg = 14;
 156                 break;
 157             }
 158             if (val & (1 << 1)) {
 159                 sh_serial_clear_fifo(s);
 160                 s->sr &= ~(1 << 1);
 161             }
 162
 163             return;
 164         case 0x20: /* SPTR */
 165             s->sptr = val & 0xf3;
 166             return;
 167         case 0x24: /* LSR */
 168             return;
 169         }
 170     }
 171     else {
 172         switch(offs) {
 173 #if 0
 174         case 0x0c:
 175             ret = s->dr;
 176             break;
 177         case 0x10:
 178             ret = 0;
 179             break;
 180 #endif
 181         case 0x1c:
 182             s->sptr = val & 0x8f;
 183             return;
 184         }
 185     }
 186
 187     fprintf(stderr, "sh_serial: unsupported write to 0x%02x\n", offs);
 188     abort();
 189 }
 190
 191 static uint32_t sh_serial_read(void *opaque, uint32_t offs)
 192 {
 193     sh_serial_state *s = opaque;
 194     uint32_t ret = ~0;
 195
 196 #if 0
 197     switch(offs) {
 198     case 0x00:
 199         ret = s->smr;
 200         break;
 201     case 0x04:
 202         ret = s->brr;
 203         break;
 204     case 0x08:
 205         ret = s->scr;
 206         break;
 207     case 0x14:
 208         ret = 0;
 209         break;
 210     }
 211 #endif
 212     if (s->feat & SH_SERIAL_FEAT_SCIF) {
 213         switch(offs) {
 214         case 0x00: /* SMR */
 215             ret = s->smr;
 216             break;
 217         case 0x08: /* SCR */
 218             ret = s->scr;
 219             break;
 220         case 0x10: /* FSR */
 221             ret = 0;
 222             if (s->flags & SH_SERIAL_FLAG_TEND)
 223                 ret |= (1 << 6);
 224             if (s->flags & SH_SERIAL_FLAG_TDE)
 225                 ret |= (1 << 5);
 226             if (s->flags & SH_SERIAL_FLAG_BRK)
 227                 ret |= (1 << 4);
 228             if (s->flags & SH_SERIAL_FLAG_RDF)
 229                 ret |= (1 << 1);
 230             if (s->flags & SH_SERIAL_FLAG_DR)
 231                 ret |= (1 << 0);
 232
 233             if (s->scr & (1 << 5))
 234                 s->flags |= SH_SERIAL_FLAG_TDE | SH_SERIAL_FLAG_TEND;
 235
 236             break;
 237         case 0x14:
 238             if (s->rx_cnt > 0) {
 239                 ret = s->rx_fifo[s->rx_tail++];
 240                 s->rx_cnt--;
 241                 if (s->rx_tail == SH_RX_FIFO_LENGTH)
 242                     s->rx_tail = 0;
 243                 if (s->rx_cnt < s->rtrg)
 244                     s->flags &= ~SH_SERIAL_FLAG_RDF;
 245             }
 246             break;
 247 #if 0
 248         case 0x18:
 249             ret = s->fcr;
 250             break;
 251 #endif
 252         case 0x1c:
 253             ret = s->rx_cnt;
 254             break;
 255         case 0x20:
 256             ret = s->sptr;
 257             break;
 258         case 0x24:
 259             ret = 0;
 260             break;
 261         }
 262     }
 263     else {
 264         switch(offs) {
 265 #if 0
 266         case 0x0c:
 267             ret = s->dr;
 268             break;
 269         case 0x10:
 270             ret = 0;
 271             break;
 272         case 0x14:
 273             ret = s->rx_fifo[0];
 274             break;
 275 #endif
 276         case 0x1c:
 277             ret = s->sptr;
 278             break;
 279         }
 280     }
 281 #ifdef DEBUG_SERIAL
 282     printf("sh_serial: read offs=0x%02x val=0x%x\n",
 283            offs, ret);
 284 #endif
 285
 286     if (ret & ~((1 << 16) - 1)) {
 287         fprintf(stderr, "sh_serial: unsupported read from 0x%02x\n", offs);
 288         abort();
 289     }
 290
 291     return ret;
 292 }
 293
 294 static int sh_serial_can_receive(sh_serial_state *s)
 295 {
 296     return s->scr & (1 << 4);
 297 }
 298
 299 static void sh_serial_receive_break(sh_serial_state *s)
 300 {
 301     if (s->feat & SH_SERIAL_FEAT_SCIF)
 302         s->sr |= (1 << 4);
 303 }
 304
 305 static void sh_serial_receive1(sh_serial_state *s, const uint8_t *buf, int size)
 306 {
 307     if (s->feat & SH_SERIAL_FEAT_SCIF) {
 308         int i;
 309         for (i = 0; i < size; i++) {
 310             if (s->rx_cnt < SH_RX_FIFO_LENGTH) {
 311                 s->rx_fifo[s->rx_head++] = buf[i];
 312                 if (s->rx_head == SH_RX_FIFO_LENGTH) {
 313                     s->rx_head = 0;
 314                 }
 315                 s->rx_cnt++;
 316                 if (s->rx_cnt >= s->rtrg) {
 317                     s->flags |= SH_SERIAL_FLAG_RDF;
 318                     if (s->scr & (1 << 6) && s->rxi) {
 319                         qemu_set_irq(s->rxi, 1);
 320                     }
 321                 }
 322             }
 323         }
 324     } else {
 325         s->rx_fifo[0] = buf[0];
 326     }
 327 }
 328
 329 static void sh_serial_receive_handler(void *opaque)
 330 {
 331     sh_serial_state *s = opaque;
 332     uint8_t buf[32];
 333     int size;
 334
 335     size = sh_serial_can_receive(s);
 336     size = MIN(size, sizeof(buf));
 337     size = qemu_chr_fe_read(s->chr, buf, size);
 338
 339     sh_serial_receive1(s, buf, size);
 340 }
 341
 342 static void sh_serial_event(void *opaque, int event)
 343 {
 344     sh_serial_state *s = opaque;
 345     if (event == CHR_EVENT_BREAK)
 346         sh_serial_receive_break(s);
 347 }
 348
 349 static CPUReadMemoryFunc * const sh_serial_readfn[] = {
 350     &sh_serial_read,
 351     &sh_serial_read,
 352     &sh_serial_read,
 353 };
 354
 355 static CPUWriteMemoryFunc * const sh_serial_writefn[] = {
 356     &sh_serial_write,
 357     &sh_serial_write,
 358     &sh_serial_write,
 359 };
 360
 361 static void sh_serial_update_handlers(sh_serial_state *s)
 362 {
 363     if (sh_serial_can_receive(s) > 0) {
 364         qemu_chr_fe_set_handlers(s->chr, sh_serial_receive_handler,
 365                                  NULL, sh_serial_event, s);
 366     } else {
 367         qemu_chr_fe_set_handlers(s->chr, NULL, NULL, sh_serial_event, s);
 368     }
 369 }
 370
 371 void sh_serial_init (target_phys_addr_t base, int feat,
 372                      uint32_t freq, CharDriverState *chr,
 373                      qemu_irq eri_source,
 374                      qemu_irq rxi_source,
 375                      qemu_irq txi_source,
 376                      qemu_irq tei_source,
 377                      qemu_irq bri_source)
 378 {
 379     sh_serial_state *s;
 380     int s_io_memory;
 381
 382     s = qemu_mallocz(sizeof(sh_serial_state));
 383
 384     s->feat = feat;
 385     s->flags = SH_SERIAL_FLAG_TEND | SH_SERIAL_FLAG_TDE;
 386     s->rtrg = 1;
 387
 388     s->smr = 0;
 389     s->brr = 0xff;
 390     s->scr = 1 << 5; /* pretend that TX is enabled so early printk works */
 391     s->sptr = 0;
 392
 393     if (feat & SH_SERIAL_FEAT_SCIF) {
 394         s->fcr = 0;
 395     }
 396     else {
 397         s->dr = 0xff;
 398     }
 399
 400     sh_serial_clear_fifo(s);
 401
 402     s_io_memory = cpu_register_io_memory(sh_serial_readfn,
 403                                          sh_serial_writefn, s,
 404                                          DEVICE_NATIVE_ENDIAN);
 405     cpu_register_physical_memory(P4ADDR(base), 0x28, s_io_memory);
 406     cpu_register_physical_memory(A7ADDR(base), 0x28, s_io_memory);
 407
 408     s->chr = chr;
 409
 410     if (chr) {
 411         qemu_chr_fe_open(chr);
 412         sh_serial_update_handlers(s);
 413     }
 414
 415     s->eri = eri_source;
 416     s->rxi = rxi_source;
 417     s->txi = txi_source;
 418     s->tei = tei_source;
 419     s->bri = bri_source;
 420 }