hw/syborg_serial.c

   1 /*
   2  * Syborg serial port
   3  *
   4  * Copyright (c) 2008 CodeSourcery
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #include "sysbus.h"
  26 #include "qemu-char.h"
  27 #include "syborg.h"
  28
  29 //#define DEBUG_SYBORG_SERIAL
  30
  31 #ifdef DEBUG_SYBORG_SERIAL
  32 #define DPRINTF(fmt, ...) \
  33 do { printf("syborg_serial: " fmt , ##args); } while (0)
  34 #define BADF(fmt, ...) \
  35 do { fprintf(stderr, "syborg_serial: error: " fmt , ## __VA_ARGS__); \
  36     exit(1);} while (0)
  37 #else
  38 #define DPRINTF(fmt, ...) do {} while(0)
  39 #define BADF(fmt, ...) \
  40 do { fprintf(stderr, "syborg_serial: error: " fmt , ## __VA_ARGS__);} while (0)
  41 #endif
  42
  43 enum {
  44     SERIAL_ID           = 0,
  45     SERIAL_DATA         = 1,
  46     SERIAL_FIFO_COUNT   = 2,
  47     SERIAL_INT_ENABLE   = 3,
  48     SERIAL_DMA_TX_ADDR  = 4,
  49     SERIAL_DMA_TX_COUNT = 5, /* triggers dma */
  50     SERIAL_DMA_RX_ADDR  = 6,
  51     SERIAL_DMA_RX_COUNT = 7, /* triggers dma */
  52     SERIAL_FIFO_SIZE    = 8
  53 };
  54
  55 #define SERIAL_INT_FIFO   (1u << 0)
  56 #define SERIAL_INT_DMA_TX (1u << 1)
  57 #define SERIAL_INT_DMA_RX (1u << 2)
  58
  59 typedef struct {
  60     SysBusDevice busdev;
  61     uint32_t int_enable;
  62     uint32_t fifo_size;
  63     uint32_t *read_fifo;
  64     int read_pos;
  65     int read_count;
  66     CharDriverState *chr;
  67     qemu_irq irq;
  68     uint32_t dma_tx_ptr;
  69     uint32_t dma_rx_ptr;
  70     uint32_t dma_rx_size;
  71 } SyborgSerialState;
  72
  73 static void syborg_serial_update_handlers(SyborgSerialState *s);
  74
  75 static void syborg_serial_update(SyborgSerialState *s)
  76 {
  77     int level;
  78     level = 0;
  79     if ((s->int_enable & SERIAL_INT_FIFO) && s->read_count)
  80         level = 1;
  81     if (s->int_enable & SERIAL_INT_DMA_TX)
  82         level = 1;
  83     if ((s->int_enable & SERIAL_INT_DMA_RX) && s->dma_rx_size == 0)
  84         level = 1;
  85
  86     qemu_set_irq(s->irq, level);
  87 }
  88
  89 static uint32_t fifo_pop(SyborgSerialState *s)
  90 {
  91     const uint32_t c = s->read_fifo[s->read_pos];
  92     s->read_count--;
  93     s->read_pos++;
  94     if (s->read_pos == s->fifo_size)
  95         s->read_pos = 0;
  96
  97     DPRINTF("FIFO pop %x (%d)\n", c, s->read_count);
  98     return c;
  99 }
 100
 101 static void fifo_push(SyborgSerialState *s, uint32_t new_value)
 102 {
 103     int slot;
 104
 105     DPRINTF("FIFO push %x (%d)\n", new_value, s->read_count);
 106     slot = s->read_pos + s->read_count;
 107     if (slot >= s->fifo_size)
 108           slot -= s->fifo_size;
 109     s->read_fifo[slot] = new_value;
 110     s->read_count++;
 111 }
 112
 113 static void do_dma_tx(SyborgSerialState *s, uint32_t count)
 114 {
 115     unsigned char ch;
 116
 117     if (count == 0)
 118         return;
 119
 120     if (s->chr != NULL) {
 121         /* optimize later. Now, 1 byte per iteration */
 122         while (count--) {
 123             cpu_physical_memory_read(s->dma_tx_ptr, &ch, 1);
 124             qemu_chr_fe_write(s->chr, &ch, 1);
 125             s->dma_tx_ptr++;
 126         }
 127     } else {
 128         s->dma_tx_ptr += count;
 129     }
 130     /* QEMU char backends do not have a nonblocking mode, so we transmit all
 131        the data immediately and the interrupt status will be unchanged.  */
 132 }
 133
 134 /* Initiate RX DMA, and transfer data from the FIFO.  */
 135 static void dma_rx_start(SyborgSerialState *s, uint32_t len)
 136 {
 137     uint32_t dest;
 138     unsigned char ch;
 139
 140     dest = s->dma_rx_ptr;
 141     if (s->read_count < len) {
 142         s->dma_rx_size = len - s->read_count;
 143         len = s->read_count;
 144     } else {
 145         s->dma_rx_size = 0;
 146     }
 147     syborg_serial_update_handlers(s);
 148
 149     while (len--) {
 150         ch = fifo_pop(s);
 151         cpu_physical_memory_write(dest, &ch, 1);
 152         dest++;
 153     }
 154     s->dma_rx_ptr = dest;
 155     syborg_serial_update(s);
 156 }
 157
 158 static uint32_t syborg_serial_read(void *opaque, target_phys_addr_t offset)
 159 {
 160     SyborgSerialState *s = (SyborgSerialState *)opaque;
 161     uint32_t c;
 162
 163     offset &= 0xfff;
 164     DPRINTF("read 0x%x\n", (int)offset);
 165     switch(offset >> 2) {
 166     case SERIAL_ID:
 167         return SYBORG_ID_SERIAL;
 168     case SERIAL_DATA:
 169         if (s->read_count > 0)
 170             c = fifo_pop(s);
 171         else
 172             c = -1;
 173         syborg_serial_update(s);
 174         return c;
 175     case SERIAL_FIFO_COUNT:
 176         return s->read_count;
 177     case SERIAL_INT_ENABLE:
 178         return s->int_enable;
 179     case SERIAL_DMA_TX_ADDR:
 180         return s->dma_tx_ptr;
 181     case SERIAL_DMA_TX_COUNT:
 182         return 0;
 183     case SERIAL_DMA_RX_ADDR:
 184         return s->dma_rx_ptr;
 185     case SERIAL_DMA_RX_COUNT:
 186         return s->dma_rx_size;
 187     case SERIAL_FIFO_SIZE:
 188         return s->fifo_size;
 189
 190     default:
 191         cpu_abort(cpu_single_env, "syborg_serial_read: Bad offset %x\n",
 192                   (int)offset);
 193         return 0;
 194     }
 195 }
 196
 197 static void syborg_serial_write(void *opaque, target_phys_addr_t offset,
 198                                 uint32_t value)
 199 {
 200     SyborgSerialState *s = (SyborgSerialState *)opaque;
 201     unsigned char ch;
 202
 203     offset &= 0xfff;
 204     DPRINTF("Write 0x%x=0x%x\n", (int)offset, value);
 205     switch (offset >> 2) {
 206     case SERIAL_DATA:
 207         ch = value;
 208         if (s->chr)
 209             qemu_chr_fe_write(s->chr, &ch, 1);
 210         break;
 211     case SERIAL_INT_ENABLE:
 212         s->int_enable = value;
 213         syborg_serial_update(s);
 214         break;
 215     case SERIAL_DMA_TX_ADDR:
 216         s->dma_tx_ptr = value;
 217         break;
 218     case SERIAL_DMA_TX_COUNT:
 219         do_dma_tx(s, value);
 220         break;
 221     case SERIAL_DMA_RX_ADDR:
 222         /* For safety, writes to this register cancel any pending DMA.  */
 223         s->dma_rx_size = 0;
 224         s->dma_rx_ptr = value;
 225         syborg_serial_update_handlers(s);
 226         break;
 227     case SERIAL_DMA_RX_COUNT:
 228         dma_rx_start(s, value);
 229         break;
 230     default:
 231         cpu_abort(cpu_single_env, "syborg_serial_write: Bad offset %x\n",
 232                   (int)offset);
 233         break;
 234     }
 235 }
 236
 237 static int syborg_serial_can_receive(SyborgSerialState *s)
 238 {
 239     if (s->dma_rx_size)
 240         return s->dma_rx_size;
 241     return s->fifo_size - s->read_count;
 242 }
 243
 244 static void syborg_serial_receive(SyborgSerialState *s, const uint8_t *buf, int size)
 245 {
 246     if (s->dma_rx_size) {
 247         /* Place it in the DMA buffer.  */
 248         cpu_physical_memory_write(s->dma_rx_ptr, buf, size);
 249         s->dma_rx_size -= size;
 250         s->dma_rx_ptr += size;
 251     } else {
 252         while (size--)
 253             fifo_push(s, *buf);
 254     }
 255
 256     syborg_serial_update_handlers(s);
 257     syborg_serial_update(s);
 258 }
 259
 260 static void syborg_serial_receive_handler(void *opaque)
 261 {
 262     SyborgSerialState *s = opaque;
 263     uint8_t buf[32];
 264     int size;
 265
 266     size = syborg_serial_can_receive(s);
 267     size = MIN(size, sizeof(buf));
 268     size = qemu_chr_fe_read(s->chr, buf, size);
 269
 270     syborg_serial_receive(s, buf, size);
 271 }
 272
 273 static CPUReadMemoryFunc * const syborg_serial_readfn[] = {
 274      syborg_serial_read,
 275      syborg_serial_read,
 276      syborg_serial_read
 277 };
 278
 279 static CPUWriteMemoryFunc * const syborg_serial_writefn[] = {
 280      syborg_serial_write,
 281      syborg_serial_write,
 282      syborg_serial_write
 283 };
 284
 285 static const VMStateDescription vmstate_syborg_serial = {
 286     .name = "syborg_serial",
 287     .version_id = 1,
 288     .minimum_version_id = 1,
 289     .minimum_version_id_old = 1,
 290     .fields      = (VMStateField[]) {
 291         VMSTATE_UINT32_EQUAL(fifo_size, SyborgSerialState),
 292         VMSTATE_UINT32(int_enable, SyborgSerialState),
 293         VMSTATE_INT32(read_pos, SyborgSerialState),
 294         VMSTATE_INT32(read_count, SyborgSerialState),
 295         VMSTATE_UINT32(dma_tx_ptr, SyborgSerialState),
 296         VMSTATE_UINT32(dma_rx_ptr, SyborgSerialState),
 297         VMSTATE_UINT32(dma_rx_size, SyborgSerialState),
 298         VMSTATE_VARRAY_UINT32(read_fifo, SyborgSerialState, fifo_size, 1,
 299                               vmstate_info_uint32, uint32),
 300         VMSTATE_END_OF_LIST()
 301     }
 302 };
 303
 304 static void syborg_serial_update_handlers(SyborgSerialState *s)
 305 {
 306     if (syborg_serial_can_receive(s)) {
 307         qemu_chr_fe_set_handlers(s->chr, syborg_serial_receive_handler,
 308                                  NULL, NULL, s);
 309     } else {
 310         qemu_chr_fe_set_handlers(s->chr, NULL, NULL, NULL, s);
 311     }
 312 }
 313
 314 static int syborg_serial_init(SysBusDevice *dev)
 315 {
 316     SyborgSerialState *s = FROM_SYSBUS(SyborgSerialState, dev);
 317     int iomemtype;
 318
 319     sysbus_init_irq(dev, &s->irq);
 320     iomemtype = cpu_register_io_memory(syborg_serial_readfn,
 321                                        syborg_serial_writefn, s,
 322                                        DEVICE_NATIVE_ENDIAN);
 323     sysbus_init_mmio(dev, 0x1000, iomemtype);
 324     s->chr = qdev_init_chardev(&dev->qdev);
 325     if (s->chr) {
 326         qemu_chr_fe_open(s->chr);
 327         syborg_serial_update_handlers(s);
 328     }
 329     if (s->fifo_size <= 0) {
 330         fprintf(stderr, "syborg_serial: fifo too small\n");
 331         s->fifo_size = 16;
 332     }
 333     s->read_fifo = qemu_mallocz(s->fifo_size * sizeof(s->read_fifo[0]));
 334
 335     return 0;
 336 }
 337
 338 static SysBusDeviceInfo syborg_serial_info = {
 339     .init = syborg_serial_init,
 340     .qdev.name  = "syborg,serial",
 341     .qdev.size  = sizeof(SyborgSerialState),
 342     .qdev.vmsd  = &vmstate_syborg_serial,
 343     .qdev.props = (Property[]) {
 344         DEFINE_PROP_UINT32("fifo-size", SyborgSerialState, fifo_size, 16),
 345         DEFINE_PROP_END_OF_LIST(),
 346     }
 347 };
 348
 349 static void syborg_serial_register_devices(void)
 350 {
 351     sysbus_register_withprop(&syborg_serial_info);
 352 }
 353
 354 device_init(syborg_serial_register_devices)