hw/versatile_pci.c

   1 /*
   2  * ARM Versatile/PB PCI host controller
   3  *
   4  * Copyright (c) 2006-2009 CodeSourcery.
   5  * Written by Paul Brook
   6  *
   7  * This code is licensed under the LGPL.
   8  */
   9
  10 #include "sysbus.h"
  11 #include "pci.h"
  12 #include "pci_host.h"
  13 #include "exec-memory.h"
  14
  15 typedef struct {
  16     SysBusDevice busdev;
  17     qemu_irq irq[4];
  18     int realview;
  19     int mem_config;
  20 } PCIVPBState;
  21
  22 static inline uint32_t vpb_pci_config_addr(target_phys_addr_t addr)
  23 {
  24     return addr & 0xffffff;
  25 }
  26
  27 static void pci_vpb_config_writeb (void *opaque, target_phys_addr_t addr,
  28                                    uint32_t val)
  29 {
  30     pci_data_write(opaque, vpb_pci_config_addr (addr), val, 1);
  31 }
  32
  33 static void pci_vpb_config_writew (void *opaque, target_phys_addr_t addr,
  34                                    uint32_t val)
  35 {
  36     pci_data_write(opaque, vpb_pci_config_addr (addr), val, 2);
  37 }
  38
  39 static void pci_vpb_config_writel (void *opaque, target_phys_addr_t addr,
  40                                    uint32_t val)
  41 {
  42     pci_data_write(opaque, vpb_pci_config_addr (addr), val, 4);
  43 }
  44
  45 static uint32_t pci_vpb_config_readb (void *opaque, target_phys_addr_t addr)
  46 {
  47     uint32_t val;
  48     val = pci_data_read(opaque, vpb_pci_config_addr (addr), 1);
  49     return val;
  50 }
  51
  52 static uint32_t pci_vpb_config_readw (void *opaque, target_phys_addr_t addr)
  53 {
  54     uint32_t val;
  55     val = pci_data_read(opaque, vpb_pci_config_addr (addr), 2);
  56     return val;
  57 }
  58
  59 static uint32_t pci_vpb_config_readl (void *opaque, target_phys_addr_t addr)
  60 {
  61     uint32_t val;
  62     val = pci_data_read(opaque, vpb_pci_config_addr (addr), 4);
  63     return val;
  64 }
  65
  66 static CPUWriteMemoryFunc * const pci_vpb_config_write[] = {
  67     &pci_vpb_config_writeb,
  68     &pci_vpb_config_writew,
  69     &pci_vpb_config_writel,
  70 };
  71
  72 static CPUReadMemoryFunc * const pci_vpb_config_read[] = {
  73     &pci_vpb_config_readb,
  74     &pci_vpb_config_readw,
  75     &pci_vpb_config_readl,
  76 };
  77
  78 static int pci_vpb_map_irq(PCIDevice *d, int irq_num)
  79 {
  80     return irq_num;
  81 }
  82
  83 static void pci_vpb_set_irq(void *opaque, int irq_num, int level)
  84 {
  85     qemu_irq *pic = opaque;
  86
  87     qemu_set_irq(pic[irq_num], level);
  88 }
  89
  90 static void pci_vpb_map(SysBusDevice *dev, target_phys_addr_t base)
  91 {
  92     PCIVPBState *s = (PCIVPBState *)dev;
  93     /* Selfconfig area.  */
  94     cpu_register_physical_memory(base + 0x01000000, 0x1000000, s->mem_config);
  95     /* Normal config area.  */
  96     cpu_register_physical_memory(base + 0x02000000, 0x1000000, s->mem_config);
  97
  98     if (s->realview) {
  99         /* IO memory area.  */
 100         isa_mmio_init(base + 0x03000000, 0x00100000);
 101     }
 102 }
 103
 104 static int pci_vpb_init(SysBusDevice *dev)
 105 {
 106     PCIVPBState *s = FROM_SYSBUS(PCIVPBState, dev);
 107     PCIBus *bus;
 108     int i;
 109
 110     for (i = 0; i < 4; i++) {
 111         sysbus_init_irq(dev, &s->irq[i]);
 112     }
 113     bus = pci_register_bus(&dev->qdev, "pci",
 114                            pci_vpb_set_irq, pci_vpb_map_irq, s->irq,
 115                            get_system_memory(), get_system_io(),
 116                            PCI_DEVFN(11, 0), 4);
 117
 118     /* ??? Register memory space.  */
 119
 120     s->mem_config = cpu_register_io_memory(pci_vpb_config_read,
 121                                            pci_vpb_config_write, bus,
 122                                            DEVICE_LITTLE_ENDIAN);
 123     sysbus_init_mmio_cb(dev, 0x04000000, pci_vpb_map);
 124
 125     pci_create_simple(bus, -1, "versatile_pci_host");
 126     return 0;
 127 }
 128
 129 static int pci_realview_init(SysBusDevice *dev)
 130 {
 131     PCIVPBState *s = FROM_SYSBUS(PCIVPBState, dev);
 132     s->realview = 1;
 133     return pci_vpb_init(dev);
 134 }
 135
 136 static int versatile_pci_host_init(PCIDevice *d)
 137 {
 138     pci_set_word(d->config + PCI_STATUS,
 139                  PCI_STATUS_66MHZ | PCI_STATUS_DEVSEL_MEDIUM);
 140     pci_set_byte(d->config + PCI_LATENCY_TIMER, 0x10);
 141     return 0;
 142 }
 143
 144 static PCIDeviceInfo versatile_pci_host_info = {
 145     .qdev.name = "versatile_pci_host",
 146     .qdev.size = sizeof(PCIDevice),
 147     .init      = versatile_pci_host_init,
 148     .vendor_id = PCI_VENDOR_ID_XILINX,
 149     /* Both boards have the same device ID.  Oh well.  */
 150     .device_id = PCI_DEVICE_ID_XILINX_XC2VP30,
 151     .class_id  = PCI_CLASS_PROCESSOR_CO,
 152 };
 153
 154 static void versatile_pci_register_devices(void)
 155 {
 156     sysbus_register_dev("versatile_pci", sizeof(PCIVPBState), pci_vpb_init);
 157     sysbus_register_dev("realview_pci", sizeof(PCIVPBState),
 158                         pci_realview_init);
 159     pci_qdev_register(&versatile_pci_host_info);
 160 }
 161
 162 device_init(versatile_pci_register_devices)