cpu-common.h

   1 #ifndef CPU_COMMON_H
   2 #define CPU_COMMON_H 1
   3
   4 /* CPU interfaces that are target indpendent.  */
   5
   6 #ifdef TARGET_PHYS_ADDR_BITS
   7 #include "targphys.h"
   8 #endif
   9
  10 #ifndef NEED_CPU_H
  11 #include "poison.h"
  12 #endif
  13
  14 #include "bswap.h"
  15 #include "qemu-queue.h"
  16
  17 #if !defined(CONFIG_USER_ONLY)
  18
  19 enum device_endian {
  20     DEVICE_NATIVE_ENDIAN,
  21     DEVICE_BIG_ENDIAN,
  22     DEVICE_LITTLE_ENDIAN,
  23 };
  24
  25 /* address in the RAM (different from a physical address) */
  26 typedef unsigned long ram_addr_t;
  27
  28 /* memory API */
  29
  30 typedef void CPUWriteMemoryFunc(void *opaque, target_phys_addr_t addr, uint32_t value);
  31 typedef uint32_t CPUReadMemoryFunc(void *opaque, target_phys_addr_t addr);
  32
  33 void cpu_register_physical_memory_log(target_phys_addr_t start_addr,
  34                                       ram_addr_t size,
  35                                       ram_addr_t phys_offset,
  36                                       ram_addr_t region_offset,
  37                                       bool log_dirty);
  38
  39 static inline void cpu_register_physical_memory_offset(target_phys_addr_t start_addr,
  40                                                        ram_addr_t size,
  41                                                        ram_addr_t phys_offset,
  42                                                        ram_addr_t region_offset)
  43 {
  44     cpu_register_physical_memory_log(start_addr, size, phys_offset,
  45                                      region_offset, false);
  46 }
  47
  48 static inline void cpu_register_physical_memory(target_phys_addr_t start_addr,
  49                                                 ram_addr_t size,
  50                                                 ram_addr_t phys_offset)
  51 {
  52     cpu_register_physical_memory_offset(start_addr, size, phys_offset, 0);
  53 }
  54
  55 ram_addr_t cpu_get_physical_page_desc(target_phys_addr_t addr);
  56 ram_addr_t qemu_ram_alloc_from_ptr(DeviceState *dev, const char *name,
  57                         ram_addr_t size, void *host);
  58 ram_addr_t qemu_ram_alloc(DeviceState *dev, const char *name, ram_addr_t size);
  59 void qemu_ram_free(ram_addr_t addr);
  60 void qemu_ram_free_from_ptr(ram_addr_t addr);
  61 void qemu_ram_remap(ram_addr_t addr, ram_addr_t length);
  62 /* This should only be used for ram local to a device.  */
  63 void *qemu_get_ram_ptr(ram_addr_t addr);
  64 void *qemu_ram_ptr_length(ram_addr_t addr, ram_addr_t *size);
  65 /* Same but slower, to use for migration, where the order of
  66  * RAMBlocks must not change. */
  67 void *qemu_safe_ram_ptr(ram_addr_t addr);
  68 void qemu_put_ram_ptr(void *addr);
  69 /* This should not be used by devices.  */
  70 int qemu_ram_addr_from_host(void *ptr, ram_addr_t *ram_addr);
  71 ram_addr_t qemu_ram_addr_from_host_nofail(void *ptr);
  72
  73 int cpu_register_io_memory(CPUReadMemoryFunc * const *mem_read,
  74                            CPUWriteMemoryFunc * const *mem_write,
  75                            void *opaque, enum device_endian endian);
  76 void cpu_unregister_io_memory(int table_address);
  77
  78 void cpu_physical_memory_rw(target_phys_addr_t addr, uint8_t *buf,
  79                             int len, int is_write);
  80 static inline void cpu_physical_memory_read(target_phys_addr_t addr,
  81                                             void *buf, int len)
  82 {
  83     cpu_physical_memory_rw(addr, buf, len, 0);
  84 }
  85 static inline void cpu_physical_memory_write(target_phys_addr_t addr,
  86                                              const void *buf, int len)
  87 {
  88     cpu_physical_memory_rw(addr, (void *)buf, len, 1);
  89 }
  90 void *cpu_physical_memory_map(target_phys_addr_t addr,
  91                               target_phys_addr_t *plen,
  92                               int is_write);
  93 void cpu_physical_memory_unmap(void *buffer, target_phys_addr_t len,
  94                                int is_write, target_phys_addr_t access_len);
  95 void *cpu_register_map_client(void *opaque, void (*callback)(void *opaque));
  96 void cpu_unregister_map_client(void *cookie);
  97
  98 struct CPUPhysMemoryClient;
  99 typedef struct CPUPhysMemoryClient CPUPhysMemoryClient;
 100 struct CPUPhysMemoryClient {
 101     void (*set_memory)(struct CPUPhysMemoryClient *client,
 102                        target_phys_addr_t start_addr,
 103                        ram_addr_t size,
 104                        ram_addr_t phys_offset,
 105                        bool log_dirty);
 106     int (*sync_dirty_bitmap)(struct CPUPhysMemoryClient *client,
 107                              target_phys_addr_t start_addr,
 108                              target_phys_addr_t end_addr);
 109     int (*migration_log)(struct CPUPhysMemoryClient *client,
 110                          int enable);
 111     int (*log_start)(struct CPUPhysMemoryClient *client,
 112                      target_phys_addr_t phys_addr, ram_addr_t size);
 113     int (*log_stop)(struct CPUPhysMemoryClient *client,
 114                     target_phys_addr_t phys_addr, ram_addr_t size);
 115     QLIST_ENTRY(CPUPhysMemoryClient) list;
 116 };
 117
 118 void cpu_register_phys_memory_client(CPUPhysMemoryClient *);
 119 void cpu_unregister_phys_memory_client(CPUPhysMemoryClient *);
 120
 121 /* Coalesced MMIO regions are areas where write operations can be reordered.
 122  * This usually implies that write operations are side-effect free.  This allows
 123  * batching which can make a major impact on performance when using
 124  * virtualization.
 125  */
 126 void qemu_register_coalesced_mmio(target_phys_addr_t addr, ram_addr_t size);
 127
 128 void qemu_unregister_coalesced_mmio(target_phys_addr_t addr, ram_addr_t size);
 129
 130 void qemu_flush_coalesced_mmio_buffer(void);
 131
 132 uint32_t ldub_phys(target_phys_addr_t addr);
 133 uint32_t lduw_le_phys(target_phys_addr_t addr);
 134 uint32_t lduw_be_phys(target_phys_addr_t addr);
 135 uint32_t ldl_le_phys(target_phys_addr_t addr);
 136 uint32_t ldl_be_phys(target_phys_addr_t addr);
 137 uint64_t ldq_le_phys(target_phys_addr_t addr);
 138 uint64_t ldq_be_phys(target_phys_addr_t addr);
 139 void stb_phys(target_phys_addr_t addr, uint32_t val);
 140 void stw_le_phys(target_phys_addr_t addr, uint32_t val);
 141 void stw_be_phys(target_phys_addr_t addr, uint32_t val);
 142 void stl_le_phys(target_phys_addr_t addr, uint32_t val);
 143 void stl_be_phys(target_phys_addr_t addr, uint32_t val);
 144 void stq_le_phys(target_phys_addr_t addr, uint64_t val);
 145 void stq_be_phys(target_phys_addr_t addr, uint64_t val);
 146
 147 #ifdef NEED_CPU_H
 148 uint32_t lduw_phys(target_phys_addr_t addr);
 149 uint32_t ldl_phys(target_phys_addr_t addr);
 150 uint64_t ldq_phys(target_phys_addr_t addr);
 151 void stl_phys_notdirty(target_phys_addr_t addr, uint32_t val);
 152 void stq_phys_notdirty(target_phys_addr_t addr, uint64_t val);
 153 void stw_phys(target_phys_addr_t addr, uint32_t val);
 154 void stl_phys(target_phys_addr_t addr, uint32_t val);
 155 void stq_phys(target_phys_addr_t addr, uint64_t val);
 156 #endif
 157
 158 void cpu_physical_memory_write_rom(target_phys_addr_t addr,
 159                                    const uint8_t *buf, int len);
 160
 161 #define IO_MEM_SHIFT       3
 162
 163 #define IO_MEM_RAM         (0 << IO_MEM_SHIFT) /* hardcoded offset */
 164 #define IO_MEM_ROM         (1 << IO_MEM_SHIFT) /* hardcoded offset */
 165 #define IO_MEM_UNASSIGNED  (2 << IO_MEM_SHIFT)
 166 #define IO_MEM_NOTDIRTY    (3 << IO_MEM_SHIFT)
 167
 168 /* Acts like a ROM when read and like a device when written.  */
 169 #define IO_MEM_ROMD        (1)
 170 #define IO_MEM_SUBPAGE     (2)
 171
 172 #endif
 173
 174 #endif /* !CPU_COMMON_H */