hw/pxa2xx_pic.c

   1 /*
   2  * Intel XScale PXA Programmable Interrupt Controller.
   3  *
   4  * Copyright (c) 2006 Openedhand Ltd.
   5  * Copyright (c) 2006 Thorsten Zitterell
   6  * Written by Andrzej Zaborowski <balrog@zabor.org>
   7  *
   8  * This code is licensed under the GPL.
   9  */
  10
  11 #include "hw.h"
  12 #include "pxa.h"
  13 #include "sysbus.h"
  14
  15 #define ICIP    0x00    /* Interrupt Controller IRQ Pending register */
  16 #define ICMR    0x04    /* Interrupt Controller Mask register */
  17 #define ICLR    0x08    /* Interrupt Controller Level register */
  18 #define ICFP    0x0c    /* Interrupt Controller FIQ Pending register */
  19 #define ICPR    0x10    /* Interrupt Controller Pending register */
  20 #define ICCR    0x14    /* Interrupt Controller Control register */
  21 #define ICHP    0x18    /* Interrupt Controller Highest Priority register */
  22 #define IPR0    0x1c    /* Interrupt Controller Priority register 0 */
  23 #define IPR31   0x98    /* Interrupt Controller Priority register 31 */
  24 #define ICIP2   0x9c    /* Interrupt Controller IRQ Pending register 2 */
  25 #define ICMR2   0xa0    /* Interrupt Controller Mask register 2 */
  26 #define ICLR2   0xa4    /* Interrupt Controller Level register 2 */
  27 #define ICFP2   0xa8    /* Interrupt Controller FIQ Pending register 2 */
  28 #define ICPR2   0xac    /* Interrupt Controller Pending register 2 */
  29 #define IPR32   0xb0    /* Interrupt Controller Priority register 32 */
  30 #define IPR39   0xcc    /* Interrupt Controller Priority register 39 */
  31
  32 #define PXA2XX_PIC_SRCS 40
  33
  34 typedef struct {
  35     SysBusDevice busdev;
  36     CPUState *cpu_env;
  37     uint32_t int_enabled[2];
  38     uint32_t int_pending[2];
  39     uint32_t is_fiq[2];
  40     uint32_t int_idle;
  41     uint32_t priority[PXA2XX_PIC_SRCS];
  42 } PXA2xxPICState;
  43
  44 static void pxa2xx_pic_update(void *opaque)
  45 {
  46     uint32_t mask[2];
  47     PXA2xxPICState *s = (PXA2xxPICState *) opaque;
  48
  49     if (s->cpu_env->halted) {
  50         mask[0] = s->int_pending[0] & (s->int_enabled[0] | s->int_idle);
  51         mask[1] = s->int_pending[1] & (s->int_enabled[1] | s->int_idle);
  52         if (mask[0] || mask[1])
  53             cpu_interrupt(s->cpu_env, CPU_INTERRUPT_EXITTB);
  54     }
  55
  56     mask[0] = s->int_pending[0] & s->int_enabled[0];
  57     mask[1] = s->int_pending[1] & s->int_enabled[1];
  58
  59     if ((mask[0] & s->is_fiq[0]) || (mask[1] & s->is_fiq[1]))
  60         cpu_interrupt(s->cpu_env, CPU_INTERRUPT_FIQ);
  61     else
  62         cpu_reset_interrupt(s->cpu_env, CPU_INTERRUPT_FIQ);
  63
  64     if ((mask[0] & ~s->is_fiq[0]) || (mask[1] & ~s->is_fiq[1]))
  65         cpu_interrupt(s->cpu_env, CPU_INTERRUPT_HARD);
  66     else
  67         cpu_reset_interrupt(s->cpu_env, CPU_INTERRUPT_HARD);
  68 }
  69
  70 /* Note: Here level means state of the signal on a pin, not
  71  * IRQ/FIQ distinction as in PXA Developer Manual.  */
  72 static void pxa2xx_pic_set_irq(void *opaque, int irq, int level)
  73 {
  74     PXA2xxPICState *s = (PXA2xxPICState *) opaque;
  75     int int_set = (irq >= 32);
  76     irq &= 31;
  77
  78     if (level)
  79         s->int_pending[int_set] |= 1 << irq;
  80     else
  81         s->int_pending[int_set] &= ~(1 << irq);
  82
  83     pxa2xx_pic_update(opaque);
  84 }
  85
  86 static inline uint32_t pxa2xx_pic_highest(PXA2xxPICState *s) {
  87     int i, int_set, irq;
  88     uint32_t bit, mask[2];
  89     uint32_t ichp = 0x003f003f; /* Both IDs invalid */
  90
  91     mask[0] = s->int_pending[0] & s->int_enabled[0];
  92     mask[1] = s->int_pending[1] & s->int_enabled[1];
  93
  94     for (i = PXA2XX_PIC_SRCS - 1; i >= 0; i --) {
  95         irq = s->priority[i] & 0x3f;
  96         if ((s->priority[i] & (1 << 31)) && irq < PXA2XX_PIC_SRCS) {
  97             /* Source peripheral ID is valid.  */
  98             bit = 1 << (irq & 31);
  99             int_set = (irq >= 32);
 100
 101             if (mask[int_set] & bit & s->is_fiq[int_set]) {
 102                 /* FIQ asserted */
 103                 ichp &= 0xffff0000;
 104                 ichp |= (1 << 15) | irq;
 105             }
 106
 107             if (mask[int_set] & bit & ~s->is_fiq[int_set]) {
 108                 /* IRQ asserted */
 109                 ichp &= 0x0000ffff;
 110                 ichp |= (1 << 31) | (irq << 16);
 111             }
 112         }
 113     }
 114
 115     return ichp;
 116 }
 117
 118 static uint32_t pxa2xx_pic_mem_read(void *opaque, target_phys_addr_t offset)
 119 {
 120     PXA2xxPICState *s = (PXA2xxPICState *) opaque;
 121
 122     switch (offset) {
 123     case ICIP:  /* IRQ Pending register */
 124         return s->int_pending[0] & ~s->is_fiq[0] & s->int_enabled[0];
 125     case ICIP2: /* IRQ Pending register 2 */
 126         return s->int_pending[1] & ~s->is_fiq[1] & s->int_enabled[1];
 127     case ICMR:  /* Mask register */
 128         return s->int_enabled[0];
 129     case ICMR2: /* Mask register 2 */
 130         return s->int_enabled[1];
 131     case ICLR:  /* Level register */
 132         return s->is_fiq[0];
 133     case ICLR2: /* Level register 2 */
 134         return s->is_fiq[1];
 135     case ICCR:  /* Idle mask */
 136         return (s->int_idle == 0);
 137     case ICFP:  /* FIQ Pending register */
 138         return s->int_pending[0] & s->is_fiq[0] & s->int_enabled[0];
 139     case ICFP2: /* FIQ Pending register 2 */
 140         return s->int_pending[1] & s->is_fiq[1] & s->int_enabled[1];
 141     case ICPR:  /* Pending register */
 142         return s->int_pending[0];
 143     case ICPR2: /* Pending register 2 */
 144         return s->int_pending[1];
 145     case IPR0  ... IPR31:
 146         return s->priority[0  + ((offset - IPR0 ) >> 2)];
 147     case IPR32 ... IPR39:
 148         return s->priority[32 + ((offset - IPR32) >> 2)];
 149     case ICHP:  /* Highest Priority register */
 150         return pxa2xx_pic_highest(s);
 151     default:
 152         printf("%s: Bad register offset " REG_FMT "\n", __FUNCTION__, offset);
 153         return 0;
 154     }
 155 }
 156
 157 static void pxa2xx_pic_mem_write(void *opaque, target_phys_addr_t offset,
 158                 uint32_t value)
 159 {
 160     PXA2xxPICState *s = (PXA2xxPICState *) opaque;
 161
 162     switch (offset) {
 163     case ICMR:  /* Mask register */
 164         s->int_enabled[0] = value;
 165         break;
 166     case ICMR2: /* Mask register 2 */
 167         s->int_enabled[1] = value;
 168         break;
 169     case ICLR:  /* Level register */
 170         s->is_fiq[0] = value;
 171         break;
 172     case ICLR2: /* Level register 2 */
 173         s->is_fiq[1] = value;
 174         break;
 175     case ICCR:  /* Idle mask */
 176         s->int_idle = (value & 1) ? 0 : ~0;
 177         break;
 178     case IPR0  ... IPR31:
 179         s->priority[0  + ((offset - IPR0 ) >> 2)] = value & 0x8000003f;
 180         break;
 181     case IPR32 ... IPR39:
 182         s->priority[32 + ((offset - IPR32) >> 2)] = value & 0x8000003f;
 183         break;
 184     default:
 185         printf("%s: Bad register offset " REG_FMT "\n", __FUNCTION__, offset);
 186         return;
 187     }
 188     pxa2xx_pic_update(opaque);
 189 }
 190
 191 /* Interrupt Controller Coprocessor Space Register Mapping */
 192 static const int pxa2xx_cp_reg_map[0x10] = {
 193     [0x0 ... 0xf] = -1,
 194     [0x0] = ICIP,
 195     [0x1] = ICMR,
 196     [0x2] = ICLR,
 197     [0x3] = ICFP,
 198     [0x4] = ICPR,
 199     [0x5] = ICHP,
 200     [0x6] = ICIP2,
 201     [0x7] = ICMR2,
 202     [0x8] = ICLR2,
 203     [0x9] = ICFP2,
 204     [0xa] = ICPR2,
 205 };
 206
 207 static uint32_t pxa2xx_pic_cp_read(void *opaque, int op2, int reg, int crm)
 208 {
 209     target_phys_addr_t offset;
 210
 211     if (pxa2xx_cp_reg_map[reg] == -1) {
 212         printf("%s: Bad register 0x%x\n", __FUNCTION__, reg);
 213         return 0;
 214     }
 215
 216     offset = pxa2xx_cp_reg_map[reg];
 217     return pxa2xx_pic_mem_read(opaque, offset);
 218 }
 219
 220 static void pxa2xx_pic_cp_write(void *opaque, int op2, int reg, int crm,
 221                 uint32_t value)
 222 {
 223     target_phys_addr_t offset;
 224
 225     if (pxa2xx_cp_reg_map[reg] == -1) {
 226         printf("%s: Bad register 0x%x\n", __FUNCTION__, reg);
 227         return;
 228     }
 229
 230     offset = pxa2xx_cp_reg_map[reg];
 231     pxa2xx_pic_mem_write(opaque, offset, value);
 232 }
 233
 234 static CPUReadMemoryFunc * const pxa2xx_pic_readfn[] = {
 235     pxa2xx_pic_mem_read,
 236     pxa2xx_pic_mem_read,
 237     pxa2xx_pic_mem_read,
 238 };
 239
 240 static CPUWriteMemoryFunc * const pxa2xx_pic_writefn[] = {
 241     pxa2xx_pic_mem_write,
 242     pxa2xx_pic_mem_write,
 243     pxa2xx_pic_mem_write,
 244 };
 245
 246 static int pxa2xx_pic_post_load(void *opaque, int version_id)
 247 {
 248     pxa2xx_pic_update(opaque);
 249     return 0;
 250 }
 251
 252 DeviceState *pxa2xx_pic_init(target_phys_addr_t base, CPUState *env)
 253 {
 254     DeviceState *dev = qdev_create(NULL, "pxa2xx_pic");
 255     int iomemtype;
 256     PXA2xxPICState *s = FROM_SYSBUS(PXA2xxPICState, sysbus_from_qdev(dev));
 257
 258     s->cpu_env = env;
 259
 260     s->int_pending[0] = 0;
 261     s->int_pending[1] = 0;
 262     s->int_enabled[0] = 0;
 263     s->int_enabled[1] = 0;
 264     s->is_fiq[0] = 0;
 265     s->is_fiq[1] = 0;
 266
 267     qdev_init_nofail(dev);
 268
 269     qdev_init_gpio_in(dev, pxa2xx_pic_set_irq, PXA2XX_PIC_SRCS);
 270
 271     /* Enable IC memory-mapped registers access.  */
 272     iomemtype = cpu_register_io_memory(pxa2xx_pic_readfn,
 273                     pxa2xx_pic_writefn, s, DEVICE_NATIVE_ENDIAN);
 274     sysbus_init_mmio(sysbus_from_qdev(dev), 0x00100000, iomemtype);
 275     sysbus_mmio_map(sysbus_from_qdev(dev), 0, base);
 276
 277     /* Enable IC coprocessor access.  */
 278     cpu_arm_set_cp_io(env, 6, pxa2xx_pic_cp_read, pxa2xx_pic_cp_write, s);
 279
 280     return dev;
 281 }
 282
 283 static VMStateDescription vmstate_pxa2xx_pic_regs = {
 284     .name = "pxa2xx_pic",
 285     .version_id = 0,
 286     .minimum_version_id = 0,
 287     .minimum_version_id_old = 0,
 288     .post_load = pxa2xx_pic_post_load,
 289     .fields = (VMStateField[]) {
 290         VMSTATE_UINT32_ARRAY(int_enabled, PXA2xxPICState, 2),
 291         VMSTATE_UINT32_ARRAY(int_pending, PXA2xxPICState, 2),
 292         VMSTATE_UINT32_ARRAY(is_fiq, PXA2xxPICState, 2),
 293         VMSTATE_UINT32(int_idle, PXA2xxPICState),
 294         VMSTATE_UINT32_ARRAY(priority, PXA2xxPICState, PXA2XX_PIC_SRCS),
 295         VMSTATE_END_OF_LIST(),
 296     },
 297 };
 298
 299 static int pxa2xx_pic_initfn(SysBusDevice *dev)
 300 {
 301     return 0;
 302 }
 303
 304 static SysBusDeviceInfo pxa2xx_pic_info = {
 305     .init       = pxa2xx_pic_initfn,
 306     .qdev.name  = "pxa2xx_pic",
 307     .qdev.desc  = "PXA2xx PIC",
 308     .qdev.size  = sizeof(PXA2xxPICState),
 309     .qdev.vmsd  = &vmstate_pxa2xx_pic_regs,
 310 };
 311
 312 static void pxa2xx_pic_register(void)
 313 {
 314     sysbus_register_withprop(&pxa2xx_pic_info);
 315 }
 316 device_init(pxa2xx_pic_register);