hw/pl011.c

   1 /*
   2  * Arm PrimeCell PL011 UART
   3  *
   4  * Copyright (c) 2006 CodeSourcery.
   5  * Written by Paul Brook
   6  *
   7  * This code is licensed under the GPL.
   8  */
   9
  10 #include "sysbus.h"
  11 #include "qemu-char.h"
  12
  13 typedef struct {
  14     SysBusDevice busdev;
  15     uint32_t readbuff;
  16     uint32_t flags;
  17     uint32_t lcr;
  18     uint32_t cr;
  19     uint32_t dmacr;
  20     uint32_t int_enabled;
  21     uint32_t int_level;
  22     uint32_t read_fifo[16];
  23     uint32_t ilpr;
  24     uint32_t ibrd;
  25     uint32_t fbrd;
  26     uint32_t ifl;
  27     int read_pos;
  28     int read_count;
  29     int read_trigger;
  30     CharDriverState *chr;
  31     qemu_irq irq;
  32     const unsigned char *id;
  33 } pl011_state;
  34
  35 #define PL011_INT_TX 0x20
  36 #define PL011_INT_RX 0x10
  37
  38 #define PL011_FLAG_TXFE 0x80
  39 #define PL011_FLAG_RXFF 0x40
  40 #define PL011_FLAG_TXFF 0x20
  41 #define PL011_FLAG_RXFE 0x10
  42
  43 static const unsigned char pl011_id_arm[8] =
  44   { 0x11, 0x10, 0x14, 0x00, 0x0d, 0xf0, 0x05, 0xb1 };
  45 static const unsigned char pl011_id_luminary[8] =
  46   { 0x11, 0x00, 0x18, 0x01, 0x0d, 0xf0, 0x05, 0xb1 };
  47
  48 static void pl011_update_handlers(pl011_state *s);
  49
  50 static void pl011_update(pl011_state *s)
  51 {
  52     uint32_t flags;
  53
  54     flags = s->int_level & s->int_enabled;
  55     qemu_set_irq(s->irq, flags != 0);
  56 }
  57
  58 static uint32_t pl011_read(void *opaque, target_phys_addr_t offset)
  59 {
  60     pl011_state *s = (pl011_state *)opaque;
  61     uint32_t c;
  62
  63     if (offset >= 0xfe0 && offset < 0x1000) {
  64         return s->id[(offset - 0xfe0) >> 2];
  65     }
  66     switch (offset >> 2) {
  67     case 0: /* UARTDR */
  68         s->flags &= ~PL011_FLAG_RXFF;
  69         c = s->read_fifo[s->read_pos];
  70         if (s->read_count > 0) {
  71             s->read_count--;
  72             if (++s->read_pos == 16)
  73                 s->read_pos = 0;
  74             pl011_update_handlers(s);
  75         }
  76         if (s->read_count == 0) {
  77             s->flags |= PL011_FLAG_RXFE;
  78         }
  79         if (s->read_count == s->read_trigger - 1)
  80             s->int_level &= ~ PL011_INT_RX;
  81         pl011_update(s);
  82         return c;
  83     case 1: /* UARTCR */
  84         return 0;
  85     case 6: /* UARTFR */
  86         return s->flags;
  87     case 8: /* UARTILPR */
  88         return s->ilpr;
  89     case 9: /* UARTIBRD */
  90         return s->ibrd;
  91     case 10: /* UARTFBRD */
  92         return s->fbrd;
  93     case 11: /* UARTLCR_H */
  94         return s->lcr;
  95     case 12: /* UARTCR */
  96         return s->cr;
  97     case 13: /* UARTIFLS */
  98         return s->ifl;
  99     case 14: /* UARTIMSC */
 100         return s->int_enabled;
 101     case 15: /* UARTRIS */
 102         return s->int_level;
 103     case 16: /* UARTMIS */
 104         return s->int_level & s->int_enabled;
 105     case 18: /* UARTDMACR */
 106         return s->dmacr;
 107     default:
 108         hw_error("pl011_read: Bad offset %x\n", (int)offset);
 109         return 0;
 110     }
 111 }
 112
 113 static void pl011_set_read_trigger(pl011_state *s)
 114 {
 115 #if 0
 116     /* The docs say the RX interrupt is triggered when the FIFO exceeds
 117        the threshold.  However linux only reads the FIFO in response to an
 118        interrupt.  Triggering the interrupt when the FIFO is non-empty seems
 119        to make things work.  */
 120     if (s->lcr & 0x10)
 121         s->read_trigger = (s->ifl >> 1) & 0x1c;
 122     else
 123 #endif
 124         s->read_trigger = 1;
 125 }
 126
 127 static void pl011_write(void *opaque, target_phys_addr_t offset,
 128                           uint32_t value)
 129 {
 130     pl011_state *s = (pl011_state *)opaque;
 131     unsigned char ch;
 132
 133     switch (offset >> 2) {
 134     case 0: /* UARTDR */
 135         /* ??? Check if transmitter is enabled.  */
 136         ch = value;
 137         if (s->chr)
 138             qemu_chr_fe_write(s->chr, &ch, 1);
 139         s->int_level |= PL011_INT_TX;
 140         pl011_update(s);
 141         break;
 142     case 1: /* UARTCR */
 143         s->cr = value;
 144         break;
 145     case 6: /* UARTFR */
 146         /* Writes to Flag register are ignored.  */
 147         break;
 148     case 8: /* UARTUARTILPR */
 149         s->ilpr = value;
 150         break;
 151     case 9: /* UARTIBRD */
 152         s->ibrd = value;
 153         break;
 154     case 10: /* UARTFBRD */
 155         s->fbrd = value;
 156         break;
 157     case 11: /* UARTLCR_H */
 158         s->lcr = value;
 159         pl011_update_handlers(s);
 160         pl011_set_read_trigger(s);
 161         break;
 162     case 12: /* UARTCR */
 163         /* ??? Need to implement the enable and loopback bits.  */
 164         s->cr = value;
 165         break;
 166     case 13: /* UARTIFS */
 167         s->ifl = value;
 168         pl011_set_read_trigger(s);
 169         break;
 170     case 14: /* UARTIMSC */
 171         s->int_enabled = value;
 172         pl011_update(s);
 173         break;
 174     case 17: /* UARTICR */
 175         s->int_level &= ~value;
 176         pl011_update(s);
 177         break;
 178     case 18: /* UARTDMACR */
 179         s->dmacr = value;
 180         if (value & 3)
 181             hw_error("PL011: DMA not implemented\n");
 182         break;
 183     default:
 184         hw_error("pl011_write: Bad offset %x\n", (int)offset);
 185     }
 186 }
 187
 188 static int pl011_can_receive(pl011_state *s)
 189 {
 190     if (s->lcr & 0x10)
 191         return s->read_count < 16;
 192     else
 193         return s->read_count < 1;
 194 }
 195
 196 static void pl011_put_fifo(pl011_state *s, uint32_t value)
 197 {
 198     int slot;
 199
 200     slot = s->read_pos + s->read_count;
 201     if (slot >= 16)
 202         slot -= 16;
 203     s->read_fifo[slot] = value;
 204     s->read_count++;
 205     s->flags &= ~PL011_FLAG_RXFE;
 206     if (s->cr & 0x10 || s->read_count == 16) {
 207         s->flags |= PL011_FLAG_RXFF;
 208     }
 209     if (s->read_count == s->read_trigger) {
 210         s->int_level |= PL011_INT_RX;
 211         pl011_update(s);
 212     }
 213     pl011_update_handlers(s);
 214 }
 215
 216 static void pl011_receive(pl011_state *s, const uint8_t *buf, int size)
 217 {
 218     pl011_put_fifo(s, *buf);
 219 }
 220
 221 static int pl011_event(void *opaque, int event, void *data)
 222 {
 223     if (event == CHR_EVENT_BREAK)
 224         pl011_put_fifo(opaque, 0x400);
 225     return 0;
 226 }
 227
 228 static void pl011_receive_handler(void *opaque)
 229 {
 230     pl011_state *s = opaque;
 231     uint8_t buf[32];
 232     int size;
 233
 234     size = pl011_can_receive(s);
 235     size = MIN(size, sizeof(buf));
 236     size = qemu_chr_fe_read(s->chr, buf, size);
 237
 238     pl011_receive(s, buf, size);
 239 }
 240
 241 static void pl011_update_handlers(pl011_state *s)
 242 {
 243     if (pl011_can_receive(s) > 0) {
 244         qemu_chr_fe_set_handlers(s->chr, pl011_receive_handler, NULL,
 245                                  pl011_event, s);
 246     } else {
 247         qemu_chr_fe_set_handlers(s->chr, NULL, NULL, pl011_event, s);
 248     }
 249 }
 250
 251 static CPUReadMemoryFunc * const pl011_readfn[] = {
 252    pl011_read,
 253    pl011_read,
 254    pl011_read
 255 };
 256
 257 static CPUWriteMemoryFunc * const pl011_writefn[] = {
 258    pl011_write,
 259    pl011_write,
 260    pl011_write
 261 };
 262
 263 static const VMStateDescription vmstate_pl011 = {
 264     .name = "pl011",
 265     .version_id = 1,
 266     .minimum_version_id = 1,
 267     .minimum_version_id_old = 1,
 268     .fields      = (VMStateField[]) {
 269         VMSTATE_UINT32(readbuff, pl011_state),
 270         VMSTATE_UINT32(flags, pl011_state),
 271         VMSTATE_UINT32(lcr, pl011_state),
 272         VMSTATE_UINT32(cr, pl011_state),
 273         VMSTATE_UINT32(dmacr, pl011_state),
 274         VMSTATE_UINT32(int_enabled, pl011_state),
 275         VMSTATE_UINT32(int_level, pl011_state),
 276         VMSTATE_UINT32_ARRAY(read_fifo, pl011_state, 16),
 277         VMSTATE_UINT32(ilpr, pl011_state),
 278         VMSTATE_UINT32(ibrd, pl011_state),
 279         VMSTATE_UINT32(fbrd, pl011_state),
 280         VMSTATE_UINT32(ifl, pl011_state),
 281         VMSTATE_INT32(read_pos, pl011_state),
 282         VMSTATE_INT32(read_count, pl011_state),
 283         VMSTATE_INT32(read_trigger, pl011_state),
 284         VMSTATE_END_OF_LIST()
 285     }
 286 };
 287
 288 static int pl011_init(SysBusDevice *dev, const unsigned char *id)
 289 {
 290     int iomemtype;
 291     pl011_state *s = FROM_SYSBUS(pl011_state, dev);
 292
 293     iomemtype = cpu_register_io_memory(pl011_readfn,
 294                                        pl011_writefn, s,
 295                                        DEVICE_NATIVE_ENDIAN);
 296     sysbus_init_mmio(dev, 0x1000,iomemtype);
 297     sysbus_init_irq(dev, &s->irq);
 298     s->id = id;
 299     s->chr = qdev_init_chardev(&dev->qdev);
 300
 301     s->read_trigger = 1;
 302     s->ifl = 0x12;
 303     s->cr = 0x300;
 304     s->flags = 0x90;
 305     if (s->chr) {
 306         qemu_chr_fe_open(s->chr);
 307         pl011_update_handlers(s);
 308     }
 309     vmstate_register(&dev->qdev, -1, &vmstate_pl011, s);
 310     return 0;
 311 }
 312
 313 static int pl011_init_arm(SysBusDevice *dev)
 314 {
 315     return pl011_init(dev, pl011_id_arm);
 316 }
 317
 318 static int pl011_init_luminary(SysBusDevice *dev)
 319 {
 320     return pl011_init(dev, pl011_id_luminary);
 321 }
 322
 323 static void pl011_register_devices(void)
 324 {
 325     sysbus_register_dev("pl011", sizeof(pl011_state),
 326                         pl011_init_arm);
 327     sysbus_register_dev("pl011_luminary", sizeof(pl011_state),
 328                         pl011_init_luminary);
 329 }
 330
 331 device_init(pl011_register_devices)