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char: implement get_msgfd in terms of an ioctl
[qemu/aliguori.git] / hw / eepro100.c
bloba636d309bef74b6d31908cca111460c43695bce4
1 /*
2 * QEMU i8255x (PRO100) emulation
3 *
4 * Copyright (C) 2006-2011 Stefan Weil
5 *
6 * Portions of the code are copies from grub / etherboot eepro100.c
7 * and linux e100.c.
8 *
9 * This program is free software: you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation, either version 2 of the License, or
12 * (at your option) version 3 or any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program. If not, see <http://www.gnu.org/licenses/>.
21 *
22 * Tested features (i82559):
23 * PXE boot (i386 guest, i386 / mips / mipsel / ppc host) ok
24 * Linux networking (i386) ok
25 *
26 * Untested:
27 * Windows networking
28 *
29 * References:
30 *
31 * Intel 8255x 10/100 Mbps Ethernet Controller Family
32 * Open Source Software Developer Manual
33 *
34 * TODO:
35 * * PHY emulation should be separated from nic emulation.
36 * Most nic emulations could share the same phy code.
37 * * i82550 is untested. It is programmed like the i82559.
38 * * i82562 is untested. It is programmed like the i82559.
39 * * Power management (i82558 and later) is not implemented.
40 * * Wake-on-LAN is not implemented.
41 */
42
43 #include <stddef.h> /* offsetof */
44 #include "hw.h"
45 #include "pci.h"
46 #include "net.h"
47 #include "eeprom93xx.h"
48 #include "sysemu.h"
49
50 /* QEMU sends frames smaller than 60 bytes to ethernet nics.
51 * Such frames are rejected by real nics and their emulations.
52 * To avoid this behaviour, other nic emulations pad received
53 * frames. The following definition enables this padding for
54 * eepro100, too. We keep the define around in case it might
55 * become useful the future if the core networking is ever
56 * changed to pad short packets itself. */
57 #define CONFIG_PAD_RECEIVED_FRAMES
58
59 #define KiB 1024
60
61 /* Debug EEPRO100 card. */
62 #if 0
63 # define DEBUG_EEPRO100
64 #endif
65
66 #ifdef DEBUG_EEPRO100
67 #define logout(fmt, ...) fprintf(stderr, "EE100\t%-24s" fmt, __func__, ## __VA_ARGS__)
68 #else
69 #define logout(fmt, ...) ((void)0)
70 #endif
71
72 /* Set flags to 0 to disable debug output. */
73 #define INT 1 /* interrupt related actions */
74 #define MDI 1 /* mdi related actions */
75 #define OTHER 1
76 #define RXTX 1
77 #define EEPROM 1 /* eeprom related actions */
78
79 #define TRACE(flag, command) ((flag) ? (command) : (void)0)
80
81 #define missing(text) fprintf(stderr, "eepro100: feature is missing in this emulation: " text "\n")
82
83 #define MAX_ETH_FRAME_SIZE 1514
84
85 /* This driver supports several different devices which are declared here. */
86 #define i82550 0x82550
87 #define i82551 0x82551
88 #define i82557A 0x82557a
89 #define i82557B 0x82557b
90 #define i82557C 0x82557c
91 #define i82558A 0x82558a
92 #define i82558B 0x82558b
93 #define i82559A 0x82559a
94 #define i82559B 0x82559b
95 #define i82559C 0x82559c
96 #define i82559ER 0x82559e
97 #define i82562 0x82562
98 #define i82801 0x82801
99
100 /* Use 64 word EEPROM. TODO: could be a runtime option. */
101 #define EEPROM_SIZE 64
102
103 #define PCI_MEM_SIZE (4 * KiB)
104 #define PCI_IO_SIZE 64
105 #define PCI_FLASH_SIZE (128 * KiB)
106
107 #define BIT(n) (1 << (n))
108 #define BITS(n, m) (((0xffffffffU << (31 - n)) >> (31 - n + m)) << m)
109
110 /* The SCB accepts the following controls for the Tx and Rx units: */
111 #define CU_NOP 0x0000 /* No operation. */
112 #define CU_START 0x0010 /* CU start. */
113 #define CU_RESUME 0x0020 /* CU resume. */
114 #define CU_STATSADDR 0x0040 /* Load dump counters address. */
115 #define CU_SHOWSTATS 0x0050 /* Dump statistical counters. */
116 #define CU_CMD_BASE 0x0060 /* Load CU base address. */
117 #define CU_DUMPSTATS 0x0070 /* Dump and reset statistical counters. */
118 #define CU_SRESUME 0x00a0 /* CU static resume. */
119
120 #define RU_NOP 0x0000
121 #define RX_START 0x0001
122 #define RX_RESUME 0x0002
123 #define RU_ABORT 0x0004
124 #define RX_ADDR_LOAD 0x0006
125 #define RX_RESUMENR 0x0007
126 #define INT_MASK 0x0100
127 #define DRVR_INT 0x0200 /* Driver generated interrupt. */
128
129 typedef struct {
130 PCIDeviceInfo pci;
131 uint32_t device;
132 uint8_t stats_size;
133 bool has_extended_tcb_support;
134 bool power_management;
135 } E100PCIDeviceInfo;
136
137 /* Offsets to the various registers.
138 All accesses need not be longword aligned. */
139 typedef enum {
140 SCBStatus = 0, /* Status Word. */
141 SCBAck = 1,
142 SCBCmd = 2, /* Rx/Command Unit command and status. */
143 SCBIntmask = 3,
144 SCBPointer = 4, /* General purpose pointer. */
145 SCBPort = 8, /* Misc. commands and operands. */
146 SCBflash = 12, /* Flash memory control. */
147 SCBeeprom = 14, /* EEPROM control. */
148 SCBCtrlMDI = 16, /* MDI interface control. */
149 SCBEarlyRx = 20, /* Early receive byte count. */
150 SCBFlow = 24, /* Flow Control. */
151 SCBpmdr = 27, /* Power Management Driver. */
152 SCBgctrl = 28, /* General Control. */
153 SCBgstat = 29, /* General Status. */
154 } E100RegisterOffset;
155
156 /* A speedo3 transmit buffer descriptor with two buffers... */
157 typedef struct {
158 uint16_t status;
159 uint16_t command;
160 uint32_t link; /* void * */
161 uint32_t tbd_array_addr; /* transmit buffer descriptor array address. */
162 uint16_t tcb_bytes; /* transmit command block byte count (in lower 14 bits */
163 uint8_t tx_threshold; /* transmit threshold */
164 uint8_t tbd_count; /* TBD number */
165 #if 0
166 /* This constitutes two "TBD" entries: hdr and data */
167 uint32_t tx_buf_addr0; /* void *, header of frame to be transmitted. */
168 int32_t tx_buf_size0; /* Length of Tx hdr. */
169 uint32_t tx_buf_addr1; /* void *, data to be transmitted. */
170 int32_t tx_buf_size1; /* Length of Tx data. */
171 #endif
172 } eepro100_tx_t;
173
174 /* Receive frame descriptor. */
175 typedef struct {
176 int16_t status;
177 uint16_t command;
178 uint32_t link; /* struct RxFD * */
179 uint32_t rx_buf_addr; /* void * */
180 uint16_t count;
181 uint16_t size;
182 /* Ethernet frame data follows. */
183 } eepro100_rx_t;
184
185 typedef enum {
186 COMMAND_EL = BIT(15),
187 COMMAND_S = BIT(14),
188 COMMAND_I = BIT(13),
189 COMMAND_NC = BIT(4),
190 COMMAND_SF = BIT(3),
191 COMMAND_CMD = BITS(2, 0),
192 } scb_command_bit;
193
194 typedef enum {
195 STATUS_C = BIT(15),
196 STATUS_OK = BIT(13),
197 } scb_status_bit;
198
199 typedef struct {
200 uint32_t tx_good_frames, tx_max_collisions, tx_late_collisions,
201 tx_underruns, tx_lost_crs, tx_deferred, tx_single_collisions,
202 tx_multiple_collisions, tx_total_collisions;
203 uint32_t rx_good_frames, rx_crc_errors, rx_alignment_errors,
204 rx_resource_errors, rx_overrun_errors, rx_cdt_errors,
205 rx_short_frame_errors;
206 uint32_t fc_xmt_pause, fc_rcv_pause, fc_rcv_unsupported;
207 uint16_t xmt_tco_frames, rcv_tco_frames;
208 /* TODO: i82559 has six reserved statistics but a total of 24 dwords. */
209 uint32_t reserved[4];
210 } eepro100_stats_t;
211
212 typedef enum {
213 cu_idle = 0,
214 cu_suspended = 1,
215 cu_active = 2,
216 cu_lpq_active = 2,
217 cu_hqp_active = 3
218 } cu_state_t;
219
220 typedef enum {
221 ru_idle = 0,
222 ru_suspended = 1,
223 ru_no_resources = 2,
224 ru_ready = 4
225 } ru_state_t;
226
227 typedef struct {
228 PCIDevice dev;
229 /* Hash register (multicast mask array, multiple individual addresses). */
230 uint8_t mult[8];
231 MemoryRegion mmio_bar;
232 MemoryRegion io_bar;
233 MemoryRegion flash_bar;
234 NICState *nic;
235 NICConf conf;
236 uint8_t scb_stat; /* SCB stat/ack byte */
237 uint8_t int_stat; /* PCI interrupt status */
238 /* region must not be saved by nic_save. */
239 uint16_t mdimem[32];
240 eeprom_t *eeprom;
241 uint32_t device; /* device variant */
242 /* (cu_base + cu_offset) address the next command block in the command block list. */
243 uint32_t cu_base; /* CU base address */
244 uint32_t cu_offset; /* CU address offset */
245 /* (ru_base + ru_offset) address the RFD in the Receive Frame Area. */
246 uint32_t ru_base; /* RU base address */
247 uint32_t ru_offset; /* RU address offset */
248 uint32_t statsaddr; /* pointer to eepro100_stats_t */
249
250 /* Temporary status information (no need to save these values),
251 * used while processing CU commands. */
252 eepro100_tx_t tx; /* transmit buffer descriptor */
253 uint32_t cb_address; /* = cu_base + cu_offset */
254
255 /* Statistical counters. Also used for wake-up packet (i82559). */
256 eepro100_stats_t statistics;
257
258 /* Data in mem is always in the byte order of the controller (le).
259 * It must be dword aligned to allow direct access to 32 bit values. */
260 uint8_t mem[PCI_MEM_SIZE] __attribute__((aligned(8)));;
261
262 /* Configuration bytes. */
263 uint8_t configuration[22];
264
265 /* vmstate for each particular nic */
266 VMStateDescription *vmstate;
267
268 /* Quasi static device properties (no need to save them). */
269 uint16_t stats_size;
270 bool has_extended_tcb_support;
271 } EEPRO100State;
272
273 /* Word indices in EEPROM. */
274 typedef enum {
275 EEPROM_CNFG_MDIX = 0x03,
276 EEPROM_ID = 0x05,
277 EEPROM_PHY_ID = 0x06,
278 EEPROM_VENDOR_ID = 0x0c,
279 EEPROM_CONFIG_ASF = 0x0d,
280 EEPROM_DEVICE_ID = 0x23,
281 EEPROM_SMBUS_ADDR = 0x90,
282 } EEPROMOffset;
283
284 /* Bit values for EEPROM ID word. */
285 typedef enum {
286 EEPROM_ID_MDM = BIT(0), /* Modem */
287 EEPROM_ID_STB = BIT(1), /* Standby Enable */
288 EEPROM_ID_WMR = BIT(2), /* ??? */
289 EEPROM_ID_WOL = BIT(5), /* Wake on LAN */
290 EEPROM_ID_DPD = BIT(6), /* Deep Power Down */
291 EEPROM_ID_ALT = BIT(7), /* */
292 /* BITS(10, 8) device revision */
293 EEPROM_ID_BD = BIT(11), /* boot disable */
294 EEPROM_ID_ID = BIT(13), /* id bit */
295 /* BITS(15, 14) signature */
296 EEPROM_ID_VALID = BIT(14), /* signature for valid eeprom */
297 } eeprom_id_bit;
298
299 /* Default values for MDI (PHY) registers */
300 static const uint16_t eepro100_mdi_default[] = {
301 /* MDI Registers 0 - 6, 7 */
302 0x3000, 0x780d, 0x02a8, 0x0154, 0x05e1, 0x0000, 0x0000, 0x0000,
303 /* MDI Registers 8 - 15 */
304 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
305 /* MDI Registers 16 - 31 */
306 0x0003, 0x0000, 0x0001, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
307 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
308 };
309
310 /* Readonly mask for MDI (PHY) registers */
311 static const uint16_t eepro100_mdi_mask[] = {
312 0x0000, 0xffff, 0xffff, 0xffff, 0xc01f, 0xffff, 0xffff, 0x0000,
313 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
314 0x0fff, 0x0000, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
315 0xffff, 0xffff, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
316 };
317
318 /* Read a 16 bit little endian value from physical memory. */
319 static uint16_t e100_ldw_le_phys(target_phys_addr_t addr)
320 {
321 /* Load 16 bit (little endian) word from emulated hardware. */
322 uint16_t val;
323 cpu_physical_memory_read(addr, &val, sizeof(val));
324 return le16_to_cpu(val);
325 }
326
327 /* Read a 32 bit little endian value from physical memory. */
328 static uint32_t e100_ldl_le_phys(target_phys_addr_t addr)
329 {
330 /* Load 32 bit (little endian) word from emulated hardware. */
331 uint32_t val;
332 cpu_physical_memory_read(addr, &val, sizeof(val));
333 return le32_to_cpu(val);
334 }
335
336 /* Write a 16 bit little endian value to physical memory. */
337 static void e100_stw_le_phys(target_phys_addr_t addr, uint16_t val)
338 {
339 val = cpu_to_le16(val);
340 cpu_physical_memory_write(addr, &val, sizeof(val));
341 }
342
343 /* Write a 32 bit little endian value to physical memory. */
344 static void e100_stl_le_phys(target_phys_addr_t addr, uint32_t val)
345 {
346 val = cpu_to_le32(val);
347 cpu_physical_memory_write(addr, &val, sizeof(val));
348 }
349
350 #define POLYNOMIAL 0x04c11db6
351
352 /* From FreeBSD */
353 /* XXX: optimize */
354 static unsigned compute_mcast_idx(const uint8_t * ep)
355 {
356 uint32_t crc;
357 int carry, i, j;
358 uint8_t b;
359
360 crc = 0xffffffff;
361 for (i = 0; i < 6; i++) {
362 b = *ep++;
363 for (j = 0; j < 8; j++) {
364 carry = ((crc & 0x80000000L) ? 1 : 0) ^ (b & 0x01);
365 crc <<= 1;
366 b >>= 1;
367 if (carry) {
368 crc = ((crc ^ POLYNOMIAL) | carry);
369 }
370 }
371 }
372 return (crc & BITS(7, 2)) >> 2;
373 }
374
375 /* Read a 16 bit control/status (CSR) register. */
376 static uint16_t e100_read_reg2(EEPRO100State *s, E100RegisterOffset addr)
377 {
378 assert(!((uintptr_t)&s->mem[addr] & 1));
379 return le16_to_cpup((uint16_t *)&s->mem[addr]);
380 }
381
382 /* Read a 32 bit control/status (CSR) register. */
383 static uint32_t e100_read_reg4(EEPRO100State *s, E100RegisterOffset addr)
384 {
385 assert(!((uintptr_t)&s->mem[addr] & 3));
386 return le32_to_cpup((uint32_t *)&s->mem[addr]);
387 }
388
389 /* Write a 16 bit control/status (CSR) register. */
390 static void e100_write_reg2(EEPRO100State *s, E100RegisterOffset addr,
391 uint16_t val)
392 {
393 assert(!((uintptr_t)&s->mem[addr] & 1));
394 cpu_to_le16w((uint16_t *)&s->mem[addr], val);
395 }
396
397 /* Read a 32 bit control/status (CSR) register. */
398 static void e100_write_reg4(EEPRO100State *s, E100RegisterOffset addr,
399 uint32_t val)
400 {
401 assert(!((uintptr_t)&s->mem[addr] & 3));
402 cpu_to_le32w((uint32_t *)&s->mem[addr], val);
403 }
404
405 #if defined(DEBUG_EEPRO100)
406 static const char *nic_dump(const uint8_t * buf, unsigned size)
407 {
408 static char dump[3 * 16 + 1];
409 char *p = &dump[0];
410 if (size > 16) {
411 size = 16;
412 }
413 while (size-- > 0) {
414 p += sprintf(p, " %02x", *buf++);
415 }
416 return dump;
417 }
418 #endif /* DEBUG_EEPRO100 */
419
420 enum scb_stat_ack {
421 stat_ack_not_ours = 0x00,
422 stat_ack_sw_gen = 0x04,
423 stat_ack_rnr = 0x10,
424 stat_ack_cu_idle = 0x20,
425 stat_ack_frame_rx = 0x40,
426 stat_ack_cu_cmd_done = 0x80,
427 stat_ack_not_present = 0xFF,
428 stat_ack_rx = (stat_ack_sw_gen | stat_ack_rnr | stat_ack_frame_rx),
429 stat_ack_tx = (stat_ack_cu_idle | stat_ack_cu_cmd_done),
430 };
431
432 static void disable_interrupt(EEPRO100State * s)
433 {
434 if (s->int_stat) {
435 TRACE(INT, logout("interrupt disabled\n"));
436 qemu_irq_lower(s->dev.irq[0]);
437 s->int_stat = 0;
438 }
439 }
440
441 static void enable_interrupt(EEPRO100State * s)
442 {
443 if (!s->int_stat) {
444 TRACE(INT, logout("interrupt enabled\n"));
445 qemu_irq_raise(s->dev.irq[0]);
446 s->int_stat = 1;
447 }
448 }
449
450 static void eepro100_acknowledge(EEPRO100State * s)
451 {
452 s->scb_stat &= ~s->mem[SCBAck];
453 s->mem[SCBAck] = s->scb_stat;
454 if (s->scb_stat == 0) {
455 disable_interrupt(s);
456 }
457 }
458
459 static void eepro100_interrupt(EEPRO100State * s, uint8_t status)
460 {
461 uint8_t mask = ~s->mem[SCBIntmask];
462 s->mem[SCBAck] |= status;
463 status = s->scb_stat = s->mem[SCBAck];
464 status &= (mask | 0x0f);
465 #if 0
466 status &= (~s->mem[SCBIntmask] | 0x0xf);
467 #endif
468 if (status && (mask & 0x01)) {
469 /* SCB mask and SCB Bit M do not disable interrupt. */
470 enable_interrupt(s);
471 } else if (s->int_stat) {
472 disable_interrupt(s);
473 }
474 }
475
476 static void eepro100_cx_interrupt(EEPRO100State * s)
477 {
478 /* CU completed action command. */
479 /* Transmit not ok (82557 only, not in emulation). */
480 eepro100_interrupt(s, 0x80);
481 }
482
483 static void eepro100_cna_interrupt(EEPRO100State * s)
484 {
485 /* CU left the active state. */
486 eepro100_interrupt(s, 0x20);
487 }
488
489 static void eepro100_fr_interrupt(EEPRO100State * s)
490 {
491 /* RU received a complete frame. */
492 eepro100_interrupt(s, 0x40);
493 }
494
495 static void eepro100_rnr_interrupt(EEPRO100State * s)
496 {
497 /* RU is not ready. */
498 eepro100_interrupt(s, 0x10);
499 }
500
501 static void eepro100_mdi_interrupt(EEPRO100State * s)
502 {
503 /* MDI completed read or write cycle. */
504 eepro100_interrupt(s, 0x08);
505 }
506
507 static void eepro100_swi_interrupt(EEPRO100State * s)
508 {
509 /* Software has requested an interrupt. */
510 eepro100_interrupt(s, 0x04);
511 }
512
513 #if 0
514 static void eepro100_fcp_interrupt(EEPRO100State * s)
515 {
516 /* Flow control pause interrupt (82558 and later). */
517 eepro100_interrupt(s, 0x01);
518 }
519 #endif
520
521 static void e100_pci_reset(EEPRO100State * s, E100PCIDeviceInfo *e100_device)
522 {
523 uint32_t device = s->device;
524 uint8_t *pci_conf = s->dev.config;
525
526 TRACE(OTHER, logout("%p\n", s));
527
528 /* PCI Status */
529 pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM |
530 PCI_STATUS_FAST_BACK);
531 /* PCI Latency Timer */
532 pci_set_byte(pci_conf + PCI_LATENCY_TIMER, 0x20); /* latency timer = 32 clocks */
533 /* Capability Pointer is set by PCI framework. */
534 /* Interrupt Line */
535 /* Interrupt Pin */
536 pci_set_byte(pci_conf + PCI_INTERRUPT_PIN, 1); /* interrupt pin A */
537 /* Minimum Grant */
538 pci_set_byte(pci_conf + PCI_MIN_GNT, 0x08);
539 /* Maximum Latency */
540 pci_set_byte(pci_conf + PCI_MAX_LAT, 0x18);
541
542 s->stats_size = e100_device->stats_size;
543 s->has_extended_tcb_support = e100_device->has_extended_tcb_support;
544
545 switch (device) {
546 case i82550:
547 case i82551:
548 case i82557A:
549 case i82557B:
550 case i82557C:
551 case i82558A:
552 case i82558B:
553 case i82559A:
554 case i82559B:
555 case i82559ER:
556 case i82562:
557 case i82801:
558 case i82559C:
559 break;
560 default:
561 logout("Device %X is undefined!\n", device);
562 }
563
564 /* Standard TxCB. */
565 s->configuration[6] |= BIT(4);
566
567 /* Standard statistical counters. */
568 s->configuration[6] |= BIT(5);
569
570 if (s->stats_size == 80) {
571 /* TODO: check TCO Statistical Counters bit. Documentation not clear. */
572 if (s->configuration[6] & BIT(2)) {
573 /* TCO statistical counters. */
574 assert(s->configuration[6] & BIT(5));
575 } else {
576 if (s->configuration[6] & BIT(5)) {
577 /* No extended statistical counters, i82557 compatible. */
578 s->stats_size = 64;
579 } else {
580 /* i82558 compatible. */
581 s->stats_size = 76;
582 }
583 }
584 } else {
585 if (s->configuration[6] & BIT(5)) {
586 /* No extended statistical counters. */
587 s->stats_size = 64;
588 }
589 }
590 assert(s->stats_size > 0 && s->stats_size <= sizeof(s->statistics));
591
592 if (e100_device->power_management) {
593 /* Power Management Capabilities */
594 int cfg_offset = 0xdc;
595 int r = pci_add_capability(&s->dev, PCI_CAP_ID_PM,
596 cfg_offset, PCI_PM_SIZEOF);
597 assert(r >= 0);
598 pci_set_word(pci_conf + cfg_offset + PCI_PM_PMC, 0x7e21);
599 #if 0 /* TODO: replace dummy code for power management emulation. */
600 /* TODO: Power Management Control / Status. */
601 pci_set_word(pci_conf + cfg_offset + PCI_PM_CTRL, 0x0000);
602 /* TODO: Ethernet Power Consumption Registers (i82559 and later). */
603 pci_set_byte(pci_conf + cfg_offset + PCI_PM_PPB_EXTENSIONS, 0x0000);
604 #endif
605 }
606
607 #if EEPROM_SIZE > 0
608 if (device == i82557C || device == i82558B || device == i82559C) {
609 /*
610 TODO: get vendor id from EEPROM for i82557C or later.
611 TODO: get device id from EEPROM for i82557C or later.
612 TODO: status bit 4 can be disabled by EEPROM for i82558, i82559.
613 TODO: header type is determined by EEPROM for i82559.
614 TODO: get subsystem id from EEPROM for i82557C or later.
615 TODO: get subsystem vendor id from EEPROM for i82557C or later.
616 TODO: exp. rom baddr depends on a bit in EEPROM for i82558 or later.
617 TODO: capability pointer depends on EEPROM for i82558.
618 */
619 logout("Get device id and revision from EEPROM!!!\n");
620 }
621 #endif /* EEPROM_SIZE > 0 */
622 }
623
624 static void nic_selective_reset(EEPRO100State * s)
625 {
626 size_t i;
627 uint16_t *eeprom_contents = eeprom93xx_data(s->eeprom);
628 #if 0
629 eeprom93xx_reset(s->eeprom);
630 #endif
631 memcpy(eeprom_contents, s->conf.macaddr.a, 6);
632 eeprom_contents[EEPROM_ID] = EEPROM_ID_VALID;
633 if (s->device == i82557B || s->device == i82557C)
634 eeprom_contents[5] = 0x0100;
635 eeprom_contents[EEPROM_PHY_ID] = 1;
636 uint16_t sum = 0;
637 for (i = 0; i < EEPROM_SIZE - 1; i++) {
638 sum += eeprom_contents[i];
639 }
640 eeprom_contents[EEPROM_SIZE - 1] = 0xbaba - sum;
641 TRACE(EEPROM, logout("checksum=0x%04x\n", eeprom_contents[EEPROM_SIZE - 1]));
642
643 memset(s->mem, 0, sizeof(s->mem));
644 e100_write_reg4(s, SCBCtrlMDI, BIT(21));
645
646 assert(sizeof(s->mdimem) == sizeof(eepro100_mdi_default));
647 memcpy(&s->mdimem[0], &eepro100_mdi_default[0], sizeof(s->mdimem));
648 }
649
650 static void nic_reset(void *opaque)
651 {
652 EEPRO100State *s = opaque;
653 TRACE(OTHER, logout("%p\n", s));
654 /* TODO: Clearing of hash register for selective reset, too? */
655 memset(&s->mult[0], 0, sizeof(s->mult));
656 nic_selective_reset(s);
657 }
658
659 #if defined(DEBUG_EEPRO100)
660 static const char * const e100_reg[PCI_IO_SIZE / 4] = {
661 "Command/Status",
662 "General Pointer",
663 "Port",
664 "EEPROM/Flash Control",
665 "MDI Control",
666 "Receive DMA Byte Count",
667 "Flow Control",
668 "General Status/Control"
669 };
670
671 static char *regname(uint32_t addr)
672 {
673 static char buf[32];
674 if (addr < PCI_IO_SIZE) {
675 const char *r = e100_reg[addr / 4];
676 if (r != 0) {
677 snprintf(buf, sizeof(buf), "%s+%u", r, addr % 4);
678 } else {
679 snprintf(buf, sizeof(buf), "0x%02x", addr);
680 }
681 } else {
682 snprintf(buf, sizeof(buf), "??? 0x%08x", addr);
683 }
684 return buf;
685 }
686 #endif /* DEBUG_EEPRO100 */
687
688 /*****************************************************************************
689 *
690 * Command emulation.
691 *
692 ****************************************************************************/
693
694 #if 0
695 static uint16_t eepro100_read_command(EEPRO100State * s)
696 {
697 uint16_t val = 0xffff;
698 TRACE(OTHER, logout("val=0x%04x\n", val));
699 return val;
700 }
701 #endif
702
703 /* Commands that can be put in a command list entry. */
704 enum commands {
705 CmdNOp = 0,
706 CmdIASetup = 1,
707 CmdConfigure = 2,
708 CmdMulticastList = 3,
709 CmdTx = 4,
710 CmdTDR = 5, /* load microcode */
711 CmdDump = 6,
712 CmdDiagnose = 7,
713
714 /* And some extra flags: */
715 CmdSuspend = 0x4000, /* Suspend after completion. */
716 CmdIntr = 0x2000, /* Interrupt after completion. */
717 CmdTxFlex = 0x0008, /* Use "Flexible mode" for CmdTx command. */
718 };
719
720 static cu_state_t get_cu_state(EEPRO100State * s)
721 {
722 return ((s->mem[SCBStatus] & BITS(7, 6)) >> 6);
723 }
724
725 static void set_cu_state(EEPRO100State * s, cu_state_t state)
726 {
727 s->mem[SCBStatus] = (s->mem[SCBStatus] & ~BITS(7, 6)) + (state << 6);
728 }
729
730 static ru_state_t get_ru_state(EEPRO100State * s)
731 {
732 return ((s->mem[SCBStatus] & BITS(5, 2)) >> 2);
733 }
734
735 static void set_ru_state(EEPRO100State * s, ru_state_t state)
736 {
737 s->mem[SCBStatus] = (s->mem[SCBStatus] & ~BITS(5, 2)) + (state << 2);
738 }
739
740 static void dump_statistics(EEPRO100State * s)
741 {
742 /* Dump statistical data. Most data is never changed by the emulation
743 * and always 0, so we first just copy the whole block and then those
744 * values which really matter.
745 * Number of data should check configuration!!!
746 */
747 cpu_physical_memory_write(s->statsaddr, &s->statistics, s->stats_size);
748 e100_stl_le_phys(s->statsaddr + 0, s->statistics.tx_good_frames);
749 e100_stl_le_phys(s->statsaddr + 36, s->statistics.rx_good_frames);
750 e100_stl_le_phys(s->statsaddr + 48, s->statistics.rx_resource_errors);
751 e100_stl_le_phys(s->statsaddr + 60, s->statistics.rx_short_frame_errors);
752 #if 0
753 e100_stw_le_phys(s->statsaddr + 76, s->statistics.xmt_tco_frames);
754 e100_stw_le_phys(s->statsaddr + 78, s->statistics.rcv_tco_frames);
755 missing("CU dump statistical counters");
756 #endif
757 }
758
759 static void read_cb(EEPRO100State *s)
760 {
761 cpu_physical_memory_read(s->cb_address, &s->tx, sizeof(s->tx));
762 s->tx.status = le16_to_cpu(s->tx.status);
763 s->tx.command = le16_to_cpu(s->tx.command);
764 s->tx.link = le32_to_cpu(s->tx.link);
765 s->tx.tbd_array_addr = le32_to_cpu(s->tx.tbd_array_addr);
766 s->tx.tcb_bytes = le16_to_cpu(s->tx.tcb_bytes);
767 }
768
769 static void tx_command(EEPRO100State *s)
770 {
771 uint32_t tbd_array = le32_to_cpu(s->tx.tbd_array_addr);
772 uint16_t tcb_bytes = (le16_to_cpu(s->tx.tcb_bytes) & 0x3fff);
773 /* Sends larger than MAX_ETH_FRAME_SIZE are allowed, up to 2600 bytes. */
774 uint8_t buf[2600];
775 uint16_t size = 0;
776 uint32_t tbd_address = s->cb_address + 0x10;
777 TRACE(RXTX, logout
778 ("transmit, TBD array address 0x%08x, TCB byte count 0x%04x, TBD count %u\n",
779 tbd_array, tcb_bytes, s->tx.tbd_count));
780
781 if (tcb_bytes > 2600) {
782 logout("TCB byte count too large, using 2600\n");
783 tcb_bytes = 2600;
784 }
785 if (!((tcb_bytes > 0) || (tbd_array != 0xffffffff))) {
786 logout
787 ("illegal values of TBD array address and TCB byte count!\n");
788 }
789 assert(tcb_bytes <= sizeof(buf));
790 while (size < tcb_bytes) {
791 uint32_t tx_buffer_address = e100_ldl_le_phys(tbd_address);
792 uint16_t tx_buffer_size = e100_ldw_le_phys(tbd_address + 4);
793 #if 0
794 uint16_t tx_buffer_el = e100_ldw_le_phys(tbd_address + 6);
795 #endif
796 tbd_address += 8;
797 TRACE(RXTX, logout
798 ("TBD (simplified mode): buffer address 0x%08x, size 0x%04x\n",
799 tx_buffer_address, tx_buffer_size));
800 tx_buffer_size = MIN(tx_buffer_size, sizeof(buf) - size);
801 cpu_physical_memory_read(tx_buffer_address, &buf[size],
802 tx_buffer_size);
803 size += tx_buffer_size;
804 }
805 if (tbd_array == 0xffffffff) {
806 /* Simplified mode. Was already handled by code above. */
807 } else {
808 /* Flexible mode. */
809 uint8_t tbd_count = 0;
810 if (s->has_extended_tcb_support && !(s->configuration[6] & BIT(4))) {
811 /* Extended Flexible TCB. */
812 for (; tbd_count < 2; tbd_count++) {
813 uint32_t tx_buffer_address = e100_ldl_le_phys(tbd_address);
814 uint16_t tx_buffer_size = e100_ldw_le_phys(tbd_address + 4);
815 uint16_t tx_buffer_el = e100_ldw_le_phys(tbd_address + 6);
816 tbd_address += 8;
817 TRACE(RXTX, logout
818 ("TBD (extended flexible mode): buffer address 0x%08x, size 0x%04x\n",
819 tx_buffer_address, tx_buffer_size));
820 tx_buffer_size = MIN(tx_buffer_size, sizeof(buf) - size);
821 cpu_physical_memory_read(tx_buffer_address, &buf[size],
822 tx_buffer_size);
823 size += tx_buffer_size;
824 if (tx_buffer_el & 1) {
825 break;
826 }
827 }
828 }
829 tbd_address = tbd_array;
830 for (; tbd_count < s->tx.tbd_count; tbd_count++) {
831 uint32_t tx_buffer_address = e100_ldl_le_phys(tbd_address);
832 uint16_t tx_buffer_size = e100_ldw_le_phys(tbd_address + 4);
833 uint16_t tx_buffer_el = e100_ldw_le_phys(tbd_address + 6);
834 tbd_address += 8;
835 TRACE(RXTX, logout
836 ("TBD (flexible mode): buffer address 0x%08x, size 0x%04x\n",
837 tx_buffer_address, tx_buffer_size));
838 tx_buffer_size = MIN(tx_buffer_size, sizeof(buf) - size);
839 cpu_physical_memory_read(tx_buffer_address, &buf[size],
840 tx_buffer_size);
841 size += tx_buffer_size;
842 if (tx_buffer_el & 1) {
843 break;
844 }
845 }
846 }
847 TRACE(RXTX, logout("%p sending frame, len=%d,%s\n", s, size, nic_dump(buf, size)));
848 qemu_send_packet(&s->nic->nc, buf, size);
849 s->statistics.tx_good_frames++;
850 /* Transmit with bad status would raise an CX/TNO interrupt.
851 * (82557 only). Emulation never has bad status. */
852 #if 0
853 eepro100_cx_interrupt(s);
854 #endif
855 }
856
857 static void set_multicast_list(EEPRO100State *s)
858 {
859 uint16_t multicast_count = s->tx.tbd_array_addr & BITS(13, 0);
860 uint16_t i;
861 memset(&s->mult[0], 0, sizeof(s->mult));
862 TRACE(OTHER, logout("multicast list, multicast count = %u\n", multicast_count));
863 for (i = 0; i < multicast_count; i += 6) {
864 uint8_t multicast_addr[6];
865 cpu_physical_memory_read(s->cb_address + 10 + i, multicast_addr, 6);
866 TRACE(OTHER, logout("multicast entry %s\n", nic_dump(multicast_addr, 6)));
867 unsigned mcast_idx = compute_mcast_idx(multicast_addr);
868 assert(mcast_idx < 64);
869 s->mult[mcast_idx >> 3] |= (1 << (mcast_idx & 7));
870 }
871 }
872
873 static void action_command(EEPRO100State *s)
874 {
875 for (;;) {
876 bool bit_el;
877 bool bit_s;
878 bool bit_i;
879 bool bit_nc;
880 uint16_t ok_status = STATUS_OK;
881 s->cb_address = s->cu_base + s->cu_offset;
882 read_cb(s);
883 bit_el = ((s->tx.command & COMMAND_EL) != 0);
884 bit_s = ((s->tx.command & COMMAND_S) != 0);
885 bit_i = ((s->tx.command & COMMAND_I) != 0);
886 bit_nc = ((s->tx.command & COMMAND_NC) != 0);
887 #if 0
888 bool bit_sf = ((s->tx.command & COMMAND_SF) != 0);
889 #endif
890 s->cu_offset = s->tx.link;
891 TRACE(OTHER,
892 logout("val=(cu start), status=0x%04x, command=0x%04x, link=0x%08x\n",
893 s->tx.status, s->tx.command, s->tx.link));
894 switch (s->tx.command & COMMAND_CMD) {
895 case CmdNOp:
896 /* Do nothing. */
897 break;
898 case CmdIASetup:
899 cpu_physical_memory_read(s->cb_address + 8, &s->conf.macaddr.a[0], 6);
900 TRACE(OTHER, logout("macaddr: %s\n", nic_dump(&s->conf.macaddr.a[0], 6)));
901 break;
902 case CmdConfigure:
903 cpu_physical_memory_read(s->cb_address + 8, &s->configuration[0],
904 sizeof(s->configuration));
905 TRACE(OTHER, logout("configuration: %s\n",
906 nic_dump(&s->configuration[0], 16)));
907 TRACE(OTHER, logout("configuration: %s\n",
908 nic_dump(&s->configuration[16],
909 ARRAY_SIZE(s->configuration) - 16)));
910 if (s->configuration[20] & BIT(6)) {
911 TRACE(OTHER, logout("Multiple IA bit\n"));
912 }
913 break;
914 case CmdMulticastList:
915 set_multicast_list(s);
916 break;
917 case CmdTx:
918 if (bit_nc) {
919 missing("CmdTx: NC = 0");
920 ok_status = 0;
921 break;
922 }
923 tx_command(s);
924 break;
925 case CmdTDR:
926 TRACE(OTHER, logout("load microcode\n"));
927 /* Starting with offset 8, the command contains
928 * 64 dwords microcode which we just ignore here. */
929 break;
930 case CmdDiagnose:
931 TRACE(OTHER, logout("diagnose\n"));
932 /* Make sure error flag is not set. */
933 s->tx.status = 0;
934 break;
935 default:
936 missing("undefined command");
937 ok_status = 0;
938 break;
939 }
940 /* Write new status. */
941 e100_stw_le_phys(s->cb_address, s->tx.status | ok_status | STATUS_C);
942 if (bit_i) {
943 /* CU completed action. */
944 eepro100_cx_interrupt(s);
945 }
946 if (bit_el) {
947 /* CU becomes idle. Terminate command loop. */
948 set_cu_state(s, cu_idle);
949 eepro100_cna_interrupt(s);
950 break;
951 } else if (bit_s) {
952 /* CU becomes suspended. Terminate command loop. */
953 set_cu_state(s, cu_suspended);
954 eepro100_cna_interrupt(s);
955 break;
956 } else {
957 /* More entries in list. */
958 TRACE(OTHER, logout("CU list with at least one more entry\n"));
959 }
960 }
961 TRACE(OTHER, logout("CU list empty\n"));
962 /* List is empty. Now CU is idle or suspended. */
963 }
964
965 static void eepro100_cu_command(EEPRO100State * s, uint8_t val)
966 {
967 cu_state_t cu_state;
968 switch (val) {
969 case CU_NOP:
970 /* No operation. */
971 break;
972 case CU_START:
973 cu_state = get_cu_state(s);
974 if (cu_state != cu_idle && cu_state != cu_suspended) {
975 /* Intel documentation says that CU must be idle or suspended
976 * for the CU start command. */
977 logout("unexpected CU state is %u\n", cu_state);
978 }
979 set_cu_state(s, cu_active);
980 s->cu_offset = e100_read_reg4(s, SCBPointer);
981 action_command(s);
982 break;
983 case CU_RESUME:
984 if (get_cu_state(s) != cu_suspended) {
985 logout("bad CU resume from CU state %u\n", get_cu_state(s));
986 /* Workaround for bad Linux eepro100 driver which resumes
987 * from idle state. */
988 #if 0
989 missing("cu resume");
990 #endif
991 set_cu_state(s, cu_suspended);
992 }
993 if (get_cu_state(s) == cu_suspended) {
994 TRACE(OTHER, logout("CU resuming\n"));
995 set_cu_state(s, cu_active);
996 action_command(s);
997 }
998 break;
999 case CU_STATSADDR:
1000 /* Load dump counters address. */
1001 s->statsaddr = e100_read_reg4(s, SCBPointer);
1002 TRACE(OTHER, logout("val=0x%02x (status address)\n", val));
1003 break;
1004 case CU_SHOWSTATS:
1005 /* Dump statistical counters. */
1006 TRACE(OTHER, logout("val=0x%02x (dump stats)\n", val));
1007 dump_statistics(s);
1008 e100_stl_le_phys(s->statsaddr + s->stats_size, 0xa005);
1009 break;
1010 case CU_CMD_BASE:
1011 /* Load CU base. */
1012 TRACE(OTHER, logout("val=0x%02x (CU base address)\n", val));
1013 s->cu_base = e100_read_reg4(s, SCBPointer);
1014 break;
1015 case CU_DUMPSTATS:
1016 /* Dump and reset statistical counters. */
1017 TRACE(OTHER, logout("val=0x%02x (dump stats and reset)\n", val));
1018 dump_statistics(s);
1019 e100_stl_le_phys(s->statsaddr + s->stats_size, 0xa007);
1020 memset(&s->statistics, 0, sizeof(s->statistics));
1021 break;
1022 case CU_SRESUME:
1023 /* CU static resume. */
1024 missing("CU static resume");
1025 break;
1026 default:
1027 missing("Undefined CU command");
1028 }
1029 }
1030
1031 static void eepro100_ru_command(EEPRO100State * s, uint8_t val)
1032 {
1033 switch (val) {
1034 case RU_NOP:
1035 /* No operation. */
1036 break;
1037 case RX_START:
1038 /* RU start. */
1039 if (get_ru_state(s) != ru_idle) {
1040 logout("RU state is %u, should be %u\n", get_ru_state(s), ru_idle);
1041 #if 0
1042 assert(!"wrong RU state");
1043 #endif
1044 }
1045 set_ru_state(s, ru_ready);
1046 s->ru_offset = e100_read_reg4(s, SCBPointer);
1047 TRACE(OTHER, logout("val=0x%02x (rx start)\n", val));
1048 break;
1049 case RX_RESUME:
1050 /* Restart RU. */
1051 if (get_ru_state(s) != ru_suspended) {
1052 logout("RU state is %u, should be %u\n", get_ru_state(s),
1053 ru_suspended);
1054 #if 0
1055 assert(!"wrong RU state");
1056 #endif
1057 }
1058 set_ru_state(s, ru_ready);
1059 break;
1060 case RU_ABORT:
1061 /* RU abort. */
1062 if (get_ru_state(s) == ru_ready) {
1063 eepro100_rnr_interrupt(s);
1064 }
1065 set_ru_state(s, ru_idle);
1066 break;
1067 case RX_ADDR_LOAD:
1068 /* Load RU base. */
1069 TRACE(OTHER, logout("val=0x%02x (RU base address)\n", val));
1070 s->ru_base = e100_read_reg4(s, SCBPointer);
1071 break;
1072 default:
1073 logout("val=0x%02x (undefined RU command)\n", val);
1074 missing("Undefined SU command");
1075 }
1076 }
1077
1078 static void eepro100_write_command(EEPRO100State * s, uint8_t val)
1079 {
1080 eepro100_ru_command(s, val & 0x0f);
1081 eepro100_cu_command(s, val & 0xf0);
1082 if ((val) == 0) {
1083 TRACE(OTHER, logout("val=0x%02x\n", val));
1084 }
1085 /* Clear command byte after command was accepted. */
1086 s->mem[SCBCmd] = 0;
1087 }
1088
1089 /*****************************************************************************
1090 *
1091 * EEPROM emulation.
1092 *
1093 ****************************************************************************/
1094
1095 #define EEPROM_CS 0x02
1096 #define EEPROM_SK 0x01
1097 #define EEPROM_DI 0x04
1098 #define EEPROM_DO 0x08
1099
1100 static uint16_t eepro100_read_eeprom(EEPRO100State * s)
1101 {
1102 uint16_t val = e100_read_reg2(s, SCBeeprom);
1103 if (eeprom93xx_read(s->eeprom)) {
1104 val |= EEPROM_DO;
1105 } else {
1106 val &= ~EEPROM_DO;
1107 }
1108 TRACE(EEPROM, logout("val=0x%04x\n", val));
1109 return val;
1110 }
1111
1112 static void eepro100_write_eeprom(eeprom_t * eeprom, uint8_t val)
1113 {
1114 TRACE(EEPROM, logout("val=0x%02x\n", val));
1115
1116 /* mask unwritable bits */
1117 #if 0
1118 val = SET_MASKED(val, 0x31, eeprom->value);
1119 #endif
1120
1121 int eecs = ((val & EEPROM_CS) != 0);
1122 int eesk = ((val & EEPROM_SK) != 0);
1123 int eedi = ((val & EEPROM_DI) != 0);
1124 eeprom93xx_write(eeprom, eecs, eesk, eedi);
1125 }
1126
1127 /*****************************************************************************
1128 *
1129 * MDI emulation.
1130 *
1131 ****************************************************************************/
1132
1133 #if defined(DEBUG_EEPRO100)
1134 static const char * const mdi_op_name[] = {
1135 "opcode 0",
1136 "write",
1137 "read",
1138 "opcode 3"
1139 };
1140
1141 static const char * const mdi_reg_name[] = {
1142 "Control",
1143 "Status",
1144 "PHY Identification (Word 1)",
1145 "PHY Identification (Word 2)",
1146 "Auto-Negotiation Advertisement",
1147 "Auto-Negotiation Link Partner Ability",
1148 "Auto-Negotiation Expansion"
1149 };
1150
1151 static const char *reg2name(uint8_t reg)
1152 {
1153 static char buffer[10];
1154 const char *p = buffer;
1155 if (reg < ARRAY_SIZE(mdi_reg_name)) {
1156 p = mdi_reg_name[reg];
1157 } else {
1158 snprintf(buffer, sizeof(buffer), "reg=0x%02x", reg);
1159 }
1160 return p;
1161 }
1162 #endif /* DEBUG_EEPRO100 */
1163
1164 static uint32_t eepro100_read_mdi(EEPRO100State * s)
1165 {
1166 uint32_t val = e100_read_reg4(s, SCBCtrlMDI);
1167
1168 #ifdef DEBUG_EEPRO100
1169 uint8_t raiseint = (val & BIT(29)) >> 29;
1170 uint8_t opcode = (val & BITS(27, 26)) >> 26;
1171 uint8_t phy = (val & BITS(25, 21)) >> 21;
1172 uint8_t reg = (val & BITS(20, 16)) >> 16;
1173 uint16_t data = (val & BITS(15, 0));
1174 #endif
1175 /* Emulation takes no time to finish MDI transaction. */
1176 val |= BIT(28);
1177 TRACE(MDI, logout("val=0x%08x (int=%u, %s, phy=%u, %s, data=0x%04x\n",
1178 val, raiseint, mdi_op_name[opcode], phy,
1179 reg2name(reg), data));
1180 return val;
1181 }
1182
1183 static void eepro100_write_mdi(EEPRO100State *s)
1184 {
1185 uint32_t val = e100_read_reg4(s, SCBCtrlMDI);
1186 uint8_t raiseint = (val & BIT(29)) >> 29;
1187 uint8_t opcode = (val & BITS(27, 26)) >> 26;
1188 uint8_t phy = (val & BITS(25, 21)) >> 21;
1189 uint8_t reg = (val & BITS(20, 16)) >> 16;
1190 uint16_t data = (val & BITS(15, 0));
1191 TRACE(MDI, logout("val=0x%08x (int=%u, %s, phy=%u, %s, data=0x%04x\n",
1192 val, raiseint, mdi_op_name[opcode], phy, reg2name(reg), data));
1193 if (phy != 1) {
1194 /* Unsupported PHY address. */
1195 #if 0
1196 logout("phy must be 1 but is %u\n", phy);
1197 #endif
1198 data = 0;
1199 } else if (opcode != 1 && opcode != 2) {
1200 /* Unsupported opcode. */
1201 logout("opcode must be 1 or 2 but is %u\n", opcode);
1202 data = 0;
1203 } else if (reg > 6) {
1204 /* Unsupported register. */
1205 logout("register must be 0...6 but is %u\n", reg);
1206 data = 0;
1207 } else {
1208 TRACE(MDI, logout("val=0x%08x (int=%u, %s, phy=%u, %s, data=0x%04x\n",
1209 val, raiseint, mdi_op_name[opcode], phy,
1210 reg2name(reg), data));
1211 if (opcode == 1) {
1212 /* MDI write */
1213 switch (reg) {
1214 case 0: /* Control Register */
1215 if (data & 0x8000) {
1216 /* Reset status and control registers to default. */
1217 s->mdimem[0] = eepro100_mdi_default[0];
1218 s->mdimem[1] = eepro100_mdi_default[1];
1219 data = s->mdimem[reg];
1220 } else {
1221 /* Restart Auto Configuration = Normal Operation */
1222 data &= ~0x0200;
1223 }
1224 break;
1225 case 1: /* Status Register */
1226 missing("not writable");
1227 data = s->mdimem[reg];
1228 break;
1229 case 2: /* PHY Identification Register (Word 1) */
1230 case 3: /* PHY Identification Register (Word 2) */
1231 missing("not implemented");
1232 break;
1233 case 4: /* Auto-Negotiation Advertisement Register */
1234 case 5: /* Auto-Negotiation Link Partner Ability Register */
1235 break;
1236 case 6: /* Auto-Negotiation Expansion Register */
1237 default:
1238 missing("not implemented");
1239 }
1240 s->mdimem[reg] = data;
1241 } else if (opcode == 2) {
1242 /* MDI read */
1243 switch (reg) {
1244 case 0: /* Control Register */
1245 if (data & 0x8000) {
1246 /* Reset status and control registers to default. */
1247 s->mdimem[0] = eepro100_mdi_default[0];
1248 s->mdimem[1] = eepro100_mdi_default[1];
1249 }
1250 break;
1251 case 1: /* Status Register */
1252 s->mdimem[reg] |= 0x0020;
1253 break;
1254 case 2: /* PHY Identification Register (Word 1) */
1255 case 3: /* PHY Identification Register (Word 2) */
1256 case 4: /* Auto-Negotiation Advertisement Register */
1257 break;
1258 case 5: /* Auto-Negotiation Link Partner Ability Register */
1259 s->mdimem[reg] = 0x41fe;
1260 break;
1261 case 6: /* Auto-Negotiation Expansion Register */
1262 s->mdimem[reg] = 0x0001;
1263 break;
1264 }
1265 data = s->mdimem[reg];
1266 }
1267 /* Emulation takes no time to finish MDI transaction.
1268 * Set MDI bit in SCB status register. */
1269 s->mem[SCBAck] |= 0x08;
1270 val |= BIT(28);
1271 if (raiseint) {
1272 eepro100_mdi_interrupt(s);
1273 }
1274 }
1275 val = (val & 0xffff0000) + data;
1276 e100_write_reg4(s, SCBCtrlMDI, val);
1277 }
1278
1279 /*****************************************************************************
1280 *
1281 * Port emulation.
1282 *
1283 ****************************************************************************/
1284
1285 #define PORT_SOFTWARE_RESET 0
1286 #define PORT_SELFTEST 1
1287 #define PORT_SELECTIVE_RESET 2
1288 #define PORT_DUMP 3
1289 #define PORT_SELECTION_MASK 3
1290
1291 typedef struct {
1292 uint32_t st_sign; /* Self Test Signature */
1293 uint32_t st_result; /* Self Test Results */
1294 } eepro100_selftest_t;
1295
1296 static uint32_t eepro100_read_port(EEPRO100State * s)
1297 {
1298 return 0;
1299 }
1300
1301 static void eepro100_write_port(EEPRO100State *s)
1302 {
1303 uint32_t val = e100_read_reg4(s, SCBPort);
1304 uint32_t address = (val & ~PORT_SELECTION_MASK);
1305 uint8_t selection = (val & PORT_SELECTION_MASK);
1306 switch (selection) {
1307 case PORT_SOFTWARE_RESET:
1308 nic_reset(s);
1309 break;
1310 case PORT_SELFTEST:
1311 TRACE(OTHER, logout("selftest address=0x%08x\n", address));
1312 eepro100_selftest_t data;
1313 cpu_physical_memory_read(address, &data, sizeof(data));
1314 data.st_sign = 0xffffffff;
1315 data.st_result = 0;
1316 cpu_physical_memory_write(address, &data, sizeof(data));
1317 break;
1318 case PORT_SELECTIVE_RESET:
1319 TRACE(OTHER, logout("selective reset, selftest address=0x%08x\n", address));
1320 nic_selective_reset(s);
1321 break;
1322 default:
1323 logout("val=0x%08x\n", val);
1324 missing("unknown port selection");
1325 }
1326 }
1327
1328 /*****************************************************************************
1329 *
1330 * General hardware emulation.
1331 *
1332 ****************************************************************************/
1333
1334 static uint8_t eepro100_read1(EEPRO100State * s, uint32_t addr)
1335 {
1336 uint8_t val = 0;
1337 if (addr <= sizeof(s->mem) - sizeof(val)) {
1338 val = s->mem[addr];
1339 }
1340
1341 switch (addr) {
1342 case SCBStatus:
1343 case SCBAck:
1344 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1345 break;
1346 case SCBCmd:
1347 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1348 #if 0
1349 val = eepro100_read_command(s);
1350 #endif
1351 break;
1352 case SCBIntmask:
1353 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1354 break;
1355 case SCBPort + 3:
1356 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1357 break;
1358 case SCBeeprom:
1359 val = eepro100_read_eeprom(s);
1360 break;
1361 case SCBCtrlMDI:
1362 case SCBCtrlMDI + 1:
1363 case SCBCtrlMDI + 2:
1364 case SCBCtrlMDI + 3:
1365 val = (uint8_t)(eepro100_read_mdi(s) >> (8 * (addr & 3)));
1366 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1367 break;
1368 case SCBpmdr: /* Power Management Driver Register */
1369 val = 0;
1370 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1371 break;
1372 case SCBgctrl: /* General Control Register */
1373 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1374 break;
1375 case SCBgstat: /* General Status Register */
1376 /* 100 Mbps full duplex, valid link */
1377 val = 0x07;
1378 TRACE(OTHER, logout("addr=General Status val=%02x\n", val));
1379 break;
1380 default:
1381 logout("addr=%s val=0x%02x\n", regname(addr), val);
1382 missing("unknown byte read");
1383 }
1384 return val;
1385 }
1386
1387 static uint16_t eepro100_read2(EEPRO100State * s, uint32_t addr)
1388 {
1389 uint16_t val = 0;
1390 if (addr <= sizeof(s->mem) - sizeof(val)) {
1391 val = e100_read_reg2(s, addr);
1392 }
1393
1394 switch (addr) {
1395 case SCBStatus:
1396 case SCBCmd:
1397 TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val));
1398 break;
1399 case SCBeeprom:
1400 val = eepro100_read_eeprom(s);
1401 TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val));
1402 break;
1403 case SCBCtrlMDI:
1404 case SCBCtrlMDI + 2:
1405 val = (uint16_t)(eepro100_read_mdi(s) >> (8 * (addr & 3)));
1406 TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val));
1407 break;
1408 default:
1409 logout("addr=%s val=0x%04x\n", regname(addr), val);
1410 missing("unknown word read");
1411 }
1412 return val;
1413 }
1414
1415 static uint32_t eepro100_read4(EEPRO100State * s, uint32_t addr)
1416 {
1417 uint32_t val = 0;
1418 if (addr <= sizeof(s->mem) - sizeof(val)) {
1419 val = e100_read_reg4(s, addr);
1420 }
1421
1422 switch (addr) {
1423 case SCBStatus:
1424 TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val));
1425 break;
1426 case SCBPointer:
1427 TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val));
1428 break;
1429 case SCBPort:
1430 val = eepro100_read_port(s);
1431 TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val));
1432 break;
1433 case SCBflash:
1434 val = eepro100_read_eeprom(s);
1435 TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val));
1436 break;
1437 case SCBCtrlMDI:
1438 val = eepro100_read_mdi(s);
1439 break;
1440 default:
1441 logout("addr=%s val=0x%08x\n", regname(addr), val);
1442 missing("unknown longword read");
1443 }
1444 return val;
1445 }
1446
1447 static void eepro100_write1(EEPRO100State * s, uint32_t addr, uint8_t val)
1448 {
1449 /* SCBStatus is readonly. */
1450 if (addr > SCBStatus && addr <= sizeof(s->mem) - sizeof(val)) {
1451 s->mem[addr] = val;
1452 }
1453
1454 switch (addr) {
1455 case SCBStatus:
1456 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1457 break;
1458 case SCBAck:
1459 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1460 eepro100_acknowledge(s);
1461 break;
1462 case SCBCmd:
1463 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1464 eepro100_write_command(s, val);
1465 break;
1466 case SCBIntmask:
1467 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1468 if (val & BIT(1)) {
1469 eepro100_swi_interrupt(s);
1470 }
1471 eepro100_interrupt(s, 0);
1472 break;
1473 case SCBPointer:
1474 case SCBPointer + 1:
1475 case SCBPointer + 2:
1476 case SCBPointer + 3:
1477 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1478 break;
1479 case SCBPort:
1480 case SCBPort + 1:
1481 case SCBPort + 2:
1482 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1483 break;
1484 case SCBPort + 3:
1485 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1486 eepro100_write_port(s);
1487 break;
1488 case SCBFlow: /* does not exist on 82557 */
1489 case SCBFlow + 1:
1490 case SCBFlow + 2:
1491 case SCBpmdr: /* does not exist on 82557 */
1492 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1493 break;
1494 case SCBeeprom:
1495 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1496 eepro100_write_eeprom(s->eeprom, val);
1497 break;
1498 case SCBCtrlMDI:
1499 case SCBCtrlMDI + 1:
1500 case SCBCtrlMDI + 2:
1501 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1502 break;
1503 case SCBCtrlMDI + 3:
1504 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1505 eepro100_write_mdi(s);
1506 break;
1507 default:
1508 logout("addr=%s val=0x%02x\n", regname(addr), val);
1509 missing("unknown byte write");
1510 }
1511 }
1512
1513 static void eepro100_write2(EEPRO100State * s, uint32_t addr, uint16_t val)
1514 {
1515 /* SCBStatus is readonly. */
1516 if (addr > SCBStatus && addr <= sizeof(s->mem) - sizeof(val)) {
1517 e100_write_reg2(s, addr, val);
1518 }
1519
1520 switch (addr) {
1521 case SCBStatus:
1522 TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val));
1523 s->mem[SCBAck] = (val >> 8);
1524 eepro100_acknowledge(s);
1525 break;
1526 case SCBCmd:
1527 TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val));
1528 eepro100_write_command(s, val);
1529 eepro100_write1(s, SCBIntmask, val >> 8);
1530 break;
1531 case SCBPointer:
1532 case SCBPointer + 2:
1533 TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val));
1534 break;
1535 case SCBPort:
1536 TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val));
1537 break;
1538 case SCBPort + 2:
1539 TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val));
1540 eepro100_write_port(s);
1541 break;
1542 case SCBeeprom:
1543 TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val));
1544 eepro100_write_eeprom(s->eeprom, val);
1545 break;
1546 case SCBCtrlMDI:
1547 TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val));
1548 break;
1549 case SCBCtrlMDI + 2:
1550 TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val));
1551 eepro100_write_mdi(s);
1552 break;
1553 default:
1554 logout("addr=%s val=0x%04x\n", regname(addr), val);
1555 missing("unknown word write");
1556 }
1557 }
1558
1559 static void eepro100_write4(EEPRO100State * s, uint32_t addr, uint32_t val)
1560 {
1561 if (addr <= sizeof(s->mem) - sizeof(val)) {
1562 e100_write_reg4(s, addr, val);
1563 }
1564
1565 switch (addr) {
1566 case SCBPointer:
1567 TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val));
1568 break;
1569 case SCBPort:
1570 TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val));
1571 eepro100_write_port(s);
1572 break;
1573 case SCBflash:
1574 TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val));
1575 val = val >> 16;
1576 eepro100_write_eeprom(s->eeprom, val);
1577 break;
1578 case SCBCtrlMDI:
1579 TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val));
1580 eepro100_write_mdi(s);
1581 break;
1582 default:
1583 logout("addr=%s val=0x%08x\n", regname(addr), val);
1584 missing("unknown longword write");
1585 }
1586 }
1587
1588 static uint64_t eepro100_read(void *opaque, target_phys_addr_t addr,
1589 unsigned size)
1590 {
1591 EEPRO100State *s = opaque;
1592
1593 switch (size) {
1594 case 1: return eepro100_read1(s, addr);
1595 case 2: return eepro100_read2(s, addr);
1596 case 4: return eepro100_read4(s, addr);
1597 default: abort();
1598 }
1599 }
1600
1601 static void eepro100_write(void *opaque, target_phys_addr_t addr,
1602 uint64_t data, unsigned size)
1603 {
1604 EEPRO100State *s = opaque;
1605
1606 switch (size) {
1607 case 1: return eepro100_write1(s, addr, data);
1608 case 2: return eepro100_write2(s, addr, data);
1609 case 4: return eepro100_write4(s, addr, data);
1610 default: abort();
1611 }
1612 }
1613
1614 static const MemoryRegionOps eepro100_ops = {
1615 .read = eepro100_read,
1616 .write = eepro100_write,
1617 .endianness = DEVICE_LITTLE_ENDIAN,
1618 };
1619
1620 static int nic_can_receive(VLANClientState *nc)
1621 {
1622 EEPRO100State *s = DO_UPCAST(NICState, nc, nc)->opaque;
1623 TRACE(RXTX, logout("%p\n", s));
1624 return get_ru_state(s) == ru_ready;
1625 #if 0
1626 return !eepro100_buffer_full(s);
1627 #endif
1628 }
1629
1630 static ssize_t nic_receive(VLANClientState *nc, const uint8_t * buf, size_t size)
1631 {
1632 /* TODO:
1633 * - Magic packets should set bit 30 in power management driver register.
1634 * - Interesting packets should set bit 29 in power management driver register.
1635 */
1636 EEPRO100State *s = DO_UPCAST(NICState, nc, nc)->opaque;
1637 uint16_t rfd_status = 0xa000;
1638 #if defined(CONFIG_PAD_RECEIVED_FRAMES)
1639 uint8_t min_buf[60];
1640 #endif
1641 static const uint8_t broadcast_macaddr[6] =
1642 { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
1643
1644 #if defined(CONFIG_PAD_RECEIVED_FRAMES)
1645 /* Pad to minimum Ethernet frame length */
1646 if (size < sizeof(min_buf)) {
1647 memcpy(min_buf, buf, size);
1648 memset(&min_buf[size], 0, sizeof(min_buf) - size);
1649 buf = min_buf;
1650 size = sizeof(min_buf);
1651 }
1652 #endif
1653
1654 if (s->configuration[8] & 0x80) {
1655 /* CSMA is disabled. */
1656 logout("%p received while CSMA is disabled\n", s);
1657 return -1;
1658 #if !defined(CONFIG_PAD_RECEIVED_FRAMES)
1659 } else if (size < 64 && (s->configuration[7] & BIT(0))) {
1660 /* Short frame and configuration byte 7/0 (discard short receive) set:
1661 * Short frame is discarded */
1662 logout("%p received short frame (%zu byte)\n", s, size);
1663 s->statistics.rx_short_frame_errors++;
1664 return -1;
1665 #endif
1666 } else if ((size > MAX_ETH_FRAME_SIZE + 4) && !(s->configuration[18] & BIT(3))) {
1667 /* Long frame and configuration byte 18/3 (long receive ok) not set:
1668 * Long frames are discarded. */
1669 logout("%p received long frame (%zu byte), ignored\n", s, size);
1670 return -1;
1671 } else if (memcmp(buf, s->conf.macaddr.a, 6) == 0) { /* !!! */
1672 /* Frame matches individual address. */
1673 /* TODO: check configuration byte 15/4 (ignore U/L). */
1674 TRACE(RXTX, logout("%p received frame for me, len=%zu\n", s, size));
1675 } else if (memcmp(buf, broadcast_macaddr, 6) == 0) {
1676 /* Broadcast frame. */
1677 TRACE(RXTX, logout("%p received broadcast, len=%zu\n", s, size));
1678 rfd_status |= 0x0002;
1679 } else if (buf[0] & 0x01) {
1680 /* Multicast frame. */
1681 TRACE(RXTX, logout("%p received multicast, len=%zu,%s\n", s, size, nic_dump(buf, size)));
1682 if (s->configuration[21] & BIT(3)) {
1683 /* Multicast all bit is set, receive all multicast frames. */
1684 } else {
1685 unsigned mcast_idx = compute_mcast_idx(buf);
1686 assert(mcast_idx < 64);
1687 if (s->mult[mcast_idx >> 3] & (1 << (mcast_idx & 7))) {
1688 /* Multicast frame is allowed in hash table. */
1689 } else if (s->configuration[15] & BIT(0)) {
1690 /* Promiscuous: receive all. */
1691 rfd_status |= 0x0004;
1692 } else {
1693 TRACE(RXTX, logout("%p multicast ignored\n", s));
1694 return -1;
1695 }
1696 }
1697 /* TODO: Next not for promiscuous mode? */
1698 rfd_status |= 0x0002;
1699 } else if (s->configuration[15] & BIT(0)) {
1700 /* Promiscuous: receive all. */
1701 TRACE(RXTX, logout("%p received frame in promiscuous mode, len=%zu\n", s, size));
1702 rfd_status |= 0x0004;
1703 } else if (s->configuration[20] & BIT(6)) {
1704 /* Multiple IA bit set. */
1705 unsigned mcast_idx = compute_mcast_idx(buf);
1706 assert(mcast_idx < 64);
1707 if (s->mult[mcast_idx >> 3] & (1 << (mcast_idx & 7))) {
1708 TRACE(RXTX, logout("%p accepted, multiple IA bit set\n", s));
1709 } else {
1710 TRACE(RXTX, logout("%p frame ignored, multiple IA bit set\n", s));
1711 return -1;
1712 }
1713 } else {
1714 TRACE(RXTX, logout("%p received frame, ignored, len=%zu,%s\n", s, size,
1715 nic_dump(buf, size)));
1716 return size;
1717 }
1718
1719 if (get_ru_state(s) != ru_ready) {
1720 /* No resources available. */
1721 logout("no resources, state=%u\n", get_ru_state(s));
1722 /* TODO: RNR interrupt only at first failed frame? */
1723 eepro100_rnr_interrupt(s);
1724 s->statistics.rx_resource_errors++;
1725 #if 0
1726 assert(!"no resources");
1727 #endif
1728 return -1;
1729 }
1730 /* !!! */
1731 eepro100_rx_t rx;
1732 cpu_physical_memory_read(s->ru_base + s->ru_offset, &rx,
1733 sizeof(eepro100_rx_t));
1734 uint16_t rfd_command = le16_to_cpu(rx.command);
1735 uint16_t rfd_size = le16_to_cpu(rx.size);
1736
1737 if (size > rfd_size) {
1738 logout("Receive buffer (%" PRId16 " bytes) too small for data "
1739 "(%zu bytes); data truncated\n", rfd_size, size);
1740 size = rfd_size;
1741 }
1742 #if !defined(CONFIG_PAD_RECEIVED_FRAMES)
1743 if (size < 64) {
1744 rfd_status |= 0x0080;
1745 }
1746 #endif
1747 TRACE(OTHER, logout("command 0x%04x, link 0x%08x, addr 0x%08x, size %u\n",
1748 rfd_command, rx.link, rx.rx_buf_addr, rfd_size));
1749 e100_stw_le_phys(s->ru_base + s->ru_offset +
1750 offsetof(eepro100_rx_t, status), rfd_status);
1751 e100_stw_le_phys(s->ru_base + s->ru_offset +
1752 offsetof(eepro100_rx_t, count), size);
1753 /* Early receive interrupt not supported. */
1754 #if 0
1755 eepro100_er_interrupt(s);
1756 #endif
1757 /* Receive CRC Transfer not supported. */
1758 if (s->configuration[18] & BIT(2)) {
1759 missing("Receive CRC Transfer");
1760 return -1;
1761 }
1762 /* TODO: check stripping enable bit. */
1763 #if 0
1764 assert(!(s->configuration[17] & BIT(0)));
1765 #endif
1766 cpu_physical_memory_write(s->ru_base + s->ru_offset +
1767 sizeof(eepro100_rx_t), buf, size);
1768 s->statistics.rx_good_frames++;
1769 eepro100_fr_interrupt(s);
1770 s->ru_offset = le32_to_cpu(rx.link);
1771 if (rfd_command & COMMAND_EL) {
1772 /* EL bit is set, so this was the last frame. */
1773 logout("receive: Running out of frames\n");
1774 set_ru_state(s, ru_suspended);
1775 }
1776 if (rfd_command & COMMAND_S) {
1777 /* S bit is set. */
1778 set_ru_state(s, ru_suspended);
1779 }
1780 return size;
1781 }
1782
1783 static const VMStateDescription vmstate_eepro100 = {
1784 .version_id = 3,
1785 .minimum_version_id = 2,
1786 .minimum_version_id_old = 2,
1787 .fields = (VMStateField []) {
1788 VMSTATE_PCI_DEVICE(dev, EEPRO100State),
1789 VMSTATE_UNUSED(32),
1790 VMSTATE_BUFFER(mult, EEPRO100State),
1791 VMSTATE_BUFFER(mem, EEPRO100State),
1792 /* Save all members of struct between scb_stat and mem. */
1793 VMSTATE_UINT8(scb_stat, EEPRO100State),
1794 VMSTATE_UINT8(int_stat, EEPRO100State),
1795 VMSTATE_UNUSED(3*4),
1796 VMSTATE_MACADDR(conf.macaddr, EEPRO100State),
1797 VMSTATE_UNUSED(19*4),
1798 VMSTATE_UINT16_ARRAY(mdimem, EEPRO100State, 32),
1799 /* The eeprom should be saved and restored by its own routines. */
1800 VMSTATE_UINT32(device, EEPRO100State),
1801 /* TODO check device. */
1802 VMSTATE_UINT32(cu_base, EEPRO100State),
1803 VMSTATE_UINT32(cu_offset, EEPRO100State),
1804 VMSTATE_UINT32(ru_base, EEPRO100State),
1805 VMSTATE_UINT32(ru_offset, EEPRO100State),
1806 VMSTATE_UINT32(statsaddr, EEPRO100State),
1807 /* Save eepro100_stats_t statistics. */
1808 VMSTATE_UINT32(statistics.tx_good_frames, EEPRO100State),
1809 VMSTATE_UINT32(statistics.tx_max_collisions, EEPRO100State),
1810 VMSTATE_UINT32(statistics.tx_late_collisions, EEPRO100State),
1811 VMSTATE_UINT32(statistics.tx_underruns, EEPRO100State),
1812 VMSTATE_UINT32(statistics.tx_lost_crs, EEPRO100State),
1813 VMSTATE_UINT32(statistics.tx_deferred, EEPRO100State),
1814 VMSTATE_UINT32(statistics.tx_single_collisions, EEPRO100State),
1815 VMSTATE_UINT32(statistics.tx_multiple_collisions, EEPRO100State),
1816 VMSTATE_UINT32(statistics.tx_total_collisions, EEPRO100State),
1817 VMSTATE_UINT32(statistics.rx_good_frames, EEPRO100State),
1818 VMSTATE_UINT32(statistics.rx_crc_errors, EEPRO100State),
1819 VMSTATE_UINT32(statistics.rx_alignment_errors, EEPRO100State),
1820 VMSTATE_UINT32(statistics.rx_resource_errors, EEPRO100State),
1821 VMSTATE_UINT32(statistics.rx_overrun_errors, EEPRO100State),
1822 VMSTATE_UINT32(statistics.rx_cdt_errors, EEPRO100State),
1823 VMSTATE_UINT32(statistics.rx_short_frame_errors, EEPRO100State),
1824 VMSTATE_UINT32(statistics.fc_xmt_pause, EEPRO100State),
1825 VMSTATE_UINT32(statistics.fc_rcv_pause, EEPRO100State),
1826 VMSTATE_UINT32(statistics.fc_rcv_unsupported, EEPRO100State),
1827 VMSTATE_UINT16(statistics.xmt_tco_frames, EEPRO100State),
1828 VMSTATE_UINT16(statistics.rcv_tco_frames, EEPRO100State),
1829 /* Configuration bytes. */
1830 VMSTATE_BUFFER(configuration, EEPRO100State),
1831 VMSTATE_END_OF_LIST()
1832 }
1833 };
1834
1835 static void nic_cleanup(VLANClientState *nc)
1836 {
1837 EEPRO100State *s = DO_UPCAST(NICState, nc, nc)->opaque;
1838
1839 s->nic = NULL;
1840 }
1841
1842 static int pci_nic_uninit(PCIDevice *pci_dev)
1843 {
1844 EEPRO100State *s = DO_UPCAST(EEPRO100State, dev, pci_dev);
1845
1846 memory_region_destroy(&s->mmio_bar);
1847 memory_region_destroy(&s->io_bar);
1848 memory_region_destroy(&s->flash_bar);
1849 vmstate_unregister(&pci_dev->qdev, s->vmstate, s);
1850 eeprom93xx_free(&pci_dev->qdev, s->eeprom);
1851 qemu_del_vlan_client(&s->nic->nc);
1852 return 0;
1853 }
1854
1855 static NetClientInfo net_eepro100_info = {
1856 .type = NET_CLIENT_TYPE_NIC,
1857 .size = sizeof(NICState),
1858 .can_receive = nic_can_receive,
1859 .receive = nic_receive,
1860 .cleanup = nic_cleanup,
1861 };
1862
1863 static int e100_nic_init(PCIDevice *pci_dev)
1864 {
1865 EEPRO100State *s = DO_UPCAST(EEPRO100State, dev, pci_dev);
1866 E100PCIDeviceInfo *e100_device = DO_UPCAST(E100PCIDeviceInfo, pci.qdev,
1867 pci_dev->qdev.info);
1868
1869 TRACE(OTHER, logout("\n"));
1870
1871 s->device = e100_device->device;
1872
1873 e100_pci_reset(s, e100_device);
1874
1875 /* Add 64 * 2 EEPROM. i82557 and i82558 support a 64 word EEPROM,
1876 * i82559 and later support 64 or 256 word EEPROM. */
1877 s->eeprom = eeprom93xx_new(&pci_dev->qdev, EEPROM_SIZE);
1878
1879 /* Handler for memory-mapped I/O */
1880 memory_region_init_io(&s->mmio_bar, &eepro100_ops, s, "eepro100-mmio",
1881 PCI_MEM_SIZE);
1882 pci_register_bar(&s->dev, 0, PCI_BASE_ADDRESS_MEM_PREFETCH, &s->mmio_bar);
1883 memory_region_init_io(&s->io_bar, &eepro100_ops, s, "eepro100-io",
1884 PCI_IO_SIZE);
1885 pci_register_bar(&s->dev, 1, PCI_BASE_ADDRESS_SPACE_IO, &s->io_bar);
1886 /* FIXME: flash aliases to mmio?! */
1887 memory_region_init_io(&s->flash_bar, &eepro100_ops, s, "eepro100-flash",
1888 PCI_FLASH_SIZE);
1889 pci_register_bar(&s->dev, 2, 0, &s->flash_bar);
1890
1891 qemu_macaddr_default_if_unset(&s->conf.macaddr);
1892 logout("macaddr: %s\n", nic_dump(&s->conf.macaddr.a[0], 6));
1893
1894 nic_reset(s);
1895
1896 s->nic = qemu_new_nic(&net_eepro100_info, &s->conf,
1897 pci_dev->qdev.info->name, pci_dev->qdev.id, s);
1898
1899 qemu_format_nic_info_str(&s->nic->nc, s->conf.macaddr.a);
1900 TRACE(OTHER, logout("%s\n", s->nic->nc.info_str));
1901
1902 qemu_register_reset(nic_reset, s);
1903
1904 s->vmstate = qemu_malloc(sizeof(vmstate_eepro100));
1905 memcpy(s->vmstate, &vmstate_eepro100, sizeof(vmstate_eepro100));
1906 s->vmstate->name = s->nic->nc.model;
1907 vmstate_register(&pci_dev->qdev, -1, s->vmstate, s);
1908
1909 add_boot_device_path(s->conf.bootindex, &pci_dev->qdev, "/ethernet-phy@0");
1910
1911 return 0;
1912 }
1913
1914 static E100PCIDeviceInfo e100_devices[] = {
1915 {
1916 .pci.qdev.name = "i82550",
1917 .pci.qdev.desc = "Intel i82550 Ethernet",
1918 .device = i82550,
1919 /* TODO: check device id. */
1920 .pci.device_id = PCI_DEVICE_ID_INTEL_82551IT,
1921 /* Revision ID: 0x0c, 0x0d, 0x0e. */
1922 .pci.revision = 0x0e,
1923 /* TODO: check size of statistical counters. */
1924 .stats_size = 80,
1925 /* TODO: check extended tcb support. */
1926 .has_extended_tcb_support = true,
1927 .power_management = true,
1928 },{
1929 .pci.qdev.name = "i82551",
1930 .pci.qdev.desc = "Intel i82551 Ethernet",
1931 .device = i82551,
1932 .pci.device_id = PCI_DEVICE_ID_INTEL_82551IT,
1933 /* Revision ID: 0x0f, 0x10. */
1934 .pci.revision = 0x0f,
1935 /* TODO: check size of statistical counters. */
1936 .stats_size = 80,
1937 .has_extended_tcb_support = true,
1938 .power_management = true,
1939 },{
1940 .pci.qdev.name = "i82557a",
1941 .pci.qdev.desc = "Intel i82557A Ethernet",
1942 .device = i82557A,
1943 .pci.device_id = PCI_DEVICE_ID_INTEL_82557,
1944 .pci.revision = 0x01,
1945 .power_management = false,
1946 },{
1947 .pci.qdev.name = "i82557b",
1948 .pci.qdev.desc = "Intel i82557B Ethernet",
1949 .device = i82557B,
1950 .pci.device_id = PCI_DEVICE_ID_INTEL_82557,
1951 .pci.revision = 0x02,
1952 .power_management = false,
1953 },{
1954 .pci.qdev.name = "i82557c",
1955 .pci.qdev.desc = "Intel i82557C Ethernet",
1956 .device = i82557C,
1957 .pci.device_id = PCI_DEVICE_ID_INTEL_82557,
1958 .pci.revision = 0x03,
1959 .power_management = false,
1960 },{
1961 .pci.qdev.name = "i82558a",
1962 .pci.qdev.desc = "Intel i82558A Ethernet",
1963 .device = i82558A,
1964 .pci.device_id = PCI_DEVICE_ID_INTEL_82557,
1965 .pci.revision = 0x04,
1966 .stats_size = 76,
1967 .has_extended_tcb_support = true,
1968 .power_management = true,
1969 },{
1970 .pci.qdev.name = "i82558b",
1971 .pci.qdev.desc = "Intel i82558B Ethernet",
1972 .device = i82558B,
1973 .pci.device_id = PCI_DEVICE_ID_INTEL_82557,
1974 .pci.revision = 0x05,
1975 .stats_size = 76,
1976 .has_extended_tcb_support = true,
1977 .power_management = true,
1978 },{
1979 .pci.qdev.name = "i82559a",
1980 .pci.qdev.desc = "Intel i82559A Ethernet",
1981 .device = i82559A,
1982 .pci.device_id = PCI_DEVICE_ID_INTEL_82557,
1983 .pci.revision = 0x06,
1984 .stats_size = 80,
1985 .has_extended_tcb_support = true,
1986 .power_management = true,
1987 },{
1988 .pci.qdev.name = "i82559b",
1989 .pci.qdev.desc = "Intel i82559B Ethernet",
1990 .device = i82559B,
1991 .pci.device_id = PCI_DEVICE_ID_INTEL_82557,
1992 .pci.revision = 0x07,
1993 .stats_size = 80,
1994 .has_extended_tcb_support = true,
1995 .power_management = true,
1996 },{
1997 .pci.qdev.name = "i82559c",
1998 .pci.qdev.desc = "Intel i82559C Ethernet",
1999 .device = i82559C,
2000 .pci.device_id = PCI_DEVICE_ID_INTEL_82557,
2001 #if 0
2002 .pci.revision = 0x08,
2003 #endif
2004 /* TODO: Windows wants revision id 0x0c. */
2005 .pci.revision = 0x0c,
2006 #if EEPROM_SIZE > 0
2007 .pci.subsystem_vendor_id = PCI_VENDOR_ID_INTEL,
2008 .pci.subsystem_id = 0x0040,
2009 #endif
2010 .stats_size = 80,
2011 .has_extended_tcb_support = true,
2012 .power_management = true,
2013 },{
2014 .pci.qdev.name = "i82559er",
2015 .pci.qdev.desc = "Intel i82559ER Ethernet",
2016 .device = i82559ER,
2017 .pci.device_id = PCI_DEVICE_ID_INTEL_82551IT,
2018 .pci.revision = 0x09,
2019 .stats_size = 80,
2020 .has_extended_tcb_support = true,
2021 .power_management = true,
2022 },{
2023 .pci.qdev.name = "i82562",
2024 .pci.qdev.desc = "Intel i82562 Ethernet",
2025 .device = i82562,
2026 /* TODO: check device id. */
2027 .pci.device_id = PCI_DEVICE_ID_INTEL_82551IT,
2028 /* TODO: wrong revision id. */
2029 .pci.revision = 0x0e,
2030 .stats_size = 80,
2031 .has_extended_tcb_support = true,
2032 .power_management = true,
2033 },{
2034 /* Toshiba Tecra 8200. */
2035 .pci.qdev.name = "i82801",
2036 .pci.qdev.desc = "Intel i82801 Ethernet",
2037 .device = i82801,
2038 .pci.device_id = 0x2449,
2039 .pci.revision = 0x03,
2040 .stats_size = 80,
2041 .has_extended_tcb_support = true,
2042 .power_management = true,
2043 }
2044 };
2045
2046 static Property e100_properties[] = {
2047 DEFINE_NIC_PROPERTIES(EEPRO100State, conf),
2048 DEFINE_PROP_END_OF_LIST(),
2049 };
2050
2051 static void eepro100_register_devices(void)
2052 {
2053 size_t i;
2054 for (i = 0; i < ARRAY_SIZE(e100_devices); i++) {
2055 PCIDeviceInfo *pci_dev = &e100_devices[i].pci;
2056 /* We use the same rom file for all device ids.
2057 QEMU fixes the device id during rom load. */
2058 pci_dev->vendor_id = PCI_VENDOR_ID_INTEL;
2059 pci_dev->class_id = PCI_CLASS_NETWORK_ETHERNET;
2060 pci_dev->romfile = "pxe-eepro100.rom";
2061 pci_dev->init = e100_nic_init;
2062 pci_dev->exit = pci_nic_uninit;
2063 pci_dev->qdev.props = e100_properties;
2064 pci_dev->qdev.size = sizeof(EEPRO100State);
2065 pci_qdev_register(pci_dev);
2066 }
2067 }
2068
2069 device_init(eepro100_register_devices)
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