hw/escc.c

   1 /*
   2  * QEMU ESCC (Z8030/Z8530/Z85C30/SCC/ESCC) serial port emulation
   3  *
   4  * Copyright (c) 2003-2005 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #include "hw.h"
  26 #include "sysbus.h"
  27 #include "escc.h"
  28 #include "qemu-char.h"
  29 #include "console.h"
  30
  31 /* debug serial */
  32 //#define DEBUG_SERIAL
  33
  34 /* debug keyboard */
  35 //#define DEBUG_KBD
  36
  37 /* debug mouse */
  38 //#define DEBUG_MOUSE
  39
  40 /*
  41  * Chipset docs:
  42  * "Z80C30/Z85C30/Z80230/Z85230/Z85233 SCC/ESCC User Manual",
  43  * http://www.zilog.com/docs/serial/scc_escc_um.pdf
  44  *
  45  * On Sparc32 this is the serial port, mouse and keyboard part of chip STP2001
  46  * (Slave I/O), also produced as NCR89C105. See
  47  * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C105.txt
  48  *
  49  * The serial ports implement full AMD AM8530 or Zilog Z8530 chips,
  50  * mouse and keyboard ports don't implement all functions and they are
  51  * only asynchronous. There is no DMA.
  52  *
  53  * Z85C30 is also used on PowerMacs. There are some small differences
  54  * between Sparc version (sunzilog) and PowerMac (pmac):
  55  *  Offset between control and data registers
  56  *  There is some kind of lockup bug, but we can ignore it
  57  *  CTS is inverted
  58  *  DMA on pmac using DBDMA chip
  59  *  pmac can do IRDA and faster rates, sunzilog can only do 38400
  60  *  pmac baud rate generator clock is 3.6864 MHz, sunzilog 4.9152 MHz
  61  */
  62
  63 /*
  64  * Modifications:
  65  *  2006-Aug-10  Igor Kovalenko :   Renamed KBDQueue to SERIOQueue, implemented
  66  *                                  serial mouse queue.
  67  *                                  Implemented serial mouse protocol.
  68  *
  69  *  2010-May-23  Artyom Tarasenko:  Reworked IUS logic
  70  */
  71
  72 #ifdef DEBUG_SERIAL
  73 #define SER_DPRINTF(fmt, ...)                                   \
  74     do { printf("SER: " fmt , ## __VA_ARGS__); } while (0)
  75 #else
  76 #define SER_DPRINTF(fmt, ...)
  77 #endif
  78 #ifdef DEBUG_KBD
  79 #define KBD_DPRINTF(fmt, ...)                                   \
  80     do { printf("KBD: " fmt , ## __VA_ARGS__); } while (0)
  81 #else
  82 #define KBD_DPRINTF(fmt, ...)
  83 #endif
  84 #ifdef DEBUG_MOUSE
  85 #define MS_DPRINTF(fmt, ...)                                    \
  86     do { printf("MSC: " fmt , ## __VA_ARGS__); } while (0)
  87 #else
  88 #define MS_DPRINTF(fmt, ...)
  89 #endif
  90
  91 typedef enum {
  92     chn_a, chn_b,
  93 } ChnID;
  94
  95 #define CHN_C(s) ((s)->chn == chn_b? 'b' : 'a')
  96
  97 typedef enum {
  98     ser, kbd, mouse,
  99 } ChnType;
 100
 101 #define SERIO_QUEUE_SIZE 256
 102
 103 typedef struct {
 104     uint8_t data[SERIO_QUEUE_SIZE];
 105     int rptr, wptr, count;
 106 } SERIOQueue;
 107
 108 #define SERIAL_REGS 16
 109 typedef struct ChannelState {
 110     qemu_irq irq;
 111     uint32_t reg;
 112     uint32_t rxint, txint, rxint_under_svc, txint_under_svc;
 113     ChnID chn; // this channel, A (base+4) or B (base+0)
 114     ChnType type;
 115     struct ChannelState *otherchn;
 116     uint8_t rx, tx, wregs[SERIAL_REGS], rregs[SERIAL_REGS];
 117     SERIOQueue queue;
 118     CharDriverState *chr;
 119     int e0_mode, led_mode, caps_lock_mode, num_lock_mode;
 120     int disabled;
 121     int clock;
 122     uint32_t vmstate_dummy;
 123 } ChannelState;
 124
 125 struct SerialState {
 126     SysBusDevice busdev;
 127     struct ChannelState chn[2];
 128     uint32_t it_shift;
 129     MemoryRegion mmio;
 130     uint32_t disabled;
 131     uint32_t frequency;
 132 };
 133
 134 #define SERIAL_CTRL 0
 135 #define SERIAL_DATA 1
 136
 137 #define W_CMD     0
 138 #define CMD_PTR_MASK   0x07
 139 #define CMD_CMD_MASK   0x38
 140 #define CMD_HI         0x08
 141 #define CMD_CLR_TXINT  0x28
 142 #define CMD_CLR_IUS    0x38
 143 #define W_INTR    1
 144 #define INTR_INTALL    0x01
 145 #define INTR_TXINT     0x02
 146 #define INTR_RXMODEMSK 0x18
 147 #define INTR_RXINT1ST  0x08
 148 #define INTR_RXINTALL  0x10
 149 #define W_IVEC    2
 150 #define W_RXCTRL  3
 151 #define RXCTRL_RXEN    0x01
 152 #define W_TXCTRL1 4
 153 #define TXCTRL1_PAREN  0x01
 154 #define TXCTRL1_PAREV  0x02
 155 #define TXCTRL1_1STOP  0x04
 156 #define TXCTRL1_1HSTOP 0x08
 157 #define TXCTRL1_2STOP  0x0c
 158 #define TXCTRL1_STPMSK 0x0c
 159 #define TXCTRL1_CLK1X  0x00
 160 #define TXCTRL1_CLK16X 0x40
 161 #define TXCTRL1_CLK32X 0x80
 162 #define TXCTRL1_CLK64X 0xc0
 163 #define TXCTRL1_CLKMSK 0xc0
 164 #define W_TXCTRL2 5
 165 #define TXCTRL2_TXEN   0x08
 166 #define TXCTRL2_BITMSK 0x60
 167 #define TXCTRL2_5BITS  0x00
 168 #define TXCTRL2_7BITS  0x20
 169 #define TXCTRL2_6BITS  0x40
 170 #define TXCTRL2_8BITS  0x60
 171 #define W_SYNC1   6
 172 #define W_SYNC2   7
 173 #define W_TXBUF   8
 174 #define W_MINTR   9
 175 #define MINTR_STATUSHI 0x10
 176 #define MINTR_RST_MASK 0xc0
 177 #define MINTR_RST_B    0x40
 178 #define MINTR_RST_A    0x80
 179 #define MINTR_RST_ALL  0xc0
 180 #define W_MISC1  10
 181 #define W_CLOCK  11
 182 #define CLOCK_TRXC     0x08
 183 #define W_BRGLO  12
 184 #define W_BRGHI  13
 185 #define W_MISC2  14
 186 #define MISC2_PLLDIS   0x30
 187 #define W_EXTINT 15
 188 #define EXTINT_DCD     0x08
 189 #define EXTINT_SYNCINT 0x10
 190 #define EXTINT_CTSINT  0x20
 191 #define EXTINT_TXUNDRN 0x40
 192 #define EXTINT_BRKINT  0x80
 193
 194 #define R_STATUS  0
 195 #define STATUS_RXAV    0x01
 196 #define STATUS_ZERO    0x02
 197 #define STATUS_TXEMPTY 0x04
 198 #define STATUS_DCD     0x08
 199 #define STATUS_SYNC    0x10
 200 #define STATUS_CTS     0x20
 201 #define STATUS_TXUNDRN 0x40
 202 #define STATUS_BRK     0x80
 203 #define R_SPEC    1
 204 #define SPEC_ALLSENT   0x01
 205 #define SPEC_BITS8     0x06
 206 #define R_IVEC    2
 207 #define IVEC_TXINTB    0x00
 208 #define IVEC_LONOINT   0x06
 209 #define IVEC_LORXINTA  0x0c
 210 #define IVEC_LORXINTB  0x04
 211 #define IVEC_LOTXINTA  0x08
 212 #define IVEC_HINOINT   0x60
 213 #define IVEC_HIRXINTA  0x30
 214 #define IVEC_HIRXINTB  0x20
 215 #define IVEC_HITXINTA  0x10
 216 #define R_INTR    3
 217 #define INTR_EXTINTB   0x01
 218 #define INTR_TXINTB    0x02
 219 #define INTR_RXINTB    0x04
 220 #define INTR_EXTINTA   0x08
 221 #define INTR_TXINTA    0x10
 222 #define INTR_RXINTA    0x20
 223 #define R_IPEN    4
 224 #define R_TXCTRL1 5
 225 #define R_TXCTRL2 6
 226 #define R_BC      7
 227 #define R_RXBUF   8
 228 #define R_RXCTRL  9
 229 #define R_MISC   10
 230 #define R_MISC1  11
 231 #define R_BRGLO  12
 232 #define R_BRGHI  13
 233 #define R_MISC1I 14
 234 #define R_EXTINT 15
 235
 236 static void handle_kbd_command(ChannelState *s, int val);
 237 static void serial_receive_byte(ChannelState *s, int ch);
 238 static void serial_update_handlers(ChannelState *s);
 239
 240 static void clear_queue(void *opaque)
 241 {
 242     ChannelState *s = opaque;
 243     SERIOQueue *q = &s->queue;
 244     q->rptr = q->wptr = q->count = 0;
 245 }
 246
 247 static void put_queue(void *opaque, int b)
 248 {
 249     ChannelState *s = opaque;
 250     SERIOQueue *q = &s->queue;
 251
 252     SER_DPRINTF("channel %c put: 0x%02x\n", CHN_C(s), b);
 253     if (q->count >= SERIO_QUEUE_SIZE)
 254         return;
 255     q->data[q->wptr] = b;
 256     if (++q->wptr == SERIO_QUEUE_SIZE)
 257         q->wptr = 0;
 258     q->count++;
 259     serial_receive_byte(s, 0);
 260 }
 261
 262 static uint32_t get_queue(void *opaque)
 263 {
 264     ChannelState *s = opaque;
 265     SERIOQueue *q = &s->queue;
 266     int val;
 267
 268     if (q->count == 0) {
 269         return 0;
 270     } else {
 271         val = q->data[q->rptr];
 272         if (++q->rptr == SERIO_QUEUE_SIZE)
 273             q->rptr = 0;
 274         q->count--;
 275     }
 276     SER_DPRINTF("channel %c get 0x%02x\n", CHN_C(s), val);
 277     if (q->count > 0)
 278         serial_receive_byte(s, 0);
 279     return val;
 280 }
 281
 282 static int escc_update_irq_chn(ChannelState *s)
 283 {
 284     if ((((s->wregs[W_INTR] & INTR_TXINT) && (s->txint == 1)) ||
 285          // tx ints enabled, pending
 286          ((((s->wregs[W_INTR] & INTR_RXMODEMSK) == INTR_RXINT1ST) ||
 287            ((s->wregs[W_INTR] & INTR_RXMODEMSK) == INTR_RXINTALL)) &&
 288           s->rxint == 1) || // rx ints enabled, pending
 289          ((s->wregs[W_EXTINT] & EXTINT_BRKINT) &&
 290           (s->rregs[R_STATUS] & STATUS_BRK)))) { // break int e&p
 291         return 1;
 292     }
 293     return 0;
 294 }
 295
 296 static void escc_update_irq(ChannelState *s)
 297 {
 298     int irq;
 299
 300     irq = escc_update_irq_chn(s);
 301     irq |= escc_update_irq_chn(s->otherchn);
 302
 303     SER_DPRINTF("IRQ = %d\n", irq);
 304     qemu_set_irq(s->irq, irq);
 305 }
 306
 307 static void escc_reset_chn(ChannelState *s)
 308 {
 309     int i;
 310
 311     s->reg = 0;
 312     for (i = 0; i < SERIAL_REGS; i++) {
 313         s->rregs[i] = 0;
 314         s->wregs[i] = 0;
 315     }
 316     s->wregs[W_TXCTRL1] = TXCTRL1_1STOP; // 1X divisor, 1 stop bit, no parity
 317     s->wregs[W_MINTR] = MINTR_RST_ALL;
 318     s->wregs[W_CLOCK] = CLOCK_TRXC; // Synch mode tx clock = TRxC
 319     s->wregs[W_MISC2] = MISC2_PLLDIS; // PLL disabled
 320     s->wregs[W_EXTINT] = EXTINT_DCD | EXTINT_SYNCINT | EXTINT_CTSINT |
 321         EXTINT_TXUNDRN | EXTINT_BRKINT; // Enable most interrupts
 322     if (s->disabled)
 323         s->rregs[R_STATUS] = STATUS_TXEMPTY | STATUS_DCD | STATUS_SYNC |
 324             STATUS_CTS | STATUS_TXUNDRN;
 325     else
 326         s->rregs[R_STATUS] = STATUS_TXEMPTY | STATUS_TXUNDRN;
 327     s->rregs[R_SPEC] = SPEC_BITS8 | SPEC_ALLSENT;
 328
 329     s->rx = s->tx = 0;
 330     s->rxint = s->txint = 0;
 331     s->rxint_under_svc = s->txint_under_svc = 0;
 332     s->e0_mode = s->led_mode = s->caps_lock_mode = s->num_lock_mode = 0;
 333     clear_queue(s);
 334     serial_update_handlers(s);
 335 }
 336
 337 static void escc_reset(DeviceState *d)
 338 {
 339     SerialState *s = container_of(d, SerialState, busdev.qdev);
 340
 341     escc_reset_chn(&s->chn[0]);
 342     escc_reset_chn(&s->chn[1]);
 343 }
 344
 345 static inline void set_rxint(ChannelState *s)
 346 {
 347     s->rxint = 1;
 348     /* XXX: missing daisy chainnig: chn_b rx should have a lower priority
 349        than chn_a rx/tx/special_condition service*/
 350     s->rxint_under_svc = 1;
 351     if (s->chn == chn_a) {
 352         s->rregs[R_INTR] |= INTR_RXINTA;
 353         if (s->wregs[W_MINTR] & MINTR_STATUSHI)
 354             s->otherchn->rregs[R_IVEC] = IVEC_HIRXINTA;
 355         else
 356             s->otherchn->rregs[R_IVEC] = IVEC_LORXINTA;
 357     } else {
 358         s->otherchn->rregs[R_INTR] |= INTR_RXINTB;
 359         if (s->wregs[W_MINTR] & MINTR_STATUSHI)
 360             s->rregs[R_IVEC] = IVEC_HIRXINTB;
 361         else
 362             s->rregs[R_IVEC] = IVEC_LORXINTB;
 363     }
 364     escc_update_irq(s);
 365 }
 366
 367 static inline void set_txint(ChannelState *s)
 368 {
 369     s->txint = 1;
 370     if (!s->rxint_under_svc) {
 371         s->txint_under_svc = 1;
 372         if (s->chn == chn_a) {
 373             if (s->wregs[W_INTR] & INTR_TXINT) {
 374                 s->rregs[R_INTR] |= INTR_TXINTA;
 375             }
 376             if (s->wregs[W_MINTR] & MINTR_STATUSHI)
 377                 s->otherchn->rregs[R_IVEC] = IVEC_HITXINTA;
 378             else
 379                 s->otherchn->rregs[R_IVEC] = IVEC_LOTXINTA;
 380         } else {
 381             s->rregs[R_IVEC] = IVEC_TXINTB;
 382             if (s->wregs[W_INTR] & INTR_TXINT) {
 383                 s->otherchn->rregs[R_INTR] |= INTR_TXINTB;
 384             }
 385         }
 386     escc_update_irq(s);
 387     }
 388 }
 389
 390 static inline void clr_rxint(ChannelState *s)
 391 {
 392     s->rxint = 0;
 393     s->rxint_under_svc = 0;
 394     if (s->chn == chn_a) {
 395         if (s->wregs[W_MINTR] & MINTR_STATUSHI)
 396             s->otherchn->rregs[R_IVEC] = IVEC_HINOINT;
 397         else
 398             s->otherchn->rregs[R_IVEC] = IVEC_LONOINT;
 399         s->rregs[R_INTR] &= ~INTR_RXINTA;
 400     } else {
 401         if (s->wregs[W_MINTR] & MINTR_STATUSHI)
 402             s->rregs[R_IVEC] = IVEC_HINOINT;
 403         else
 404             s->rregs[R_IVEC] = IVEC_LONOINT;
 405         s->otherchn->rregs[R_INTR] &= ~INTR_RXINTB;
 406     }
 407     if (s->txint)
 408         set_txint(s);
 409     escc_update_irq(s);
 410 }
 411
 412 static inline void clr_txint(ChannelState *s)
 413 {
 414     s->txint = 0;
 415     s->txint_under_svc = 0;
 416     if (s->chn == chn_a) {
 417         if (s->wregs[W_MINTR] & MINTR_STATUSHI)
 418             s->otherchn->rregs[R_IVEC] = IVEC_HINOINT;
 419         else
 420             s->otherchn->rregs[R_IVEC] = IVEC_LONOINT;
 421         s->rregs[R_INTR] &= ~INTR_TXINTA;
 422     } else {
 423         s->otherchn->rregs[R_INTR] &= ~INTR_TXINTB;
 424         if (s->wregs[W_MINTR] & MINTR_STATUSHI)
 425             s->rregs[R_IVEC] = IVEC_HINOINT;
 426         else
 427             s->rregs[R_IVEC] = IVEC_LONOINT;
 428         s->otherchn->rregs[R_INTR] &= ~INTR_TXINTB;
 429     }
 430     if (s->rxint)
 431         set_rxint(s);
 432     escc_update_irq(s);
 433 }
 434
 435 static void escc_update_parameters(ChannelState *s)
 436 {
 437     int speed, parity, data_bits, stop_bits;
 438     QEMUSerialSetParams ssp;
 439
 440     if (!s->chr || s->type != ser)
 441         return;
 442
 443     if (s->wregs[W_TXCTRL1] & TXCTRL1_PAREN) {
 444         if (s->wregs[W_TXCTRL1] & TXCTRL1_PAREV)
 445             parity = 'E';
 446         else
 447             parity = 'O';
 448     } else {
 449         parity = 'N';
 450     }
 451     if ((s->wregs[W_TXCTRL1] & TXCTRL1_STPMSK) == TXCTRL1_2STOP)
 452         stop_bits = 2;
 453     else
 454         stop_bits = 1;
 455     switch (s->wregs[W_TXCTRL2] & TXCTRL2_BITMSK) {
 456     case TXCTRL2_5BITS:
 457         data_bits = 5;
 458         break;
 459     case TXCTRL2_7BITS:
 460         data_bits = 7;
 461         break;
 462     case TXCTRL2_6BITS:
 463         data_bits = 6;
 464         break;
 465     default:
 466     case TXCTRL2_8BITS:
 467         data_bits = 8;
 468         break;
 469     }
 470     speed = s->clock / ((s->wregs[W_BRGLO] | (s->wregs[W_BRGHI] << 8)) + 2);
 471     switch (s->wregs[W_TXCTRL1] & TXCTRL1_CLKMSK) {
 472     case TXCTRL1_CLK1X:
 473         break;
 474     case TXCTRL1_CLK16X:
 475         speed /= 16;
 476         break;
 477     case TXCTRL1_CLK32X:
 478         speed /= 32;
 479         break;
 480     default:
 481     case TXCTRL1_CLK64X:
 482         speed /= 64;
 483         break;
 484     }
 485     ssp.speed = speed;
 486     ssp.parity = parity;
 487     ssp.data_bits = data_bits;
 488     ssp.stop_bits = stop_bits;
 489     SER_DPRINTF("channel %c: speed=%d parity=%c data=%d stop=%d\n", CHN_C(s),
 490                 speed, parity, data_bits, stop_bits);
 491     qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp);
 492 }
 493
 494 static void escc_mem_write(void *opaque, target_phys_addr_t addr,
 495                            uint64_t val, unsigned size)
 496 {
 497     SerialState *serial = opaque;
 498     ChannelState *s;
 499     uint32_t saddr;
 500     int newreg, channel;
 501
 502     val &= 0xff;
 503     saddr = (addr >> serial->it_shift) & 1;
 504     channel = (addr >> (serial->it_shift + 1)) & 1;
 505     s = &serial->chn[channel];
 506     switch (saddr) {
 507     case SERIAL_CTRL:
 508         SER_DPRINTF("Write channel %c, reg[%d] = %2.2x\n", CHN_C(s), s->reg,
 509                     val & 0xff);
 510         newreg = 0;
 511         switch (s->reg) {
 512         case W_CMD:
 513             newreg = val & CMD_PTR_MASK;
 514             val &= CMD_CMD_MASK;
 515             switch (val) {
 516             case CMD_HI:
 517                 newreg |= CMD_HI;
 518                 break;
 519             case CMD_CLR_TXINT:
 520                 clr_txint(s);
 521                 break;
 522             case CMD_CLR_IUS:
 523                 if (s->rxint_under_svc) {
 524                     s->rxint_under_svc = 0;
 525                     if (s->txint) {
 526                         set_txint(s);
 527                     }
 528                 } else if (s->txint_under_svc) {
 529                     s->txint_under_svc = 0;
 530                 }
 531                 escc_update_irq(s);
 532                 break;
 533             default:
 534                 break;
 535             }
 536             break;
 537         case W_INTR ... W_RXCTRL:
 538         case W_SYNC1 ... W_TXBUF:
 539         case W_MISC1 ... W_CLOCK:
 540         case W_MISC2 ... W_EXTINT:
 541             s->wregs[s->reg] = val;
 542             serial_update_handlers(s);
 543             break;
 544         case W_TXCTRL1:
 545         case W_TXCTRL2:
 546             s->wregs[s->reg] = val;
 547             escc_update_parameters(s);
 548             break;
 549         case W_BRGLO:
 550         case W_BRGHI:
 551             s->wregs[s->reg] = val;
 552             s->rregs[s->reg] = val;
 553             escc_update_parameters(s);
 554             break;
 555         case W_MINTR:
 556             switch (val & MINTR_RST_MASK) {
 557             case 0:
 558             default:
 559                 break;
 560             case MINTR_RST_B:
 561                 escc_reset_chn(&serial->chn[0]);
 562                 return;
 563             case MINTR_RST_A:
 564                 escc_reset_chn(&serial->chn[1]);
 565                 return;
 566             case MINTR_RST_ALL:
 567                 escc_reset(&serial->busdev.qdev);
 568                 return;
 569             }
 570             break;
 571         default:
 572             break;
 573         }
 574         if (s->reg == 0)
 575             s->reg = newreg;
 576         else
 577             s->reg = 0;
 578         break;
 579     case SERIAL_DATA:
 580         SER_DPRINTF("Write channel %c, ch %d\n", CHN_C(s), val);
 581         s->tx = val;
 582         if (s->wregs[W_TXCTRL2] & TXCTRL2_TXEN) { // tx enabled
 583             if (s->chr)
 584                 qemu_chr_fe_write(s->chr, &s->tx, 1);
 585             else if (s->type == kbd && !s->disabled) {
 586                 handle_kbd_command(s, val);
 587             }
 588         }
 589         s->rregs[R_STATUS] |= STATUS_TXEMPTY; // Tx buffer empty
 590         s->rregs[R_SPEC] |= SPEC_ALLSENT; // All sent
 591         serial_update_handlers(s);
 592         set_txint(s);
 593         break;
 594     default:
 595         break;
 596     }
 597 }
 598
 599 static uint64_t escc_mem_read(void *opaque, target_phys_addr_t addr,
 600                               unsigned size)
 601 {
 602     SerialState *serial = opaque;
 603     ChannelState *s;
 604     uint32_t saddr;
 605     uint32_t ret;
 606     int channel;
 607
 608     saddr = (addr >> serial->it_shift) & 1;
 609     channel = (addr >> (serial->it_shift + 1)) & 1;
 610     s = &serial->chn[channel];
 611     switch (saddr) {
 612     case SERIAL_CTRL:
 613         SER_DPRINTF("Read channel %c, reg[%d] = %2.2x\n", CHN_C(s), s->reg,
 614                     s->rregs[s->reg]);
 615         ret = s->rregs[s->reg];
 616         s->reg = 0;
 617         return ret;
 618     case SERIAL_DATA:
 619         s->rregs[R_STATUS] &= ~STATUS_RXAV;
 620         clr_rxint(s);
 621         if (s->type == kbd || s->type == mouse)
 622             ret = get_queue(s);
 623         else
 624             ret = s->rx;
 625         SER_DPRINTF("Read channel %c, ch %d\n", CHN_C(s), ret);
 626         serial_update_handlers(s);
 627         return ret;
 628     default:
 629         break;
 630     }
 631     return 0;
 632 }
 633
 634 static const MemoryRegionOps escc_mem_ops = {
 635     .read = escc_mem_read,
 636     .write = escc_mem_write,
 637     .endianness = DEVICE_NATIVE_ENDIAN,
 638     .valid = {
 639         .min_access_size = 1,
 640         .max_access_size = 1,
 641     },
 642 };
 643
 644 static int serial_can_receive(ChannelState *s)
 645 {
 646     int ret;
 647
 648     if (((s->wregs[W_RXCTRL] & RXCTRL_RXEN) == 0) // Rx not enabled
 649         || ((s->rregs[R_STATUS] & STATUS_RXAV) == STATUS_RXAV))
 650         // char already available
 651         ret = 0;
 652     else
 653         ret = 1;
 654     return ret;
 655 }
 656
 657 static void serial_receive_byte(ChannelState *s, int ch)
 658 {
 659     SER_DPRINTF("channel %c put ch %d\n", CHN_C(s), ch);
 660     s->rregs[R_STATUS] |= STATUS_RXAV;
 661     s->rx = ch;
 662     set_rxint(s);
 663     serial_update_handlers(s);
 664 }
 665
 666 static void serial_receive_break(ChannelState *s)
 667 {
 668     s->rregs[R_STATUS] |= STATUS_BRK;
 669     serial_update_handlers(s);
 670     escc_update_irq(s);
 671 }
 672
 673 static void serial_receive1(void *opaque)
 674 {
 675     ChannelState *s = opaque;
 676     uint8_t buf[32];
 677     int size;
 678
 679     size = serial_can_receive(s);
 680     size = MIN(size, sizeof(buf));
 681     size = qemu_chr_fe_read(s->chr, buf, size);
 682
 683     serial_receive_byte(s, buf[0]);
 684 }
 685
 686 static int serial_event(void *opaque, int event, void *data)
 687 {
 688     ChannelState *s = opaque;
 689     if (event == CHR_EVENT_BREAK)
 690         serial_receive_break(s);
 691     return 0;
 692 }
 693
 694 static void serial_update_handlers(ChannelState *s)
 695 {
 696     if (serial_can_receive(s) > 0) {
 697         qemu_chr_fe_set_handlers(s->chr, serial_receive1,
 698                                  NULL, serial_event, s);
 699     } else {
 700         qemu_chr_fe_set_handlers(s->chr, NULL, NULL, serial_event, s);
 701     }
 702 }
 703
 704 static const VMStateDescription vmstate_escc_chn = {
 705     .name ="escc_chn",
 706     .version_id = 2,
 707     .minimum_version_id = 1,
 708     .minimum_version_id_old = 1,
 709     .fields      = (VMStateField []) {
 710         VMSTATE_UINT32(vmstate_dummy, ChannelState),
 711         VMSTATE_UINT32(reg, ChannelState),
 712         VMSTATE_UINT32(rxint, ChannelState),
 713         VMSTATE_UINT32(txint, ChannelState),
 714         VMSTATE_UINT32(rxint_under_svc, ChannelState),
 715         VMSTATE_UINT32(txint_under_svc, ChannelState),
 716         VMSTATE_UINT8(rx, ChannelState),
 717         VMSTATE_UINT8(tx, ChannelState),
 718         VMSTATE_BUFFER(wregs, ChannelState),
 719         VMSTATE_BUFFER(rregs, ChannelState),
 720         VMSTATE_END_OF_LIST()
 721     }
 722 };
 723
 724 static const VMStateDescription vmstate_escc = {
 725     .name ="escc",
 726     .version_id = 2,
 727     .minimum_version_id = 1,
 728     .minimum_version_id_old = 1,
 729     .fields      = (VMStateField []) {
 730         VMSTATE_STRUCT_ARRAY(chn, SerialState, 2, 2, vmstate_escc_chn,
 731                              ChannelState),
 732         VMSTATE_END_OF_LIST()
 733     }
 734 };
 735
 736 MemoryRegion *escc_init(target_phys_addr_t base, qemu_irq irqA, qemu_irq irqB,
 737               CharDriverState *chrA, CharDriverState *chrB,
 738               int clock, int it_shift)
 739 {
 740     DeviceState *dev;
 741     SysBusDevice *s;
 742     SerialState *d;
 743
 744     dev = qdev_create(NULL, "escc");
 745     qdev_prop_set_uint32(dev, "disabled", 0);
 746     qdev_prop_set_uint32(dev, "frequency", clock);
 747     qdev_prop_set_uint32(dev, "it_shift", it_shift);
 748     qdev_prop_set_chr(dev, "chrB", chrB);
 749     qdev_prop_set_chr(dev, "chrA", chrA);
 750     qdev_prop_set_uint32(dev, "chnBtype", ser);
 751     qdev_prop_set_uint32(dev, "chnAtype", ser);
 752     qdev_init_nofail(dev);
 753     s = sysbus_from_qdev(dev);
 754     sysbus_connect_irq(s, 0, irqB);
 755     sysbus_connect_irq(s, 1, irqA);
 756     if (base) {
 757         sysbus_mmio_map(s, 0, base);
 758     }
 759
 760     d = FROM_SYSBUS(SerialState, s);
 761     return &d->mmio;
 762 }
 763
 764 static const uint8_t keycodes[128] = {
 765     127, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 43, 53,
 766     54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 89, 76, 77, 78,
 767     79, 80, 81, 82, 83, 84, 85, 86, 87, 42, 99, 88, 100, 101, 102, 103,
 768     104, 105, 106, 107, 108, 109, 110, 47, 19, 121, 119, 5, 6, 8, 10, 12,
 769     14, 16, 17, 18, 7, 98, 23, 68, 69, 70, 71, 91, 92, 93, 125, 112,
 770     113, 114, 94, 50, 0, 0, 124, 9, 11, 0, 0, 0, 0, 0, 0, 0,
 771     90, 0, 46, 22, 13, 111, 52, 20, 96, 24, 28, 74, 27, 123, 44, 66,
 772     0, 45, 2, 4, 48, 0, 0, 21, 0, 0, 0, 0, 0, 120, 122, 67,
 773 };
 774
 775 static const uint8_t e0_keycodes[128] = {
 776     0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
 777     0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 90, 76, 0, 0,
 778     0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
 779     0, 0, 0, 0, 0, 109, 0, 0, 13, 0, 0, 0, 0, 0, 0, 0,
 780     0, 0, 0, 0, 0, 0, 0, 68, 69, 70, 0, 91, 0, 93, 0, 112,
 781     113, 114, 94, 50, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
 782     0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
 783     1, 3, 25, 26, 49, 52, 72, 73, 97, 99, 111, 118, 120, 122, 67, 0,
 784 };
 785
 786 static void sunkbd_event(void *opaque, int ch)
 787 {
 788     ChannelState *s = opaque;
 789     int release = ch & 0x80;
 790
 791     KBD_DPRINTF("Untranslated keycode %2.2x (%s)\n", ch, release? "release" :
 792                 "press");
 793     switch (ch) {
 794     case 58: // Caps lock press
 795         s->caps_lock_mode ^= 1;
 796         if (s->caps_lock_mode == 2)
 797             return; // Drop second press
 798         break;
 799     case 69: // Num lock press
 800         s->num_lock_mode ^= 1;
 801         if (s->num_lock_mode == 2)
 802             return; // Drop second press
 803         break;
 804     case 186: // Caps lock release
 805         s->caps_lock_mode ^= 2;
 806         if (s->caps_lock_mode == 3)
 807             return; // Drop first release
 808         break;
 809     case 197: // Num lock release
 810         s->num_lock_mode ^= 2;
 811         if (s->num_lock_mode == 3)
 812             return; // Drop first release
 813         break;
 814     case 0xe0:
 815         s->e0_mode = 1;
 816         return;
 817     default:
 818         break;
 819     }
 820     if (s->e0_mode) {
 821         s->e0_mode = 0;
 822         ch = e0_keycodes[ch & 0x7f];
 823     } else {
 824         ch = keycodes[ch & 0x7f];
 825     }
 826     KBD_DPRINTF("Translated keycode %2.2x\n", ch);
 827     put_queue(s, ch | release);
 828 }
 829
 830 static void handle_kbd_command(ChannelState *s, int val)
 831 {
 832     KBD_DPRINTF("Command %d\n", val);
 833     if (s->led_mode) { // Ignore led byte
 834         s->led_mode = 0;
 835         return;
 836     }
 837     switch (val) {
 838     case 1: // Reset, return type code
 839         clear_queue(s);
 840         put_queue(s, 0xff);
 841         put_queue(s, 4); // Type 4
 842         put_queue(s, 0x7f);
 843         break;
 844     case 0xe: // Set leds
 845         s->led_mode = 1;
 846         break;
 847     case 7: // Query layout
 848     case 0xf:
 849         clear_queue(s);
 850         put_queue(s, 0xfe);
 851         put_queue(s, 0); // XXX, layout?
 852         break;
 853     default:
 854         break;
 855     }
 856 }
 857
 858 static void sunmouse_event(void *opaque,
 859                                int dx, int dy, int dz, int buttons_state)
 860 {
 861     ChannelState *s = opaque;
 862     int ch;
 863
 864     MS_DPRINTF("dx=%d dy=%d buttons=%01x\n", dx, dy, buttons_state);
 865
 866     ch = 0x80 | 0x7; /* protocol start byte, no buttons pressed */
 867
 868     if (buttons_state & MOUSE_EVENT_LBUTTON)
 869         ch ^= 0x4;
 870     if (buttons_state & MOUSE_EVENT_MBUTTON)
 871         ch ^= 0x2;
 872     if (buttons_state & MOUSE_EVENT_RBUTTON)
 873         ch ^= 0x1;
 874
 875     put_queue(s, ch);
 876
 877     ch = dx;
 878
 879     if (ch > 127)
 880         ch = 127;
 881     else if (ch < -127)
 882         ch = -127;
 883
 884     put_queue(s, ch & 0xff);
 885
 886     ch = -dy;
 887
 888     if (ch > 127)
 889         ch = 127;
 890     else if (ch < -127)
 891         ch = -127;
 892
 893     put_queue(s, ch & 0xff);
 894
 895     // MSC protocol specify two extra motion bytes
 896
 897     put_queue(s, 0);
 898     put_queue(s, 0);
 899 }
 900
 901 void slavio_serial_ms_kbd_init(target_phys_addr_t base, qemu_irq irq,
 902                                int disabled, int clock, int it_shift)
 903 {
 904     DeviceState *dev;
 905     SysBusDevice *s;
 906
 907     dev = qdev_create(NULL, "escc");
 908     qdev_prop_set_uint32(dev, "disabled", disabled);
 909     qdev_prop_set_uint32(dev, "frequency", clock);
 910     qdev_prop_set_uint32(dev, "it_shift", it_shift);
 911     qdev_prop_set_chr(dev, "chrB", NULL);
 912     qdev_prop_set_chr(dev, "chrA", NULL);
 913     qdev_prop_set_uint32(dev, "chnBtype", mouse);
 914     qdev_prop_set_uint32(dev, "chnAtype", kbd);
 915     qdev_init_nofail(dev);
 916     s = sysbus_from_qdev(dev);
 917     sysbus_connect_irq(s, 0, irq);
 918     sysbus_connect_irq(s, 1, irq);
 919     sysbus_mmio_map(s, 0, base);
 920 }
 921
 922 static int escc_init1(SysBusDevice *dev)
 923 {
 924     SerialState *s = FROM_SYSBUS(SerialState, dev);
 925     unsigned int i;
 926
 927     s->chn[0].disabled = s->disabled;
 928     s->chn[1].disabled = s->disabled;
 929     for (i = 0; i < 2; i++) {
 930         sysbus_init_irq(dev, &s->chn[i].irq);
 931         s->chn[i].chn = 1 - i;
 932         s->chn[i].clock = s->frequency / 2;
 933         if (s->chn[i].chr) {
 934             qemu_chr_fe_open(s->chn[i].chr);
 935             serial_update_handlers(&s->chn[i]);
 936         }
 937     }
 938     s->chn[0].otherchn = &s->chn[1];
 939     s->chn[1].otherchn = &s->chn[0];
 940
 941     memory_region_init_io(&s->mmio, &escc_mem_ops, s, "escc",
 942                           ESCC_SIZE << s->it_shift);
 943     sysbus_init_mmio_region(dev, &s->mmio);
 944
 945     if (s->chn[0].type == mouse) {
 946         qemu_add_mouse_event_handler(sunmouse_event, &s->chn[0], 0,
 947                                      "QEMU Sun Mouse");
 948     }
 949     if (s->chn[1].type == kbd) {
 950         qemu_add_kbd_event_handler(sunkbd_event, &s->chn[1]);
 951     }
 952
 953     return 0;
 954 }
 955
 956 static SysBusDeviceInfo escc_info = {
 957     .init = escc_init1,
 958     .qdev.name  = "escc",
 959     .qdev.size  = sizeof(SerialState),
 960     .qdev.vmsd  = &vmstate_escc,
 961     .qdev.reset = escc_reset,
 962     .qdev.props = (Property[]) {
 963         DEFINE_PROP_UINT32("frequency", SerialState, frequency,   0),
 964         DEFINE_PROP_UINT32("it_shift",  SerialState, it_shift,    0),
 965         DEFINE_PROP_UINT32("disabled",  SerialState, disabled,    0),
 966         DEFINE_PROP_UINT32("disabled",  SerialState, disabled,    0),
 967         DEFINE_PROP_UINT32("chnBtype",  SerialState, chn[0].type, 0),
 968         DEFINE_PROP_UINT32("chnAtype",  SerialState, chn[1].type, 0),
 969         DEFINE_PROP_CHR("chrB", SerialState, chn[0].chr),
 970         DEFINE_PROP_CHR("chrA", SerialState, chn[1].chr),
 971         DEFINE_PROP_END_OF_LIST(),
 972     }
 973 };
 974
 975 static void escc_register_devices(void)
 976 {
 977     sysbus_register_withprop(&escc_info);
 978 }
 979
 980 device_init(escc_register_devices)