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ditto for etraxfs_ser.c
[qemu/aliguori.git] / hw / omap1.c
blob400de475d9d4697d9a82aa66b6c35c285c0b724d
1 /*
2 * TI OMAP processors emulation.
3 *
4 * Copyright (C) 2006-2008 Andrzej Zaborowski <balrog@zabor.org>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 or
9 * (at your option) version 3 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, see <http://www.gnu.org/licenses/>.
18 */
19 #include "hw.h"
20 #include "arm-misc.h"
21 #include "omap.h"
22 #include "sysemu.h"
23 #include "qemu-timer.h"
24 #include "qemu-char.h"
25 #include "soc_dma.h"
26 /* We use pc-style serial ports. */
27 #include "pc.h"
28 #include "blockdev.h"
29 #include "range.h"
30 #include "sysbus.h"
31
32 /* Should signal the TCMI/GPMC */
33 uint32_t omap_badwidth_read8(void *opaque, target_phys_addr_t addr)
34 {
35 uint8_t ret;
36
37 OMAP_8B_REG(addr);
38 cpu_physical_memory_read(addr, (void *) &ret, 1);
39 return ret;
40 }
41
42 void omap_badwidth_write8(void *opaque, target_phys_addr_t addr,
43 uint32_t value)
44 {
45 uint8_t val8 = value;
46
47 OMAP_8B_REG(addr);
48 cpu_physical_memory_write(addr, (void *) &val8, 1);
49 }
50
51 uint32_t omap_badwidth_read16(void *opaque, target_phys_addr_t addr)
52 {
53 uint16_t ret;
54
55 OMAP_16B_REG(addr);
56 cpu_physical_memory_read(addr, (void *) &ret, 2);
57 return ret;
58 }
59
60 void omap_badwidth_write16(void *opaque, target_phys_addr_t addr,
61 uint32_t value)
62 {
63 uint16_t val16 = value;
64
65 OMAP_16B_REG(addr);
66 cpu_physical_memory_write(addr, (void *) &val16, 2);
67 }
68
69 uint32_t omap_badwidth_read32(void *opaque, target_phys_addr_t addr)
70 {
71 uint32_t ret;
72
73 OMAP_32B_REG(addr);
74 cpu_physical_memory_read(addr, (void *) &ret, 4);
75 return ret;
76 }
77
78 void omap_badwidth_write32(void *opaque, target_phys_addr_t addr,
79 uint32_t value)
80 {
81 OMAP_32B_REG(addr);
82 cpu_physical_memory_write(addr, (void *) &value, 4);
83 }
84
85 /* MPU OS timers */
86 struct omap_mpu_timer_s {
87 qemu_irq irq;
88 omap_clk clk;
89 uint32_t val;
90 int64_t time;
91 QEMUTimer *timer;
92 QEMUBH *tick;
93 int64_t rate;
94 int it_ena;
95
96 int enable;
97 int ptv;
98 int ar;
99 int st;
100 uint32_t reset_val;
101 };
102
103 static inline uint32_t omap_timer_read(struct omap_mpu_timer_s *timer)
104 {
105 uint64_t distance = qemu_get_clock_ns(vm_clock) - timer->time;
106
107 if (timer->st && timer->enable && timer->rate)
108 return timer->val - muldiv64(distance >> (timer->ptv + 1),
109 timer->rate, get_ticks_per_sec());
110 else
111 return timer->val;
112 }
113
114 static inline void omap_timer_sync(struct omap_mpu_timer_s *timer)
115 {
116 timer->val = omap_timer_read(timer);
117 timer->time = qemu_get_clock_ns(vm_clock);
118 }
119
120 static inline void omap_timer_update(struct omap_mpu_timer_s *timer)
121 {
122 int64_t expires;
123
124 if (timer->enable && timer->st && timer->rate) {
125 timer->val = timer->reset_val; /* Should skip this on clk enable */
126 expires = muldiv64((uint64_t) timer->val << (timer->ptv + 1),
127 get_ticks_per_sec(), timer->rate);
128
129 /* If timer expiry would be sooner than in about 1 ms and
130 * auto-reload isn't set, then fire immediately. This is a hack
131 * to make systems like PalmOS run in acceptable time. PalmOS
132 * sets the interval to a very low value and polls the status bit
133 * in a busy loop when it wants to sleep just a couple of CPU
134 * ticks. */
135 if (expires > (get_ticks_per_sec() >> 10) || timer->ar)
136 qemu_mod_timer(timer->timer, timer->time + expires);
137 else
138 qemu_bh_schedule(timer->tick);
139 } else
140 qemu_del_timer(timer->timer);
141 }
142
143 static void omap_timer_fire(void *opaque)
144 {
145 struct omap_mpu_timer_s *timer = opaque;
146
147 if (!timer->ar) {
148 timer->val = 0;
149 timer->st = 0;
150 }
151
152 if (timer->it_ena)
153 /* Edge-triggered irq */
154 qemu_irq_pulse(timer->irq);
155 }
156
157 static void omap_timer_tick(void *opaque)
158 {
159 struct omap_mpu_timer_s *timer = (struct omap_mpu_timer_s *) opaque;
160
161 omap_timer_sync(timer);
162 omap_timer_fire(timer);
163 omap_timer_update(timer);
164 }
165
166 static void omap_timer_clk_update(void *opaque, int line, int on)
167 {
168 struct omap_mpu_timer_s *timer = (struct omap_mpu_timer_s *) opaque;
169
170 omap_timer_sync(timer);
171 timer->rate = on ? omap_clk_getrate(timer->clk) : 0;
172 omap_timer_update(timer);
173 }
174
175 static void omap_timer_clk_setup(struct omap_mpu_timer_s *timer)
176 {
177 omap_clk_adduser(timer->clk,
178 qemu_allocate_irqs(omap_timer_clk_update, timer, 1)[0]);
179 timer->rate = omap_clk_getrate(timer->clk);
180 }
181
182 static uint32_t omap_mpu_timer_read(void *opaque, target_phys_addr_t addr)
183 {
184 struct omap_mpu_timer_s *s = (struct omap_mpu_timer_s *) opaque;
185
186 switch (addr) {
187 case 0x00: /* CNTL_TIMER */
188 return (s->enable << 5) | (s->ptv << 2) | (s->ar << 1) | s->st;
189
190 case 0x04: /* LOAD_TIM */
191 break;
192
193 case 0x08: /* READ_TIM */
194 return omap_timer_read(s);
195 }
196
197 OMAP_BAD_REG(addr);
198 return 0;
199 }
200
201 static void omap_mpu_timer_write(void *opaque, target_phys_addr_t addr,
202 uint32_t value)
203 {
204 struct omap_mpu_timer_s *s = (struct omap_mpu_timer_s *) opaque;
205
206 switch (addr) {
207 case 0x00: /* CNTL_TIMER */
208 omap_timer_sync(s);
209 s->enable = (value >> 5) & 1;
210 s->ptv = (value >> 2) & 7;
211 s->ar = (value >> 1) & 1;
212 s->st = value & 1;
213 omap_timer_update(s);
214 return;
215
216 case 0x04: /* LOAD_TIM */
217 s->reset_val = value;
218 return;
219
220 case 0x08: /* READ_TIM */
221 OMAP_RO_REG(addr);
222 break;
223
224 default:
225 OMAP_BAD_REG(addr);
226 }
227 }
228
229 static CPUReadMemoryFunc * const omap_mpu_timer_readfn[] = {
230 omap_badwidth_read32,
231 omap_badwidth_read32,
232 omap_mpu_timer_read,
233 };
234
235 static CPUWriteMemoryFunc * const omap_mpu_timer_writefn[] = {
236 omap_badwidth_write32,
237 omap_badwidth_write32,
238 omap_mpu_timer_write,
239 };
240
241 static void omap_mpu_timer_reset(struct omap_mpu_timer_s *s)
242 {
243 qemu_del_timer(s->timer);
244 s->enable = 0;
245 s->reset_val = 31337;
246 s->val = 0;
247 s->ptv = 0;
248 s->ar = 0;
249 s->st = 0;
250 s->it_ena = 1;
251 }
252
253 static struct omap_mpu_timer_s *omap_mpu_timer_init(target_phys_addr_t base,
254 qemu_irq irq, omap_clk clk)
255 {
256 int iomemtype;
257 struct omap_mpu_timer_s *s = (struct omap_mpu_timer_s *)
258 qemu_mallocz(sizeof(struct omap_mpu_timer_s));
259
260 s->irq = irq;
261 s->clk = clk;
262 s->timer = qemu_new_timer_ns(vm_clock, omap_timer_tick, s);
263 s->tick = qemu_bh_new(omap_timer_fire, s);
264 omap_mpu_timer_reset(s);
265 omap_timer_clk_setup(s);
266
267 iomemtype = cpu_register_io_memory(omap_mpu_timer_readfn,
268 omap_mpu_timer_writefn, s, DEVICE_NATIVE_ENDIAN);
269 cpu_register_physical_memory(base, 0x100, iomemtype);
270
271 return s;
272 }
273
274 /* Watchdog timer */
275 struct omap_watchdog_timer_s {
276 struct omap_mpu_timer_s timer;
277 uint8_t last_wr;
278 int mode;
279 int free;
280 int reset;
281 };
282
283 static uint32_t omap_wd_timer_read(void *opaque, target_phys_addr_t addr)
284 {
285 struct omap_watchdog_timer_s *s = (struct omap_watchdog_timer_s *) opaque;
286
287 switch (addr) {
288 case 0x00: /* CNTL_TIMER */
289 return (s->timer.ptv << 9) | (s->timer.ar << 8) |
290 (s->timer.st << 7) | (s->free << 1);
291
292 case 0x04: /* READ_TIMER */
293 return omap_timer_read(&s->timer);
294
295 case 0x08: /* TIMER_MODE */
296 return s->mode << 15;
297 }
298
299 OMAP_BAD_REG(addr);
300 return 0;
301 }
302
303 static void omap_wd_timer_write(void *opaque, target_phys_addr_t addr,
304 uint32_t value)
305 {
306 struct omap_watchdog_timer_s *s = (struct omap_watchdog_timer_s *) opaque;
307
308 switch (addr) {
309 case 0x00: /* CNTL_TIMER */
310 omap_timer_sync(&s->timer);
311 s->timer.ptv = (value >> 9) & 7;
312 s->timer.ar = (value >> 8) & 1;
313 s->timer.st = (value >> 7) & 1;
314 s->free = (value >> 1) & 1;
315 omap_timer_update(&s->timer);
316 break;
317
318 case 0x04: /* LOAD_TIMER */
319 s->timer.reset_val = value & 0xffff;
320 break;
321
322 case 0x08: /* TIMER_MODE */
323 if (!s->mode && ((value >> 15) & 1))
324 omap_clk_get(s->timer.clk);
325 s->mode |= (value >> 15) & 1;
326 if (s->last_wr == 0xf5) {
327 if ((value & 0xff) == 0xa0) {
328 if (s->mode) {
329 s->mode = 0;
330 omap_clk_put(s->timer.clk);
331 }
332 } else {
333 /* XXX: on T|E hardware somehow this has no effect,
334 * on Zire 71 it works as specified. */
335 s->reset = 1;
336 qemu_system_reset_request();
337 }
338 }
339 s->last_wr = value & 0xff;
340 break;
341
342 default:
343 OMAP_BAD_REG(addr);
344 }
345 }
346
347 static CPUReadMemoryFunc * const omap_wd_timer_readfn[] = {
348 omap_badwidth_read16,
349 omap_wd_timer_read,
350 omap_badwidth_read16,
351 };
352
353 static CPUWriteMemoryFunc * const omap_wd_timer_writefn[] = {
354 omap_badwidth_write16,
355 omap_wd_timer_write,
356 omap_badwidth_write16,
357 };
358
359 static void omap_wd_timer_reset(struct omap_watchdog_timer_s *s)
360 {
361 qemu_del_timer(s->timer.timer);
362 if (!s->mode)
363 omap_clk_get(s->timer.clk);
364 s->mode = 1;
365 s->free = 1;
366 s->reset = 0;
367 s->timer.enable = 1;
368 s->timer.it_ena = 1;
369 s->timer.reset_val = 0xffff;
370 s->timer.val = 0;
371 s->timer.st = 0;
372 s->timer.ptv = 0;
373 s->timer.ar = 0;
374 omap_timer_update(&s->timer);
375 }
376
377 static struct omap_watchdog_timer_s *omap_wd_timer_init(target_phys_addr_t base,
378 qemu_irq irq, omap_clk clk)
379 {
380 int iomemtype;
381 struct omap_watchdog_timer_s *s = (struct omap_watchdog_timer_s *)
382 qemu_mallocz(sizeof(struct omap_watchdog_timer_s));
383
384 s->timer.irq = irq;
385 s->timer.clk = clk;
386 s->timer.timer = qemu_new_timer_ns(vm_clock, omap_timer_tick, &s->timer);
387 omap_wd_timer_reset(s);
388 omap_timer_clk_setup(&s->timer);
389
390 iomemtype = cpu_register_io_memory(omap_wd_timer_readfn,
391 omap_wd_timer_writefn, s, DEVICE_NATIVE_ENDIAN);
392 cpu_register_physical_memory(base, 0x100, iomemtype);
393
394 return s;
395 }
396
397 /* 32-kHz timer */
398 struct omap_32khz_timer_s {
399 struct omap_mpu_timer_s timer;
400 };
401
402 static uint32_t omap_os_timer_read(void *opaque, target_phys_addr_t addr)
403 {
404 struct omap_32khz_timer_s *s = (struct omap_32khz_timer_s *) opaque;
405 int offset = addr & OMAP_MPUI_REG_MASK;
406
407 switch (offset) {
408 case 0x00: /* TVR */
409 return s->timer.reset_val;
410
411 case 0x04: /* TCR */
412 return omap_timer_read(&s->timer);
413
414 case 0x08: /* CR */
415 return (s->timer.ar << 3) | (s->timer.it_ena << 2) | s->timer.st;
416
417 default:
418 break;
419 }
420 OMAP_BAD_REG(addr);
421 return 0;
422 }
423
424 static void omap_os_timer_write(void *opaque, target_phys_addr_t addr,
425 uint32_t value)
426 {
427 struct omap_32khz_timer_s *s = (struct omap_32khz_timer_s *) opaque;
428 int offset = addr & OMAP_MPUI_REG_MASK;
429
430 switch (offset) {
431 case 0x00: /* TVR */
432 s->timer.reset_val = value & 0x00ffffff;
433 break;
434
435 case 0x04: /* TCR */
436 OMAP_RO_REG(addr);
437 break;
438
439 case 0x08: /* CR */
440 s->timer.ar = (value >> 3) & 1;
441 s->timer.it_ena = (value >> 2) & 1;
442 if (s->timer.st != (value & 1) || (value & 2)) {
443 omap_timer_sync(&s->timer);
444 s->timer.enable = value & 1;
445 s->timer.st = value & 1;
446 omap_timer_update(&s->timer);
447 }
448 break;
449
450 default:
451 OMAP_BAD_REG(addr);
452 }
453 }
454
455 static CPUReadMemoryFunc * const omap_os_timer_readfn[] = {
456 omap_badwidth_read32,
457 omap_badwidth_read32,
458 omap_os_timer_read,
459 };
460
461 static CPUWriteMemoryFunc * const omap_os_timer_writefn[] = {
462 omap_badwidth_write32,
463 omap_badwidth_write32,
464 omap_os_timer_write,
465 };
466
467 static void omap_os_timer_reset(struct omap_32khz_timer_s *s)
468 {
469 qemu_del_timer(s->timer.timer);
470 s->timer.enable = 0;
471 s->timer.it_ena = 0;
472 s->timer.reset_val = 0x00ffffff;
473 s->timer.val = 0;
474 s->timer.st = 0;
475 s->timer.ptv = 0;
476 s->timer.ar = 1;
477 }
478
479 static struct omap_32khz_timer_s *omap_os_timer_init(target_phys_addr_t base,
480 qemu_irq irq, omap_clk clk)
481 {
482 int iomemtype;
483 struct omap_32khz_timer_s *s = (struct omap_32khz_timer_s *)
484 qemu_mallocz(sizeof(struct omap_32khz_timer_s));
485
486 s->timer.irq = irq;
487 s->timer.clk = clk;
488 s->timer.timer = qemu_new_timer_ns(vm_clock, omap_timer_tick, &s->timer);
489 omap_os_timer_reset(s);
490 omap_timer_clk_setup(&s->timer);
491
492 iomemtype = cpu_register_io_memory(omap_os_timer_readfn,
493 omap_os_timer_writefn, s, DEVICE_NATIVE_ENDIAN);
494 cpu_register_physical_memory(base, 0x800, iomemtype);
495
496 return s;
497 }
498
499 /* Ultra Low-Power Device Module */
500 static uint32_t omap_ulpd_pm_read(void *opaque, target_phys_addr_t addr)
501 {
502 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
503 uint16_t ret;
504
505 switch (addr) {
506 case 0x14: /* IT_STATUS */
507 ret = s->ulpd_pm_regs[addr >> 2];
508 s->ulpd_pm_regs[addr >> 2] = 0;
509 qemu_irq_lower(s->irq[1][OMAP_INT_GAUGE_32K]);
510 return ret;
511
512 case 0x18: /* Reserved */
513 case 0x1c: /* Reserved */
514 case 0x20: /* Reserved */
515 case 0x28: /* Reserved */
516 case 0x2c: /* Reserved */
517 OMAP_BAD_REG(addr);
518 case 0x00: /* COUNTER_32_LSB */
519 case 0x04: /* COUNTER_32_MSB */
520 case 0x08: /* COUNTER_HIGH_FREQ_LSB */
521 case 0x0c: /* COUNTER_HIGH_FREQ_MSB */
522 case 0x10: /* GAUGING_CTRL */
523 case 0x24: /* SETUP_ANALOG_CELL3_ULPD1 */
524 case 0x30: /* CLOCK_CTRL */
525 case 0x34: /* SOFT_REQ */
526 case 0x38: /* COUNTER_32_FIQ */
527 case 0x3c: /* DPLL_CTRL */
528 case 0x40: /* STATUS_REQ */
529 /* XXX: check clk::usecount state for every clock */
530 case 0x48: /* LOCL_TIME */
531 case 0x4c: /* APLL_CTRL */
532 case 0x50: /* POWER_CTRL */
533 return s->ulpd_pm_regs[addr >> 2];
534 }
535
536 OMAP_BAD_REG(addr);
537 return 0;
538 }
539
540 static inline void omap_ulpd_clk_update(struct omap_mpu_state_s *s,
541 uint16_t diff, uint16_t value)
542 {
543 if (diff & (1 << 4)) /* USB_MCLK_EN */
544 omap_clk_onoff(omap_findclk(s, "usb_clk0"), (value >> 4) & 1);
545 if (diff & (1 << 5)) /* DIS_USB_PVCI_CLK */
546 omap_clk_onoff(omap_findclk(s, "usb_w2fc_ck"), (~value >> 5) & 1);
547 }
548
549 static inline void omap_ulpd_req_update(struct omap_mpu_state_s *s,
550 uint16_t diff, uint16_t value)
551 {
552 if (diff & (1 << 0)) /* SOFT_DPLL_REQ */
553 omap_clk_canidle(omap_findclk(s, "dpll4"), (~value >> 0) & 1);
554 if (diff & (1 << 1)) /* SOFT_COM_REQ */
555 omap_clk_canidle(omap_findclk(s, "com_mclk_out"), (~value >> 1) & 1);
556 if (diff & (1 << 2)) /* SOFT_SDW_REQ */
557 omap_clk_canidle(omap_findclk(s, "bt_mclk_out"), (~value >> 2) & 1);
558 if (diff & (1 << 3)) /* SOFT_USB_REQ */
559 omap_clk_canidle(omap_findclk(s, "usb_clk0"), (~value >> 3) & 1);
560 }
561
562 static void omap_ulpd_pm_write(void *opaque, target_phys_addr_t addr,
563 uint32_t value)
564 {
565 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
566 int64_t now, ticks;
567 int div, mult;
568 static const int bypass_div[4] = { 1, 2, 4, 4 };
569 uint16_t diff;
570
571 switch (addr) {
572 case 0x00: /* COUNTER_32_LSB */
573 case 0x04: /* COUNTER_32_MSB */
574 case 0x08: /* COUNTER_HIGH_FREQ_LSB */
575 case 0x0c: /* COUNTER_HIGH_FREQ_MSB */
576 case 0x14: /* IT_STATUS */
577 case 0x40: /* STATUS_REQ */
578 OMAP_RO_REG(addr);
579 break;
580
581 case 0x10: /* GAUGING_CTRL */
582 /* Bits 0 and 1 seem to be confused in the OMAP 310 TRM */
583 if ((s->ulpd_pm_regs[addr >> 2] ^ value) & 1) {
584 now = qemu_get_clock_ns(vm_clock);
585
586 if (value & 1)
587 s->ulpd_gauge_start = now;
588 else {
589 now -= s->ulpd_gauge_start;
590
591 /* 32-kHz ticks */
592 ticks = muldiv64(now, 32768, get_ticks_per_sec());
593 s->ulpd_pm_regs[0x00 >> 2] = (ticks >> 0) & 0xffff;
594 s->ulpd_pm_regs[0x04 >> 2] = (ticks >> 16) & 0xffff;
595 if (ticks >> 32) /* OVERFLOW_32K */
596 s->ulpd_pm_regs[0x14 >> 2] |= 1 << 2;
597
598 /* High frequency ticks */
599 ticks = muldiv64(now, 12000000, get_ticks_per_sec());
600 s->ulpd_pm_regs[0x08 >> 2] = (ticks >> 0) & 0xffff;
601 s->ulpd_pm_regs[0x0c >> 2] = (ticks >> 16) & 0xffff;
602 if (ticks >> 32) /* OVERFLOW_HI_FREQ */
603 s->ulpd_pm_regs[0x14 >> 2] |= 1 << 1;
604
605 s->ulpd_pm_regs[0x14 >> 2] |= 1 << 0; /* IT_GAUGING */
606 qemu_irq_raise(s->irq[1][OMAP_INT_GAUGE_32K]);
607 }
608 }
609 s->ulpd_pm_regs[addr >> 2] = value;
610 break;
611
612 case 0x18: /* Reserved */
613 case 0x1c: /* Reserved */
614 case 0x20: /* Reserved */
615 case 0x28: /* Reserved */
616 case 0x2c: /* Reserved */
617 OMAP_BAD_REG(addr);
618 case 0x24: /* SETUP_ANALOG_CELL3_ULPD1 */
619 case 0x38: /* COUNTER_32_FIQ */
620 case 0x48: /* LOCL_TIME */
621 case 0x50: /* POWER_CTRL */
622 s->ulpd_pm_regs[addr >> 2] = value;
623 break;
624
625 case 0x30: /* CLOCK_CTRL */
626 diff = s->ulpd_pm_regs[addr >> 2] ^ value;
627 s->ulpd_pm_regs[addr >> 2] = value & 0x3f;
628 omap_ulpd_clk_update(s, diff, value);
629 break;
630
631 case 0x34: /* SOFT_REQ */
632 diff = s->ulpd_pm_regs[addr >> 2] ^ value;
633 s->ulpd_pm_regs[addr >> 2] = value & 0x1f;
634 omap_ulpd_req_update(s, diff, value);
635 break;
636
637 case 0x3c: /* DPLL_CTRL */
638 /* XXX: OMAP310 TRM claims bit 3 is PLL_ENABLE, and bit 4 is
639 * omitted altogether, probably a typo. */
640 /* This register has identical semantics with DPLL(1:3) control
641 * registers, see omap_dpll_write() */
642 diff = s->ulpd_pm_regs[addr >> 2] & value;
643 s->ulpd_pm_regs[addr >> 2] = value & 0x2fff;
644 if (diff & (0x3ff << 2)) {
645 if (value & (1 << 4)) { /* PLL_ENABLE */
646 div = ((value >> 5) & 3) + 1; /* PLL_DIV */
647 mult = MIN((value >> 7) & 0x1f, 1); /* PLL_MULT */
648 } else {
649 div = bypass_div[((value >> 2) & 3)]; /* BYPASS_DIV */
650 mult = 1;
651 }
652 omap_clk_setrate(omap_findclk(s, "dpll4"), div, mult);
653 }
654
655 /* Enter the desired mode. */
656 s->ulpd_pm_regs[addr >> 2] =
657 (s->ulpd_pm_regs[addr >> 2] & 0xfffe) |
658 ((s->ulpd_pm_regs[addr >> 2] >> 4) & 1);
659
660 /* Act as if the lock is restored. */
661 s->ulpd_pm_regs[addr >> 2] |= 2;
662 break;
663
664 case 0x4c: /* APLL_CTRL */
665 diff = s->ulpd_pm_regs[addr >> 2] & value;
666 s->ulpd_pm_regs[addr >> 2] = value & 0xf;
667 if (diff & (1 << 0)) /* APLL_NDPLL_SWITCH */
668 omap_clk_reparent(omap_findclk(s, "ck_48m"), omap_findclk(s,
669 (value & (1 << 0)) ? "apll" : "dpll4"));
670 break;
671
672 default:
673 OMAP_BAD_REG(addr);
674 }
675 }
676
677 static CPUReadMemoryFunc * const omap_ulpd_pm_readfn[] = {
678 omap_badwidth_read16,
679 omap_ulpd_pm_read,
680 omap_badwidth_read16,
681 };
682
683 static CPUWriteMemoryFunc * const omap_ulpd_pm_writefn[] = {
684 omap_badwidth_write16,
685 omap_ulpd_pm_write,
686 omap_badwidth_write16,
687 };
688
689 static void omap_ulpd_pm_reset(struct omap_mpu_state_s *mpu)
690 {
691 mpu->ulpd_pm_regs[0x00 >> 2] = 0x0001;
692 mpu->ulpd_pm_regs[0x04 >> 2] = 0x0000;
693 mpu->ulpd_pm_regs[0x08 >> 2] = 0x0001;
694 mpu->ulpd_pm_regs[0x0c >> 2] = 0x0000;
695 mpu->ulpd_pm_regs[0x10 >> 2] = 0x0000;
696 mpu->ulpd_pm_regs[0x18 >> 2] = 0x01;
697 mpu->ulpd_pm_regs[0x1c >> 2] = 0x01;
698 mpu->ulpd_pm_regs[0x20 >> 2] = 0x01;
699 mpu->ulpd_pm_regs[0x24 >> 2] = 0x03ff;
700 mpu->ulpd_pm_regs[0x28 >> 2] = 0x01;
701 mpu->ulpd_pm_regs[0x2c >> 2] = 0x01;
702 omap_ulpd_clk_update(mpu, mpu->ulpd_pm_regs[0x30 >> 2], 0x0000);
703 mpu->ulpd_pm_regs[0x30 >> 2] = 0x0000;
704 omap_ulpd_req_update(mpu, mpu->ulpd_pm_regs[0x34 >> 2], 0x0000);
705 mpu->ulpd_pm_regs[0x34 >> 2] = 0x0000;
706 mpu->ulpd_pm_regs[0x38 >> 2] = 0x0001;
707 mpu->ulpd_pm_regs[0x3c >> 2] = 0x2211;
708 mpu->ulpd_pm_regs[0x40 >> 2] = 0x0000; /* FIXME: dump a real STATUS_REQ */
709 mpu->ulpd_pm_regs[0x48 >> 2] = 0x960;
710 mpu->ulpd_pm_regs[0x4c >> 2] = 0x08;
711 mpu->ulpd_pm_regs[0x50 >> 2] = 0x08;
712 omap_clk_setrate(omap_findclk(mpu, "dpll4"), 1, 4);
713 omap_clk_reparent(omap_findclk(mpu, "ck_48m"), omap_findclk(mpu, "dpll4"));
714 }
715
716 static void omap_ulpd_pm_init(target_phys_addr_t base,
717 struct omap_mpu_state_s *mpu)
718 {
719 int iomemtype = cpu_register_io_memory(omap_ulpd_pm_readfn,
720 omap_ulpd_pm_writefn, mpu, DEVICE_NATIVE_ENDIAN);
721
722 cpu_register_physical_memory(base, 0x800, iomemtype);
723 omap_ulpd_pm_reset(mpu);
724 }
725
726 /* OMAP Pin Configuration */
727 static uint32_t omap_pin_cfg_read(void *opaque, target_phys_addr_t addr)
728 {
729 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
730
731 switch (addr) {
732 case 0x00: /* FUNC_MUX_CTRL_0 */
733 case 0x04: /* FUNC_MUX_CTRL_1 */
734 case 0x08: /* FUNC_MUX_CTRL_2 */
735 return s->func_mux_ctrl[addr >> 2];
736
737 case 0x0c: /* COMP_MODE_CTRL_0 */
738 return s->comp_mode_ctrl[0];
739
740 case 0x10: /* FUNC_MUX_CTRL_3 */
741 case 0x14: /* FUNC_MUX_CTRL_4 */
742 case 0x18: /* FUNC_MUX_CTRL_5 */
743 case 0x1c: /* FUNC_MUX_CTRL_6 */
744 case 0x20: /* FUNC_MUX_CTRL_7 */
745 case 0x24: /* FUNC_MUX_CTRL_8 */
746 case 0x28: /* FUNC_MUX_CTRL_9 */
747 case 0x2c: /* FUNC_MUX_CTRL_A */
748 case 0x30: /* FUNC_MUX_CTRL_B */
749 case 0x34: /* FUNC_MUX_CTRL_C */
750 case 0x38: /* FUNC_MUX_CTRL_D */
751 return s->func_mux_ctrl[(addr >> 2) - 1];
752
753 case 0x40: /* PULL_DWN_CTRL_0 */
754 case 0x44: /* PULL_DWN_CTRL_1 */
755 case 0x48: /* PULL_DWN_CTRL_2 */
756 case 0x4c: /* PULL_DWN_CTRL_3 */
757 return s->pull_dwn_ctrl[(addr & 0xf) >> 2];
758
759 case 0x50: /* GATE_INH_CTRL_0 */
760 return s->gate_inh_ctrl[0];
761
762 case 0x60: /* VOLTAGE_CTRL_0 */
763 return s->voltage_ctrl[0];
764
765 case 0x70: /* TEST_DBG_CTRL_0 */
766 return s->test_dbg_ctrl[0];
767
768 case 0x80: /* MOD_CONF_CTRL_0 */
769 return s->mod_conf_ctrl[0];
770 }
771
772 OMAP_BAD_REG(addr);
773 return 0;
774 }
775
776 static inline void omap_pin_funcmux0_update(struct omap_mpu_state_s *s,
777 uint32_t diff, uint32_t value)
778 {
779 if (s->compat1509) {
780 if (diff & (1 << 9)) /* BLUETOOTH */
781 omap_clk_onoff(omap_findclk(s, "bt_mclk_out"),
782 (~value >> 9) & 1);
783 if (diff & (1 << 7)) /* USB.CLKO */
784 omap_clk_onoff(omap_findclk(s, "usb.clko"),
785 (value >> 7) & 1);
786 }
787 }
788
789 static inline void omap_pin_funcmux1_update(struct omap_mpu_state_s *s,
790 uint32_t diff, uint32_t value)
791 {
792 if (s->compat1509) {
793 if (diff & (1 << 31)) /* MCBSP3_CLK_HIZ_DI */
794 omap_clk_onoff(omap_findclk(s, "mcbsp3.clkx"),
795 (value >> 31) & 1);
796 if (diff & (1 << 1)) /* CLK32K */
797 omap_clk_onoff(omap_findclk(s, "clk32k_out"),
798 (~value >> 1) & 1);
799 }
800 }
801
802 static inline void omap_pin_modconf1_update(struct omap_mpu_state_s *s,
803 uint32_t diff, uint32_t value)
804 {
805 if (diff & (1 << 31)) /* CONF_MOD_UART3_CLK_MODE_R */
806 omap_clk_reparent(omap_findclk(s, "uart3_ck"),
807 omap_findclk(s, ((value >> 31) & 1) ?
808 "ck_48m" : "armper_ck"));
809 if (diff & (1 << 30)) /* CONF_MOD_UART2_CLK_MODE_R */
810 omap_clk_reparent(omap_findclk(s, "uart2_ck"),
811 omap_findclk(s, ((value >> 30) & 1) ?
812 "ck_48m" : "armper_ck"));
813 if (diff & (1 << 29)) /* CONF_MOD_UART1_CLK_MODE_R */
814 omap_clk_reparent(omap_findclk(s, "uart1_ck"),
815 omap_findclk(s, ((value >> 29) & 1) ?
816 "ck_48m" : "armper_ck"));
817 if (diff & (1 << 23)) /* CONF_MOD_MMC_SD_CLK_REQ_R */
818 omap_clk_reparent(omap_findclk(s, "mmc_ck"),
819 omap_findclk(s, ((value >> 23) & 1) ?
820 "ck_48m" : "armper_ck"));
821 if (diff & (1 << 12)) /* CONF_MOD_COM_MCLK_12_48_S */
822 omap_clk_reparent(omap_findclk(s, "com_mclk_out"),
823 omap_findclk(s, ((value >> 12) & 1) ?
824 "ck_48m" : "armper_ck"));
825 if (diff & (1 << 9)) /* CONF_MOD_USB_HOST_HHC_UHO */
826 omap_clk_onoff(omap_findclk(s, "usb_hhc_ck"), (value >> 9) & 1);
827 }
828
829 static void omap_pin_cfg_write(void *opaque, target_phys_addr_t addr,
830 uint32_t value)
831 {
832 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
833 uint32_t diff;
834
835 switch (addr) {
836 case 0x00: /* FUNC_MUX_CTRL_0 */
837 diff = s->func_mux_ctrl[addr >> 2] ^ value;
838 s->func_mux_ctrl[addr >> 2] = value;
839 omap_pin_funcmux0_update(s, diff, value);
840 return;
841
842 case 0x04: /* FUNC_MUX_CTRL_1 */
843 diff = s->func_mux_ctrl[addr >> 2] ^ value;
844 s->func_mux_ctrl[addr >> 2] = value;
845 omap_pin_funcmux1_update(s, diff, value);
846 return;
847
848 case 0x08: /* FUNC_MUX_CTRL_2 */
849 s->func_mux_ctrl[addr >> 2] = value;
850 return;
851
852 case 0x0c: /* COMP_MODE_CTRL_0 */
853 s->comp_mode_ctrl[0] = value;
854 s->compat1509 = (value != 0x0000eaef);
855 omap_pin_funcmux0_update(s, ~0, s->func_mux_ctrl[0]);
856 omap_pin_funcmux1_update(s, ~0, s->func_mux_ctrl[1]);
857 return;
858
859 case 0x10: /* FUNC_MUX_CTRL_3 */
860 case 0x14: /* FUNC_MUX_CTRL_4 */
861 case 0x18: /* FUNC_MUX_CTRL_5 */
862 case 0x1c: /* FUNC_MUX_CTRL_6 */
863 case 0x20: /* FUNC_MUX_CTRL_7 */
864 case 0x24: /* FUNC_MUX_CTRL_8 */
865 case 0x28: /* FUNC_MUX_CTRL_9 */
866 case 0x2c: /* FUNC_MUX_CTRL_A */
867 case 0x30: /* FUNC_MUX_CTRL_B */
868 case 0x34: /* FUNC_MUX_CTRL_C */
869 case 0x38: /* FUNC_MUX_CTRL_D */
870 s->func_mux_ctrl[(addr >> 2) - 1] = value;
871 return;
872
873 case 0x40: /* PULL_DWN_CTRL_0 */
874 case 0x44: /* PULL_DWN_CTRL_1 */
875 case 0x48: /* PULL_DWN_CTRL_2 */
876 case 0x4c: /* PULL_DWN_CTRL_3 */
877 s->pull_dwn_ctrl[(addr & 0xf) >> 2] = value;
878 return;
879
880 case 0x50: /* GATE_INH_CTRL_0 */
881 s->gate_inh_ctrl[0] = value;
882 return;
883
884 case 0x60: /* VOLTAGE_CTRL_0 */
885 s->voltage_ctrl[0] = value;
886 return;
887
888 case 0x70: /* TEST_DBG_CTRL_0 */
889 s->test_dbg_ctrl[0] = value;
890 return;
891
892 case 0x80: /* MOD_CONF_CTRL_0 */
893 diff = s->mod_conf_ctrl[0] ^ value;
894 s->mod_conf_ctrl[0] = value;
895 omap_pin_modconf1_update(s, diff, value);
896 return;
897
898 default:
899 OMAP_BAD_REG(addr);
900 }
901 }
902
903 static CPUReadMemoryFunc * const omap_pin_cfg_readfn[] = {
904 omap_badwidth_read32,
905 omap_badwidth_read32,
906 omap_pin_cfg_read,
907 };
908
909 static CPUWriteMemoryFunc * const omap_pin_cfg_writefn[] = {
910 omap_badwidth_write32,
911 omap_badwidth_write32,
912 omap_pin_cfg_write,
913 };
914
915 static void omap_pin_cfg_reset(struct omap_mpu_state_s *mpu)
916 {
917 /* Start in Compatibility Mode. */
918 mpu->compat1509 = 1;
919 omap_pin_funcmux0_update(mpu, mpu->func_mux_ctrl[0], 0);
920 omap_pin_funcmux1_update(mpu, mpu->func_mux_ctrl[1], 0);
921 omap_pin_modconf1_update(mpu, mpu->mod_conf_ctrl[0], 0);
922 memset(mpu->func_mux_ctrl, 0, sizeof(mpu->func_mux_ctrl));
923 memset(mpu->comp_mode_ctrl, 0, sizeof(mpu->comp_mode_ctrl));
924 memset(mpu->pull_dwn_ctrl, 0, sizeof(mpu->pull_dwn_ctrl));
925 memset(mpu->gate_inh_ctrl, 0, sizeof(mpu->gate_inh_ctrl));
926 memset(mpu->voltage_ctrl, 0, sizeof(mpu->voltage_ctrl));
927 memset(mpu->test_dbg_ctrl, 0, sizeof(mpu->test_dbg_ctrl));
928 memset(mpu->mod_conf_ctrl, 0, sizeof(mpu->mod_conf_ctrl));
929 }
930
931 static void omap_pin_cfg_init(target_phys_addr_t base,
932 struct omap_mpu_state_s *mpu)
933 {
934 int iomemtype = cpu_register_io_memory(omap_pin_cfg_readfn,
935 omap_pin_cfg_writefn, mpu, DEVICE_NATIVE_ENDIAN);
936
937 cpu_register_physical_memory(base, 0x800, iomemtype);
938 omap_pin_cfg_reset(mpu);
939 }
940
941 /* Device Identification, Die Identification */
942 static uint32_t omap_id_read(void *opaque, target_phys_addr_t addr)
943 {
944 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
945
946 switch (addr) {
947 case 0xfffe1800: /* DIE_ID_LSB */
948 return 0xc9581f0e;
949 case 0xfffe1804: /* DIE_ID_MSB */
950 return 0xa8858bfa;
951
952 case 0xfffe2000: /* PRODUCT_ID_LSB */
953 return 0x00aaaafc;
954 case 0xfffe2004: /* PRODUCT_ID_MSB */
955 return 0xcafeb574;
956
957 case 0xfffed400: /* JTAG_ID_LSB */
958 switch (s->mpu_model) {
959 case omap310:
960 return 0x03310315;
961 case omap1510:
962 return 0x03310115;
963 default:
964 hw_error("%s: bad mpu model\n", __FUNCTION__);
965 }
966 break;
967
968 case 0xfffed404: /* JTAG_ID_MSB */
969 switch (s->mpu_model) {
970 case omap310:
971 return 0xfb57402f;
972 case omap1510:
973 return 0xfb47002f;
974 default:
975 hw_error("%s: bad mpu model\n", __FUNCTION__);
976 }
977 break;
978 }
979
980 OMAP_BAD_REG(addr);
981 return 0;
982 }
983
984 static void omap_id_write(void *opaque, target_phys_addr_t addr,
985 uint32_t value)
986 {
987 OMAP_BAD_REG(addr);
988 }
989
990 static CPUReadMemoryFunc * const omap_id_readfn[] = {
991 omap_badwidth_read32,
992 omap_badwidth_read32,
993 omap_id_read,
994 };
995
996 static CPUWriteMemoryFunc * const omap_id_writefn[] = {
997 omap_badwidth_write32,
998 omap_badwidth_write32,
999 omap_id_write,
1000 };
1001
1002 static void omap_id_init(struct omap_mpu_state_s *mpu)
1003 {
1004 int iomemtype = cpu_register_io_memory(omap_id_readfn,
1005 omap_id_writefn, mpu, DEVICE_NATIVE_ENDIAN);
1006 cpu_register_physical_memory_offset(0xfffe1800, 0x800, iomemtype, 0xfffe1800);
1007 cpu_register_physical_memory_offset(0xfffed400, 0x100, iomemtype, 0xfffed400);
1008 if (!cpu_is_omap15xx(mpu))
1009 cpu_register_physical_memory_offset(0xfffe2000, 0x800, iomemtype, 0xfffe2000);
1010 }
1011
1012 /* MPUI Control (Dummy) */
1013 static uint32_t omap_mpui_read(void *opaque, target_phys_addr_t addr)
1014 {
1015 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
1016
1017 switch (addr) {
1018 case 0x00: /* CTRL */
1019 return s->mpui_ctrl;
1020 case 0x04: /* DEBUG_ADDR */
1021 return 0x01ffffff;
1022 case 0x08: /* DEBUG_DATA */
1023 return 0xffffffff;
1024 case 0x0c: /* DEBUG_FLAG */
1025 return 0x00000800;
1026 case 0x10: /* STATUS */
1027 return 0x00000000;
1028
1029 /* Not in OMAP310 */
1030 case 0x14: /* DSP_STATUS */
1031 case 0x18: /* DSP_BOOT_CONFIG */
1032 return 0x00000000;
1033 case 0x1c: /* DSP_MPUI_CONFIG */
1034 return 0x0000ffff;
1035 }
1036
1037 OMAP_BAD_REG(addr);
1038 return 0;
1039 }
1040
1041 static void omap_mpui_write(void *opaque, target_phys_addr_t addr,
1042 uint32_t value)
1043 {
1044 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
1045
1046 switch (addr) {
1047 case 0x00: /* CTRL */
1048 s->mpui_ctrl = value & 0x007fffff;
1049 break;
1050
1051 case 0x04: /* DEBUG_ADDR */
1052 case 0x08: /* DEBUG_DATA */
1053 case 0x0c: /* DEBUG_FLAG */
1054 case 0x10: /* STATUS */
1055 /* Not in OMAP310 */
1056 case 0x14: /* DSP_STATUS */
1057 OMAP_RO_REG(addr);
1058 case 0x18: /* DSP_BOOT_CONFIG */
1059 case 0x1c: /* DSP_MPUI_CONFIG */
1060 break;
1061
1062 default:
1063 OMAP_BAD_REG(addr);
1064 }
1065 }
1066
1067 static CPUReadMemoryFunc * const omap_mpui_readfn[] = {
1068 omap_badwidth_read32,
1069 omap_badwidth_read32,
1070 omap_mpui_read,
1071 };
1072
1073 static CPUWriteMemoryFunc * const omap_mpui_writefn[] = {
1074 omap_badwidth_write32,
1075 omap_badwidth_write32,
1076 omap_mpui_write,
1077 };
1078
1079 static void omap_mpui_reset(struct omap_mpu_state_s *s)
1080 {
1081 s->mpui_ctrl = 0x0003ff1b;
1082 }
1083
1084 static void omap_mpui_init(target_phys_addr_t base,
1085 struct omap_mpu_state_s *mpu)
1086 {
1087 int iomemtype = cpu_register_io_memory(omap_mpui_readfn,
1088 omap_mpui_writefn, mpu, DEVICE_NATIVE_ENDIAN);
1089
1090 cpu_register_physical_memory(base, 0x100, iomemtype);
1091
1092 omap_mpui_reset(mpu);
1093 }
1094
1095 /* TIPB Bridges */
1096 struct omap_tipb_bridge_s {
1097 qemu_irq abort;
1098
1099 int width_intr;
1100 uint16_t control;
1101 uint16_t alloc;
1102 uint16_t buffer;
1103 uint16_t enh_control;
1104 };
1105
1106 static uint32_t omap_tipb_bridge_read(void *opaque, target_phys_addr_t addr)
1107 {
1108 struct omap_tipb_bridge_s *s = (struct omap_tipb_bridge_s *) opaque;
1109
1110 switch (addr) {
1111 case 0x00: /* TIPB_CNTL */
1112 return s->control;
1113 case 0x04: /* TIPB_BUS_ALLOC */
1114 return s->alloc;
1115 case 0x08: /* MPU_TIPB_CNTL */
1116 return s->buffer;
1117 case 0x0c: /* ENHANCED_TIPB_CNTL */
1118 return s->enh_control;
1119 case 0x10: /* ADDRESS_DBG */
1120 case 0x14: /* DATA_DEBUG_LOW */
1121 case 0x18: /* DATA_DEBUG_HIGH */
1122 return 0xffff;
1123 case 0x1c: /* DEBUG_CNTR_SIG */
1124 return 0x00f8;
1125 }
1126
1127 OMAP_BAD_REG(addr);
1128 return 0;
1129 }
1130
1131 static void omap_tipb_bridge_write(void *opaque, target_phys_addr_t addr,
1132 uint32_t value)
1133 {
1134 struct omap_tipb_bridge_s *s = (struct omap_tipb_bridge_s *) opaque;
1135
1136 switch (addr) {
1137 case 0x00: /* TIPB_CNTL */
1138 s->control = value & 0xffff;
1139 break;
1140
1141 case 0x04: /* TIPB_BUS_ALLOC */
1142 s->alloc = value & 0x003f;
1143 break;
1144
1145 case 0x08: /* MPU_TIPB_CNTL */
1146 s->buffer = value & 0x0003;
1147 break;
1148
1149 case 0x0c: /* ENHANCED_TIPB_CNTL */
1150 s->width_intr = !(value & 2);
1151 s->enh_control = value & 0x000f;
1152 break;
1153
1154 case 0x10: /* ADDRESS_DBG */
1155 case 0x14: /* DATA_DEBUG_LOW */
1156 case 0x18: /* DATA_DEBUG_HIGH */
1157 case 0x1c: /* DEBUG_CNTR_SIG */
1158 OMAP_RO_REG(addr);
1159 break;
1160
1161 default:
1162 OMAP_BAD_REG(addr);
1163 }
1164 }
1165
1166 static CPUReadMemoryFunc * const omap_tipb_bridge_readfn[] = {
1167 omap_badwidth_read16,
1168 omap_tipb_bridge_read,
1169 omap_tipb_bridge_read,
1170 };
1171
1172 static CPUWriteMemoryFunc * const omap_tipb_bridge_writefn[] = {
1173 omap_badwidth_write16,
1174 omap_tipb_bridge_write,
1175 omap_tipb_bridge_write,
1176 };
1177
1178 static void omap_tipb_bridge_reset(struct omap_tipb_bridge_s *s)
1179 {
1180 s->control = 0xffff;
1181 s->alloc = 0x0009;
1182 s->buffer = 0x0000;
1183 s->enh_control = 0x000f;
1184 }
1185
1186 static struct omap_tipb_bridge_s *omap_tipb_bridge_init(target_phys_addr_t base,
1187 qemu_irq abort_irq, omap_clk clk)
1188 {
1189 int iomemtype;
1190 struct omap_tipb_bridge_s *s = (struct omap_tipb_bridge_s *)
1191 qemu_mallocz(sizeof(struct omap_tipb_bridge_s));
1192
1193 s->abort = abort_irq;
1194 omap_tipb_bridge_reset(s);
1195
1196 iomemtype = cpu_register_io_memory(omap_tipb_bridge_readfn,
1197 omap_tipb_bridge_writefn, s, DEVICE_NATIVE_ENDIAN);
1198 cpu_register_physical_memory(base, 0x100, iomemtype);
1199
1200 return s;
1201 }
1202
1203 /* Dummy Traffic Controller's Memory Interface */
1204 static uint32_t omap_tcmi_read(void *opaque, target_phys_addr_t addr)
1205 {
1206 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
1207 uint32_t ret;
1208
1209 switch (addr) {
1210 case 0x00: /* IMIF_PRIO */
1211 case 0x04: /* EMIFS_PRIO */
1212 case 0x08: /* EMIFF_PRIO */
1213 case 0x0c: /* EMIFS_CONFIG */
1214 case 0x10: /* EMIFS_CS0_CONFIG */
1215 case 0x14: /* EMIFS_CS1_CONFIG */
1216 case 0x18: /* EMIFS_CS2_CONFIG */
1217 case 0x1c: /* EMIFS_CS3_CONFIG */
1218 case 0x24: /* EMIFF_MRS */
1219 case 0x28: /* TIMEOUT1 */
1220 case 0x2c: /* TIMEOUT2 */
1221 case 0x30: /* TIMEOUT3 */
1222 case 0x3c: /* EMIFF_SDRAM_CONFIG_2 */
1223 case 0x40: /* EMIFS_CFG_DYN_WAIT */
1224 return s->tcmi_regs[addr >> 2];
1225
1226 case 0x20: /* EMIFF_SDRAM_CONFIG */
1227 ret = s->tcmi_regs[addr >> 2];
1228 s->tcmi_regs[addr >> 2] &= ~1; /* XXX: Clear SLRF on SDRAM access */
1229 /* XXX: We can try using the VGA_DIRTY flag for this */
1230 return ret;
1231 }
1232
1233 OMAP_BAD_REG(addr);
1234 return 0;
1235 }
1236
1237 static void omap_tcmi_write(void *opaque, target_phys_addr_t addr,
1238 uint32_t value)
1239 {
1240 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
1241
1242 switch (addr) {
1243 case 0x00: /* IMIF_PRIO */
1244 case 0x04: /* EMIFS_PRIO */
1245 case 0x08: /* EMIFF_PRIO */
1246 case 0x10: /* EMIFS_CS0_CONFIG */
1247 case 0x14: /* EMIFS_CS1_CONFIG */
1248 case 0x18: /* EMIFS_CS2_CONFIG */
1249 case 0x1c: /* EMIFS_CS3_CONFIG */
1250 case 0x20: /* EMIFF_SDRAM_CONFIG */
1251 case 0x24: /* EMIFF_MRS */
1252 case 0x28: /* TIMEOUT1 */
1253 case 0x2c: /* TIMEOUT2 */
1254 case 0x30: /* TIMEOUT3 */
1255 case 0x3c: /* EMIFF_SDRAM_CONFIG_2 */
1256 case 0x40: /* EMIFS_CFG_DYN_WAIT */
1257 s->tcmi_regs[addr >> 2] = value;
1258 break;
1259 case 0x0c: /* EMIFS_CONFIG */
1260 s->tcmi_regs[addr >> 2] = (value & 0xf) | (1 << 4);
1261 break;
1262
1263 default:
1264 OMAP_BAD_REG(addr);
1265 }
1266 }
1267
1268 static CPUReadMemoryFunc * const omap_tcmi_readfn[] = {
1269 omap_badwidth_read32,
1270 omap_badwidth_read32,
1271 omap_tcmi_read,
1272 };
1273
1274 static CPUWriteMemoryFunc * const omap_tcmi_writefn[] = {
1275 omap_badwidth_write32,
1276 omap_badwidth_write32,
1277 omap_tcmi_write,
1278 };
1279
1280 static void omap_tcmi_reset(struct omap_mpu_state_s *mpu)
1281 {
1282 mpu->tcmi_regs[0x00 >> 2] = 0x00000000;
1283 mpu->tcmi_regs[0x04 >> 2] = 0x00000000;
1284 mpu->tcmi_regs[0x08 >> 2] = 0x00000000;
1285 mpu->tcmi_regs[0x0c >> 2] = 0x00000010;
1286 mpu->tcmi_regs[0x10 >> 2] = 0x0010fffb;
1287 mpu->tcmi_regs[0x14 >> 2] = 0x0010fffb;
1288 mpu->tcmi_regs[0x18 >> 2] = 0x0010fffb;
1289 mpu->tcmi_regs[0x1c >> 2] = 0x0010fffb;
1290 mpu->tcmi_regs[0x20 >> 2] = 0x00618800;
1291 mpu->tcmi_regs[0x24 >> 2] = 0x00000037;
1292 mpu->tcmi_regs[0x28 >> 2] = 0x00000000;
1293 mpu->tcmi_regs[0x2c >> 2] = 0x00000000;
1294 mpu->tcmi_regs[0x30 >> 2] = 0x00000000;
1295 mpu->tcmi_regs[0x3c >> 2] = 0x00000003;
1296 mpu->tcmi_regs[0x40 >> 2] = 0x00000000;
1297 }
1298
1299 static void omap_tcmi_init(target_phys_addr_t base,
1300 struct omap_mpu_state_s *mpu)
1301 {
1302 int iomemtype = cpu_register_io_memory(omap_tcmi_readfn,
1303 omap_tcmi_writefn, mpu, DEVICE_NATIVE_ENDIAN);
1304
1305 cpu_register_physical_memory(base, 0x100, iomemtype);
1306 omap_tcmi_reset(mpu);
1307 }
1308
1309 /* Digital phase-locked loops control */
1310 static uint32_t omap_dpll_read(void *opaque, target_phys_addr_t addr)
1311 {
1312 struct dpll_ctl_s *s = (struct dpll_ctl_s *) opaque;
1313
1314 if (addr == 0x00) /* CTL_REG */
1315 return s->mode;
1316
1317 OMAP_BAD_REG(addr);
1318 return 0;
1319 }
1320
1321 static void omap_dpll_write(void *opaque, target_phys_addr_t addr,
1322 uint32_t value)
1323 {
1324 struct dpll_ctl_s *s = (struct dpll_ctl_s *) opaque;
1325 uint16_t diff;
1326 static const int bypass_div[4] = { 1, 2, 4, 4 };
1327 int div, mult;
1328
1329 if (addr == 0x00) { /* CTL_REG */
1330 /* See omap_ulpd_pm_write() too */
1331 diff = s->mode & value;
1332 s->mode = value & 0x2fff;
1333 if (diff & (0x3ff << 2)) {
1334 if (value & (1 << 4)) { /* PLL_ENABLE */
1335 div = ((value >> 5) & 3) + 1; /* PLL_DIV */
1336 mult = MIN((value >> 7) & 0x1f, 1); /* PLL_MULT */
1337 } else {
1338 div = bypass_div[((value >> 2) & 3)]; /* BYPASS_DIV */
1339 mult = 1;
1340 }
1341 omap_clk_setrate(s->dpll, div, mult);
1342 }
1343
1344 /* Enter the desired mode. */
1345 s->mode = (s->mode & 0xfffe) | ((s->mode >> 4) & 1);
1346
1347 /* Act as if the lock is restored. */
1348 s->mode |= 2;
1349 } else {
1350 OMAP_BAD_REG(addr);
1351 }
1352 }
1353
1354 static CPUReadMemoryFunc * const omap_dpll_readfn[] = {
1355 omap_badwidth_read16,
1356 omap_dpll_read,
1357 omap_badwidth_read16,
1358 };
1359
1360 static CPUWriteMemoryFunc * const omap_dpll_writefn[] = {
1361 omap_badwidth_write16,
1362 omap_dpll_write,
1363 omap_badwidth_write16,
1364 };
1365
1366 static void omap_dpll_reset(struct dpll_ctl_s *s)
1367 {
1368 s->mode = 0x2002;
1369 omap_clk_setrate(s->dpll, 1, 1);
1370 }
1371
1372 static void omap_dpll_init(struct dpll_ctl_s *s, target_phys_addr_t base,
1373 omap_clk clk)
1374 {
1375 int iomemtype = cpu_register_io_memory(omap_dpll_readfn,
1376 omap_dpll_writefn, s, DEVICE_NATIVE_ENDIAN);
1377
1378 s->dpll = clk;
1379 omap_dpll_reset(s);
1380
1381 cpu_register_physical_memory(base, 0x100, iomemtype);
1382 }
1383
1384 /* MPU Clock/Reset/Power Mode Control */
1385 static uint32_t omap_clkm_read(void *opaque, target_phys_addr_t addr)
1386 {
1387 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
1388
1389 switch (addr) {
1390 case 0x00: /* ARM_CKCTL */
1391 return s->clkm.arm_ckctl;
1392
1393 case 0x04: /* ARM_IDLECT1 */
1394 return s->clkm.arm_idlect1;
1395
1396 case 0x08: /* ARM_IDLECT2 */
1397 return s->clkm.arm_idlect2;
1398
1399 case 0x0c: /* ARM_EWUPCT */
1400 return s->clkm.arm_ewupct;
1401
1402 case 0x10: /* ARM_RSTCT1 */
1403 return s->clkm.arm_rstct1;
1404
1405 case 0x14: /* ARM_RSTCT2 */
1406 return s->clkm.arm_rstct2;
1407
1408 case 0x18: /* ARM_SYSST */
1409 return (s->clkm.clocking_scheme << 11) | s->clkm.cold_start;
1410
1411 case 0x1c: /* ARM_CKOUT1 */
1412 return s->clkm.arm_ckout1;
1413
1414 case 0x20: /* ARM_CKOUT2 */
1415 break;
1416 }
1417
1418 OMAP_BAD_REG(addr);
1419 return 0;
1420 }
1421
1422 static inline void omap_clkm_ckctl_update(struct omap_mpu_state_s *s,
1423 uint16_t diff, uint16_t value)
1424 {
1425 omap_clk clk;
1426
1427 if (diff & (1 << 14)) { /* ARM_INTHCK_SEL */
1428 if (value & (1 << 14))
1429 /* Reserved */;
1430 else {
1431 clk = omap_findclk(s, "arminth_ck");
1432 omap_clk_reparent(clk, omap_findclk(s, "tc_ck"));
1433 }
1434 }
1435 if (diff & (1 << 12)) { /* ARM_TIMXO */
1436 clk = omap_findclk(s, "armtim_ck");
1437 if (value & (1 << 12))
1438 omap_clk_reparent(clk, omap_findclk(s, "clkin"));
1439 else
1440 omap_clk_reparent(clk, omap_findclk(s, "ck_gen1"));
1441 }
1442 /* XXX: en_dspck */
1443 if (diff & (3 << 10)) { /* DSPMMUDIV */
1444 clk = omap_findclk(s, "dspmmu_ck");
1445 omap_clk_setrate(clk, 1 << ((value >> 10) & 3), 1);
1446 }
1447 if (diff & (3 << 8)) { /* TCDIV */
1448 clk = omap_findclk(s, "tc_ck");
1449 omap_clk_setrate(clk, 1 << ((value >> 8) & 3), 1);
1450 }
1451 if (diff & (3 << 6)) { /* DSPDIV */
1452 clk = omap_findclk(s, "dsp_ck");
1453 omap_clk_setrate(clk, 1 << ((value >> 6) & 3), 1);
1454 }
1455 if (diff & (3 << 4)) { /* ARMDIV */
1456 clk = omap_findclk(s, "arm_ck");
1457 omap_clk_setrate(clk, 1 << ((value >> 4) & 3), 1);
1458 }
1459 if (diff & (3 << 2)) { /* LCDDIV */
1460 clk = omap_findclk(s, "lcd_ck");
1461 omap_clk_setrate(clk, 1 << ((value >> 2) & 3), 1);
1462 }
1463 if (diff & (3 << 0)) { /* PERDIV */
1464 clk = omap_findclk(s, "armper_ck");
1465 omap_clk_setrate(clk, 1 << ((value >> 0) & 3), 1);
1466 }
1467 }
1468
1469 static inline void omap_clkm_idlect1_update(struct omap_mpu_state_s *s,
1470 uint16_t diff, uint16_t value)
1471 {
1472 omap_clk clk;
1473
1474 if (value & (1 << 11)) /* SETARM_IDLE */
1475 cpu_interrupt(s->env, CPU_INTERRUPT_HALT);
1476 if (!(value & (1 << 10))) /* WKUP_MODE */
1477 qemu_system_shutdown_request(); /* XXX: disable wakeup from IRQ */
1478
1479 #define SET_CANIDLE(clock, bit) \
1480 if (diff & (1 << bit)) { \
1481 clk = omap_findclk(s, clock); \
1482 omap_clk_canidle(clk, (value >> bit) & 1); \
1483 }
1484 SET_CANIDLE("mpuwd_ck", 0) /* IDLWDT_ARM */
1485 SET_CANIDLE("armxor_ck", 1) /* IDLXORP_ARM */
1486 SET_CANIDLE("mpuper_ck", 2) /* IDLPER_ARM */
1487 SET_CANIDLE("lcd_ck", 3) /* IDLLCD_ARM */
1488 SET_CANIDLE("lb_ck", 4) /* IDLLB_ARM */
1489 SET_CANIDLE("hsab_ck", 5) /* IDLHSAB_ARM */
1490 SET_CANIDLE("tipb_ck", 6) /* IDLIF_ARM */
1491 SET_CANIDLE("dma_ck", 6) /* IDLIF_ARM */
1492 SET_CANIDLE("tc_ck", 6) /* IDLIF_ARM */
1493 SET_CANIDLE("dpll1", 7) /* IDLDPLL_ARM */
1494 SET_CANIDLE("dpll2", 7) /* IDLDPLL_ARM */
1495 SET_CANIDLE("dpll3", 7) /* IDLDPLL_ARM */
1496 SET_CANIDLE("mpui_ck", 8) /* IDLAPI_ARM */
1497 SET_CANIDLE("armtim_ck", 9) /* IDLTIM_ARM */
1498 }
1499
1500 static inline void omap_clkm_idlect2_update(struct omap_mpu_state_s *s,
1501 uint16_t diff, uint16_t value)
1502 {
1503 omap_clk clk;
1504
1505 #define SET_ONOFF(clock, bit) \
1506 if (diff & (1 << bit)) { \
1507 clk = omap_findclk(s, clock); \
1508 omap_clk_onoff(clk, (value >> bit) & 1); \
1509 }
1510 SET_ONOFF("mpuwd_ck", 0) /* EN_WDTCK */
1511 SET_ONOFF("armxor_ck", 1) /* EN_XORPCK */
1512 SET_ONOFF("mpuper_ck", 2) /* EN_PERCK */
1513 SET_ONOFF("lcd_ck", 3) /* EN_LCDCK */
1514 SET_ONOFF("lb_ck", 4) /* EN_LBCK */
1515 SET_ONOFF("hsab_ck", 5) /* EN_HSABCK */
1516 SET_ONOFF("mpui_ck", 6) /* EN_APICK */
1517 SET_ONOFF("armtim_ck", 7) /* EN_TIMCK */
1518 SET_CANIDLE("dma_ck", 8) /* DMACK_REQ */
1519 SET_ONOFF("arm_gpio_ck", 9) /* EN_GPIOCK */
1520 SET_ONOFF("lbfree_ck", 10) /* EN_LBFREECK */
1521 }
1522
1523 static inline void omap_clkm_ckout1_update(struct omap_mpu_state_s *s,
1524 uint16_t diff, uint16_t value)
1525 {
1526 omap_clk clk;
1527
1528 if (diff & (3 << 4)) { /* TCLKOUT */
1529 clk = omap_findclk(s, "tclk_out");
1530 switch ((value >> 4) & 3) {
1531 case 1:
1532 omap_clk_reparent(clk, omap_findclk(s, "ck_gen3"));
1533 omap_clk_onoff(clk, 1);
1534 break;
1535 case 2:
1536 omap_clk_reparent(clk, omap_findclk(s, "tc_ck"));
1537 omap_clk_onoff(clk, 1);
1538 break;
1539 default:
1540 omap_clk_onoff(clk, 0);
1541 }
1542 }
1543 if (diff & (3 << 2)) { /* DCLKOUT */
1544 clk = omap_findclk(s, "dclk_out");
1545 switch ((value >> 2) & 3) {
1546 case 0:
1547 omap_clk_reparent(clk, omap_findclk(s, "dspmmu_ck"));
1548 break;
1549 case 1:
1550 omap_clk_reparent(clk, omap_findclk(s, "ck_gen2"));
1551 break;
1552 case 2:
1553 omap_clk_reparent(clk, omap_findclk(s, "dsp_ck"));
1554 break;
1555 case 3:
1556 omap_clk_reparent(clk, omap_findclk(s, "ck_ref14"));
1557 break;
1558 }
1559 }
1560 if (diff & (3 << 0)) { /* ACLKOUT */
1561 clk = omap_findclk(s, "aclk_out");
1562 switch ((value >> 0) & 3) {
1563 case 1:
1564 omap_clk_reparent(clk, omap_findclk(s, "ck_gen1"));
1565 omap_clk_onoff(clk, 1);
1566 break;
1567 case 2:
1568 omap_clk_reparent(clk, omap_findclk(s, "arm_ck"));
1569 omap_clk_onoff(clk, 1);
1570 break;
1571 case 3:
1572 omap_clk_reparent(clk, omap_findclk(s, "ck_ref14"));
1573 omap_clk_onoff(clk, 1);
1574 break;
1575 default:
1576 omap_clk_onoff(clk, 0);
1577 }
1578 }
1579 }
1580
1581 static void omap_clkm_write(void *opaque, target_phys_addr_t addr,
1582 uint32_t value)
1583 {
1584 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
1585 uint16_t diff;
1586 omap_clk clk;
1587 static const char *clkschemename[8] = {
1588 "fully synchronous", "fully asynchronous", "synchronous scalable",
1589 "mix mode 1", "mix mode 2", "bypass mode", "mix mode 3", "mix mode 4",
1590 };
1591
1592 switch (addr) {
1593 case 0x00: /* ARM_CKCTL */
1594 diff = s->clkm.arm_ckctl ^ value;
1595 s->clkm.arm_ckctl = value & 0x7fff;
1596 omap_clkm_ckctl_update(s, diff, value);
1597 return;
1598
1599 case 0x04: /* ARM_IDLECT1 */
1600 diff = s->clkm.arm_idlect1 ^ value;
1601 s->clkm.arm_idlect1 = value & 0x0fff;
1602 omap_clkm_idlect1_update(s, diff, value);
1603 return;
1604
1605 case 0x08: /* ARM_IDLECT2 */
1606 diff = s->clkm.arm_idlect2 ^ value;
1607 s->clkm.arm_idlect2 = value & 0x07ff;
1608 omap_clkm_idlect2_update(s, diff, value);
1609 return;
1610
1611 case 0x0c: /* ARM_EWUPCT */
1612 s->clkm.arm_ewupct = value & 0x003f;
1613 return;
1614
1615 case 0x10: /* ARM_RSTCT1 */
1616 diff = s->clkm.arm_rstct1 ^ value;
1617 s->clkm.arm_rstct1 = value & 0x0007;
1618 if (value & 9) {
1619 qemu_system_reset_request();
1620 s->clkm.cold_start = 0xa;
1621 }
1622 if (diff & ~value & 4) { /* DSP_RST */
1623 omap_mpui_reset(s);
1624 omap_tipb_bridge_reset(s->private_tipb);
1625 omap_tipb_bridge_reset(s->public_tipb);
1626 }
1627 if (diff & 2) { /* DSP_EN */
1628 clk = omap_findclk(s, "dsp_ck");
1629 omap_clk_canidle(clk, (~value >> 1) & 1);
1630 }
1631 return;
1632
1633 case 0x14: /* ARM_RSTCT2 */
1634 s->clkm.arm_rstct2 = value & 0x0001;
1635 return;
1636
1637 case 0x18: /* ARM_SYSST */
1638 if ((s->clkm.clocking_scheme ^ (value >> 11)) & 7) {
1639 s->clkm.clocking_scheme = (value >> 11) & 7;
1640 printf("%s: clocking scheme set to %s\n", __FUNCTION__,
1641 clkschemename[s->clkm.clocking_scheme]);
1642 }
1643 s->clkm.cold_start &= value & 0x3f;
1644 return;
1645
1646 case 0x1c: /* ARM_CKOUT1 */
1647 diff = s->clkm.arm_ckout1 ^ value;
1648 s->clkm.arm_ckout1 = value & 0x003f;
1649 omap_clkm_ckout1_update(s, diff, value);
1650 return;
1651
1652 case 0x20: /* ARM_CKOUT2 */
1653 default:
1654 OMAP_BAD_REG(addr);
1655 }
1656 }
1657
1658 static CPUReadMemoryFunc * const omap_clkm_readfn[] = {
1659 omap_badwidth_read16,
1660 omap_clkm_read,
1661 omap_badwidth_read16,
1662 };
1663
1664 static CPUWriteMemoryFunc * const omap_clkm_writefn[] = {
1665 omap_badwidth_write16,
1666 omap_clkm_write,
1667 omap_badwidth_write16,
1668 };
1669
1670 static uint32_t omap_clkdsp_read(void *opaque, target_phys_addr_t addr)
1671 {
1672 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
1673
1674 switch (addr) {
1675 case 0x04: /* DSP_IDLECT1 */
1676 return s->clkm.dsp_idlect1;
1677
1678 case 0x08: /* DSP_IDLECT2 */
1679 return s->clkm.dsp_idlect2;
1680
1681 case 0x14: /* DSP_RSTCT2 */
1682 return s->clkm.dsp_rstct2;
1683
1684 case 0x18: /* DSP_SYSST */
1685 return (s->clkm.clocking_scheme << 11) | s->clkm.cold_start |
1686 (s->env->halted << 6); /* Quite useless... */
1687 }
1688
1689 OMAP_BAD_REG(addr);
1690 return 0;
1691 }
1692
1693 static inline void omap_clkdsp_idlect1_update(struct omap_mpu_state_s *s,
1694 uint16_t diff, uint16_t value)
1695 {
1696 omap_clk clk;
1697
1698 SET_CANIDLE("dspxor_ck", 1); /* IDLXORP_DSP */
1699 }
1700
1701 static inline void omap_clkdsp_idlect2_update(struct omap_mpu_state_s *s,
1702 uint16_t diff, uint16_t value)
1703 {
1704 omap_clk clk;
1705
1706 SET_ONOFF("dspxor_ck", 1); /* EN_XORPCK */
1707 }
1708
1709 static void omap_clkdsp_write(void *opaque, target_phys_addr_t addr,
1710 uint32_t value)
1711 {
1712 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
1713 uint16_t diff;
1714
1715 switch (addr) {
1716 case 0x04: /* DSP_IDLECT1 */
1717 diff = s->clkm.dsp_idlect1 ^ value;
1718 s->clkm.dsp_idlect1 = value & 0x01f7;
1719 omap_clkdsp_idlect1_update(s, diff, value);
1720 break;
1721
1722 case 0x08: /* DSP_IDLECT2 */
1723 s->clkm.dsp_idlect2 = value & 0x0037;
1724 diff = s->clkm.dsp_idlect1 ^ value;
1725 omap_clkdsp_idlect2_update(s, diff, value);
1726 break;
1727
1728 case 0x14: /* DSP_RSTCT2 */
1729 s->clkm.dsp_rstct2 = value & 0x0001;
1730 break;
1731
1732 case 0x18: /* DSP_SYSST */
1733 s->clkm.cold_start &= value & 0x3f;
1734 break;
1735
1736 default:
1737 OMAP_BAD_REG(addr);
1738 }
1739 }
1740
1741 static CPUReadMemoryFunc * const omap_clkdsp_readfn[] = {
1742 omap_badwidth_read16,
1743 omap_clkdsp_read,
1744 omap_badwidth_read16,
1745 };
1746
1747 static CPUWriteMemoryFunc * const omap_clkdsp_writefn[] = {
1748 omap_badwidth_write16,
1749 omap_clkdsp_write,
1750 omap_badwidth_write16,
1751 };
1752
1753 static void omap_clkm_reset(struct omap_mpu_state_s *s)
1754 {
1755 if (s->wdt && s->wdt->reset)
1756 s->clkm.cold_start = 0x6;
1757 s->clkm.clocking_scheme = 0;
1758 omap_clkm_ckctl_update(s, ~0, 0x3000);
1759 s->clkm.arm_ckctl = 0x3000;
1760 omap_clkm_idlect1_update(s, s->clkm.arm_idlect1 ^ 0x0400, 0x0400);
1761 s->clkm.arm_idlect1 = 0x0400;
1762 omap_clkm_idlect2_update(s, s->clkm.arm_idlect2 ^ 0x0100, 0x0100);
1763 s->clkm.arm_idlect2 = 0x0100;
1764 s->clkm.arm_ewupct = 0x003f;
1765 s->clkm.arm_rstct1 = 0x0000;
1766 s->clkm.arm_rstct2 = 0x0000;
1767 s->clkm.arm_ckout1 = 0x0015;
1768 s->clkm.dpll1_mode = 0x2002;
1769 omap_clkdsp_idlect1_update(s, s->clkm.dsp_idlect1 ^ 0x0040, 0x0040);
1770 s->clkm.dsp_idlect1 = 0x0040;
1771 omap_clkdsp_idlect2_update(s, ~0, 0x0000);
1772 s->clkm.dsp_idlect2 = 0x0000;
1773 s->clkm.dsp_rstct2 = 0x0000;
1774 }
1775
1776 static void omap_clkm_init(target_phys_addr_t mpu_base,
1777 target_phys_addr_t dsp_base, struct omap_mpu_state_s *s)
1778 {
1779 int iomemtype[2] = {
1780 cpu_register_io_memory(omap_clkm_readfn, omap_clkm_writefn, s,
1781 DEVICE_NATIVE_ENDIAN),
1782 cpu_register_io_memory(omap_clkdsp_readfn, omap_clkdsp_writefn, s,
1783 DEVICE_NATIVE_ENDIAN),
1784 };
1785
1786 s->clkm.arm_idlect1 = 0x03ff;
1787 s->clkm.arm_idlect2 = 0x0100;
1788 s->clkm.dsp_idlect1 = 0x0002;
1789 omap_clkm_reset(s);
1790 s->clkm.cold_start = 0x3a;
1791
1792 cpu_register_physical_memory(mpu_base, 0x100, iomemtype[0]);
1793 cpu_register_physical_memory(dsp_base, 0x1000, iomemtype[1]);
1794 }
1795
1796 /* MPU I/O */
1797 struct omap_mpuio_s {
1798 qemu_irq irq;
1799 qemu_irq kbd_irq;
1800 qemu_irq *in;
1801 qemu_irq handler[16];
1802 qemu_irq wakeup;
1803
1804 uint16_t inputs;
1805 uint16_t outputs;
1806 uint16_t dir;
1807 uint16_t edge;
1808 uint16_t mask;
1809 uint16_t ints;
1810
1811 uint16_t debounce;
1812 uint16_t latch;
1813 uint8_t event;
1814
1815 uint8_t buttons[5];
1816 uint8_t row_latch;
1817 uint8_t cols;
1818 int kbd_mask;
1819 int clk;
1820 };
1821
1822 static void omap_mpuio_set(void *opaque, int line, int level)
1823 {
1824 struct omap_mpuio_s *s = (struct omap_mpuio_s *) opaque;
1825 uint16_t prev = s->inputs;
1826
1827 if (level)
1828 s->inputs |= 1 << line;
1829 else
1830 s->inputs &= ~(1 << line);
1831
1832 if (((1 << line) & s->dir & ~s->mask) && s->clk) {
1833 if ((s->edge & s->inputs & ~prev) | (~s->edge & ~s->inputs & prev)) {
1834 s->ints |= 1 << line;
1835 qemu_irq_raise(s->irq);
1836 /* TODO: wakeup */
1837 }
1838 if ((s->event & (1 << 0)) && /* SET_GPIO_EVENT_MODE */
1839 (s->event >> 1) == line) /* PIN_SELECT */
1840 s->latch = s->inputs;
1841 }
1842 }
1843
1844 static void omap_mpuio_kbd_update(struct omap_mpuio_s *s)
1845 {
1846 int i;
1847 uint8_t *row, rows = 0, cols = ~s->cols;
1848
1849 for (row = s->buttons + 4, i = 1 << 4; i; row --, i >>= 1)
1850 if (*row & cols)
1851 rows |= i;
1852
1853 qemu_set_irq(s->kbd_irq, rows && !s->kbd_mask && s->clk);
1854 s->row_latch = ~rows;
1855 }
1856
1857 static uint32_t omap_mpuio_read(void *opaque, target_phys_addr_t addr)
1858 {
1859 struct omap_mpuio_s *s = (struct omap_mpuio_s *) opaque;
1860 int offset = addr & OMAP_MPUI_REG_MASK;
1861 uint16_t ret;
1862
1863 switch (offset) {
1864 case 0x00: /* INPUT_LATCH */
1865 return s->inputs;
1866
1867 case 0x04: /* OUTPUT_REG */
1868 return s->outputs;
1869
1870 case 0x08: /* IO_CNTL */
1871 return s->dir;
1872
1873 case 0x10: /* KBR_LATCH */
1874 return s->row_latch;
1875
1876 case 0x14: /* KBC_REG */
1877 return s->cols;
1878
1879 case 0x18: /* GPIO_EVENT_MODE_REG */
1880 return s->event;
1881
1882 case 0x1c: /* GPIO_INT_EDGE_REG */
1883 return s->edge;
1884
1885 case 0x20: /* KBD_INT */
1886 return (~s->row_latch & 0x1f) && !s->kbd_mask;
1887
1888 case 0x24: /* GPIO_INT */
1889 ret = s->ints;
1890 s->ints &= s->mask;
1891 if (ret)
1892 qemu_irq_lower(s->irq);
1893 return ret;
1894
1895 case 0x28: /* KBD_MASKIT */
1896 return s->kbd_mask;
1897
1898 case 0x2c: /* GPIO_MASKIT */
1899 return s->mask;
1900
1901 case 0x30: /* GPIO_DEBOUNCING_REG */
1902 return s->debounce;
1903
1904 case 0x34: /* GPIO_LATCH_REG */
1905 return s->latch;
1906 }
1907
1908 OMAP_BAD_REG(addr);
1909 return 0;
1910 }
1911
1912 static void omap_mpuio_write(void *opaque, target_phys_addr_t addr,
1913 uint32_t value)
1914 {
1915 struct omap_mpuio_s *s = (struct omap_mpuio_s *) opaque;
1916 int offset = addr & OMAP_MPUI_REG_MASK;
1917 uint16_t diff;
1918 int ln;
1919
1920 switch (offset) {
1921 case 0x04: /* OUTPUT_REG */
1922 diff = (s->outputs ^ value) & ~s->dir;
1923 s->outputs = value;
1924 while ((ln = ffs(diff))) {
1925 ln --;
1926 if (s->handler[ln])
1927 qemu_set_irq(s->handler[ln], (value >> ln) & 1);
1928 diff &= ~(1 << ln);
1929 }
1930 break;
1931
1932 case 0x08: /* IO_CNTL */
1933 diff = s->outputs & (s->dir ^ value);
1934 s->dir = value;
1935
1936 value = s->outputs & ~s->dir;
1937 while ((ln = ffs(diff))) {
1938 ln --;
1939 if (s->handler[ln])
1940 qemu_set_irq(s->handler[ln], (value >> ln) & 1);
1941 diff &= ~(1 << ln);
1942 }
1943 break;
1944
1945 case 0x14: /* KBC_REG */
1946 s->cols = value;
1947 omap_mpuio_kbd_update(s);
1948 break;
1949
1950 case 0x18: /* GPIO_EVENT_MODE_REG */
1951 s->event = value & 0x1f;
1952 break;
1953
1954 case 0x1c: /* GPIO_INT_EDGE_REG */
1955 s->edge = value;
1956 break;
1957
1958 case 0x28: /* KBD_MASKIT */
1959 s->kbd_mask = value & 1;
1960 omap_mpuio_kbd_update(s);
1961 break;
1962
1963 case 0x2c: /* GPIO_MASKIT */
1964 s->mask = value;
1965 break;
1966
1967 case 0x30: /* GPIO_DEBOUNCING_REG */
1968 s->debounce = value & 0x1ff;
1969 break;
1970
1971 case 0x00: /* INPUT_LATCH */
1972 case 0x10: /* KBR_LATCH */
1973 case 0x20: /* KBD_INT */
1974 case 0x24: /* GPIO_INT */
1975 case 0x34: /* GPIO_LATCH_REG */
1976 OMAP_RO_REG(addr);
1977 return;
1978
1979 default:
1980 OMAP_BAD_REG(addr);
1981 return;
1982 }
1983 }
1984
1985 static CPUReadMemoryFunc * const omap_mpuio_readfn[] = {
1986 omap_badwidth_read16,
1987 omap_mpuio_read,
1988 omap_badwidth_read16,
1989 };
1990
1991 static CPUWriteMemoryFunc * const omap_mpuio_writefn[] = {
1992 omap_badwidth_write16,
1993 omap_mpuio_write,
1994 omap_badwidth_write16,
1995 };
1996
1997 static void omap_mpuio_reset(struct omap_mpuio_s *s)
1998 {
1999 s->inputs = 0;
2000 s->outputs = 0;
2001 s->dir = ~0;
2002 s->event = 0;
2003 s->edge = 0;
2004 s->kbd_mask = 0;
2005 s->mask = 0;
2006 s->debounce = 0;
2007 s->latch = 0;
2008 s->ints = 0;
2009 s->row_latch = 0x1f;
2010 s->clk = 1;
2011 }
2012
2013 static void omap_mpuio_onoff(void *opaque, int line, int on)
2014 {
2015 struct omap_mpuio_s *s = (struct omap_mpuio_s *) opaque;
2016
2017 s->clk = on;
2018 if (on)
2019 omap_mpuio_kbd_update(s);
2020 }
2021
2022 struct omap_mpuio_s *omap_mpuio_init(target_phys_addr_t base,
2023 qemu_irq kbd_int, qemu_irq gpio_int, qemu_irq wakeup,
2024 omap_clk clk)
2025 {
2026 int iomemtype;
2027 struct omap_mpuio_s *s = (struct omap_mpuio_s *)
2028 qemu_mallocz(sizeof(struct omap_mpuio_s));
2029
2030 s->irq = gpio_int;
2031 s->kbd_irq = kbd_int;
2032 s->wakeup = wakeup;
2033 s->in = qemu_allocate_irqs(omap_mpuio_set, s, 16);
2034 omap_mpuio_reset(s);
2035
2036 iomemtype = cpu_register_io_memory(omap_mpuio_readfn,
2037 omap_mpuio_writefn, s, DEVICE_NATIVE_ENDIAN);
2038 cpu_register_physical_memory(base, 0x800, iomemtype);
2039
2040 omap_clk_adduser(clk, qemu_allocate_irqs(omap_mpuio_onoff, s, 1)[0]);
2041
2042 return s;
2043 }
2044
2045 qemu_irq *omap_mpuio_in_get(struct omap_mpuio_s *s)
2046 {
2047 return s->in;
2048 }
2049
2050 void omap_mpuio_out_set(struct omap_mpuio_s *s, int line, qemu_irq handler)
2051 {
2052 if (line >= 16 || line < 0)
2053 hw_error("%s: No GPIO line %i\n", __FUNCTION__, line);
2054 s->handler[line] = handler;
2055 }
2056
2057 void omap_mpuio_key(struct omap_mpuio_s *s, int row, int col, int down)
2058 {
2059 if (row >= 5 || row < 0)
2060 hw_error("%s: No key %i-%i\n", __FUNCTION__, col, row);
2061
2062 if (down)
2063 s->buttons[row] |= 1 << col;
2064 else
2065 s->buttons[row] &= ~(1 << col);
2066
2067 omap_mpuio_kbd_update(s);
2068 }
2069
2070 /* MicroWire Interface */
2071 struct omap_uwire_s {
2072 qemu_irq txirq;
2073 qemu_irq rxirq;
2074 qemu_irq txdrq;
2075
2076 uint16_t txbuf;
2077 uint16_t rxbuf;
2078 uint16_t control;
2079 uint16_t setup[5];
2080
2081 uWireSlave *chip[4];
2082 };
2083
2084 static void omap_uwire_transfer_start(struct omap_uwire_s *s)
2085 {
2086 int chipselect = (s->control >> 10) & 3; /* INDEX */
2087 uWireSlave *slave = s->chip[chipselect];
2088
2089 if ((s->control >> 5) & 0x1f) { /* NB_BITS_WR */
2090 if (s->control & (1 << 12)) /* CS_CMD */
2091 if (slave && slave->send)
2092 slave->send(slave->opaque,
2093 s->txbuf >> (16 - ((s->control >> 5) & 0x1f)));
2094 s->control &= ~(1 << 14); /* CSRB */
2095 /* TODO: depending on s->setup[4] bits [1:0] assert an IRQ or
2096 * a DRQ. When is the level IRQ supposed to be reset? */
2097 }
2098
2099 if ((s->control >> 0) & 0x1f) { /* NB_BITS_RD */
2100 if (s->control & (1 << 12)) /* CS_CMD */
2101 if (slave && slave->receive)
2102 s->rxbuf = slave->receive(slave->opaque);
2103 s->control |= 1 << 15; /* RDRB */
2104 /* TODO: depending on s->setup[4] bits [1:0] assert an IRQ or
2105 * a DRQ. When is the level IRQ supposed to be reset? */
2106 }
2107 }
2108
2109 static uint32_t omap_uwire_read(void *opaque, target_phys_addr_t addr)
2110 {
2111 struct omap_uwire_s *s = (struct omap_uwire_s *) opaque;
2112 int offset = addr & OMAP_MPUI_REG_MASK;
2113
2114 switch (offset) {
2115 case 0x00: /* RDR */
2116 s->control &= ~(1 << 15); /* RDRB */
2117 return s->rxbuf;
2118
2119 case 0x04: /* CSR */
2120 return s->control;
2121
2122 case 0x08: /* SR1 */
2123 return s->setup[0];
2124 case 0x0c: /* SR2 */
2125 return s->setup[1];
2126 case 0x10: /* SR3 */
2127 return s->setup[2];
2128 case 0x14: /* SR4 */
2129 return s->setup[3];
2130 case 0x18: /* SR5 */
2131 return s->setup[4];
2132 }
2133
2134 OMAP_BAD_REG(addr);
2135 return 0;
2136 }
2137
2138 static void omap_uwire_write(void *opaque, target_phys_addr_t addr,
2139 uint32_t value)
2140 {
2141 struct omap_uwire_s *s = (struct omap_uwire_s *) opaque;
2142 int offset = addr & OMAP_MPUI_REG_MASK;
2143
2144 switch (offset) {
2145 case 0x00: /* TDR */
2146 s->txbuf = value; /* TD */
2147 if ((s->setup[4] & (1 << 2)) && /* AUTO_TX_EN */
2148 ((s->setup[4] & (1 << 3)) || /* CS_TOGGLE_TX_EN */
2149 (s->control & (1 << 12)))) { /* CS_CMD */
2150 s->control |= 1 << 14; /* CSRB */
2151 omap_uwire_transfer_start(s);
2152 }
2153 break;
2154
2155 case 0x04: /* CSR */
2156 s->control = value & 0x1fff;
2157 if (value & (1 << 13)) /* START */
2158 omap_uwire_transfer_start(s);
2159 break;
2160
2161 case 0x08: /* SR1 */
2162 s->setup[0] = value & 0x003f;
2163 break;
2164
2165 case 0x0c: /* SR2 */
2166 s->setup[1] = value & 0x0fc0;
2167 break;
2168
2169 case 0x10: /* SR3 */
2170 s->setup[2] = value & 0x0003;
2171 break;
2172
2173 case 0x14: /* SR4 */
2174 s->setup[3] = value & 0x0001;
2175 break;
2176
2177 case 0x18: /* SR5 */
2178 s->setup[4] = value & 0x000f;
2179 break;
2180
2181 default:
2182 OMAP_BAD_REG(addr);
2183 return;
2184 }
2185 }
2186
2187 static CPUReadMemoryFunc * const omap_uwire_readfn[] = {
2188 omap_badwidth_read16,
2189 omap_uwire_read,
2190 omap_badwidth_read16,
2191 };
2192
2193 static CPUWriteMemoryFunc * const omap_uwire_writefn[] = {
2194 omap_badwidth_write16,
2195 omap_uwire_write,
2196 omap_badwidth_write16,
2197 };
2198
2199 static void omap_uwire_reset(struct omap_uwire_s *s)
2200 {
2201 s->control = 0;
2202 s->setup[0] = 0;
2203 s->setup[1] = 0;
2204 s->setup[2] = 0;
2205 s->setup[3] = 0;
2206 s->setup[4] = 0;
2207 }
2208
2209 struct omap_uwire_s *omap_uwire_init(target_phys_addr_t base,
2210 qemu_irq *irq, qemu_irq dma, omap_clk clk)
2211 {
2212 int iomemtype;
2213 struct omap_uwire_s *s = (struct omap_uwire_s *)
2214 qemu_mallocz(sizeof(struct omap_uwire_s));
2215
2216 s->txirq = irq[0];
2217 s->rxirq = irq[1];
2218 s->txdrq = dma;
2219 omap_uwire_reset(s);
2220
2221 iomemtype = cpu_register_io_memory(omap_uwire_readfn,
2222 omap_uwire_writefn, s, DEVICE_NATIVE_ENDIAN);
2223 cpu_register_physical_memory(base, 0x800, iomemtype);
2224
2225 return s;
2226 }
2227
2228 void omap_uwire_attach(struct omap_uwire_s *s,
2229 uWireSlave *slave, int chipselect)
2230 {
2231 if (chipselect < 0 || chipselect > 3) {
2232 fprintf(stderr, "%s: Bad chipselect %i\n", __FUNCTION__, chipselect);
2233 exit(-1);
2234 }
2235
2236 s->chip[chipselect] = slave;
2237 }
2238
2239 /* Pseudonoise Pulse-Width Light Modulator */
2240 static void omap_pwl_update(struct omap_mpu_state_s *s)
2241 {
2242 int output = (s->pwl.clk && s->pwl.enable) ? s->pwl.level : 0;
2243
2244 if (output != s->pwl.output) {
2245 s->pwl.output = output;
2246 printf("%s: Backlight now at %i/256\n", __FUNCTION__, output);
2247 }
2248 }
2249
2250 static uint32_t omap_pwl_read(void *opaque, target_phys_addr_t addr)
2251 {
2252 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
2253 int offset = addr & OMAP_MPUI_REG_MASK;
2254
2255 switch (offset) {
2256 case 0x00: /* PWL_LEVEL */
2257 return s->pwl.level;
2258 case 0x04: /* PWL_CTRL */
2259 return s->pwl.enable;
2260 }
2261 OMAP_BAD_REG(addr);
2262 return 0;
2263 }
2264
2265 static void omap_pwl_write(void *opaque, target_phys_addr_t addr,
2266 uint32_t value)
2267 {
2268 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
2269 int offset = addr & OMAP_MPUI_REG_MASK;
2270
2271 switch (offset) {
2272 case 0x00: /* PWL_LEVEL */
2273 s->pwl.level = value;
2274 omap_pwl_update(s);
2275 break;
2276 case 0x04: /* PWL_CTRL */
2277 s->pwl.enable = value & 1;
2278 omap_pwl_update(s);
2279 break;
2280 default:
2281 OMAP_BAD_REG(addr);
2282 return;
2283 }
2284 }
2285
2286 static CPUReadMemoryFunc * const omap_pwl_readfn[] = {
2287 omap_pwl_read,
2288 omap_badwidth_read8,
2289 omap_badwidth_read8,
2290 };
2291
2292 static CPUWriteMemoryFunc * const omap_pwl_writefn[] = {
2293 omap_pwl_write,
2294 omap_badwidth_write8,
2295 omap_badwidth_write8,
2296 };
2297
2298 static void omap_pwl_reset(struct omap_mpu_state_s *s)
2299 {
2300 s->pwl.output = 0;
2301 s->pwl.level = 0;
2302 s->pwl.enable = 0;
2303 s->pwl.clk = 1;
2304 omap_pwl_update(s);
2305 }
2306
2307 static void omap_pwl_clk_update(void *opaque, int line, int on)
2308 {
2309 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
2310
2311 s->pwl.clk = on;
2312 omap_pwl_update(s);
2313 }
2314
2315 static void omap_pwl_init(target_phys_addr_t base, struct omap_mpu_state_s *s,
2316 omap_clk clk)
2317 {
2318 int iomemtype;
2319
2320 omap_pwl_reset(s);
2321
2322 iomemtype = cpu_register_io_memory(omap_pwl_readfn,
2323 omap_pwl_writefn, s, DEVICE_NATIVE_ENDIAN);
2324 cpu_register_physical_memory(base, 0x800, iomemtype);
2325
2326 omap_clk_adduser(clk, qemu_allocate_irqs(omap_pwl_clk_update, s, 1)[0]);
2327 }
2328
2329 /* Pulse-Width Tone module */
2330 static uint32_t omap_pwt_read(void *opaque, target_phys_addr_t addr)
2331 {
2332 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
2333 int offset = addr & OMAP_MPUI_REG_MASK;
2334
2335 switch (offset) {
2336 case 0x00: /* FRC */
2337 return s->pwt.frc;
2338 case 0x04: /* VCR */
2339 return s->pwt.vrc;
2340 case 0x08: /* GCR */
2341 return s->pwt.gcr;
2342 }
2343 OMAP_BAD_REG(addr);
2344 return 0;
2345 }
2346
2347 static void omap_pwt_write(void *opaque, target_phys_addr_t addr,
2348 uint32_t value)
2349 {
2350 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
2351 int offset = addr & OMAP_MPUI_REG_MASK;
2352
2353 switch (offset) {
2354 case 0x00: /* FRC */
2355 s->pwt.frc = value & 0x3f;
2356 break;
2357 case 0x04: /* VRC */
2358 if ((value ^ s->pwt.vrc) & 1) {
2359 if (value & 1)
2360 printf("%s: %iHz buzz on\n", __FUNCTION__, (int)
2361 /* 1.5 MHz from a 12-MHz or 13-MHz PWT_CLK */
2362 ((omap_clk_getrate(s->pwt.clk) >> 3) /
2363 /* Pre-multiplexer divider */
2364 ((s->pwt.gcr & 2) ? 1 : 154) /
2365 /* Octave multiplexer */
2366 (2 << (value & 3)) *
2367 /* 101/107 divider */
2368 ((value & (1 << 2)) ? 101 : 107) *
2369 /* 49/55 divider */
2370 ((value & (1 << 3)) ? 49 : 55) *
2371 /* 50/63 divider */
2372 ((value & (1 << 4)) ? 50 : 63) *
2373 /* 80/127 divider */
2374 ((value & (1 << 5)) ? 80 : 127) /
2375 (107 * 55 * 63 * 127)));
2376 else
2377 printf("%s: silence!\n", __FUNCTION__);
2378 }
2379 s->pwt.vrc = value & 0x7f;
2380 break;
2381 case 0x08: /* GCR */
2382 s->pwt.gcr = value & 3;
2383 break;
2384 default:
2385 OMAP_BAD_REG(addr);
2386 return;
2387 }
2388 }
2389
2390 static CPUReadMemoryFunc * const omap_pwt_readfn[] = {
2391 omap_pwt_read,
2392 omap_badwidth_read8,
2393 omap_badwidth_read8,
2394 };
2395
2396 static CPUWriteMemoryFunc * const omap_pwt_writefn[] = {
2397 omap_pwt_write,
2398 omap_badwidth_write8,
2399 omap_badwidth_write8,
2400 };
2401
2402 static void omap_pwt_reset(struct omap_mpu_state_s *s)
2403 {
2404 s->pwt.frc = 0;
2405 s->pwt.vrc = 0;
2406 s->pwt.gcr = 0;
2407 }
2408
2409 static void omap_pwt_init(target_phys_addr_t base, struct omap_mpu_state_s *s,
2410 omap_clk clk)
2411 {
2412 int iomemtype;
2413
2414 s->pwt.clk = clk;
2415 omap_pwt_reset(s);
2416
2417 iomemtype = cpu_register_io_memory(omap_pwt_readfn,
2418 omap_pwt_writefn, s, DEVICE_NATIVE_ENDIAN);
2419 cpu_register_physical_memory(base, 0x800, iomemtype);
2420 }
2421
2422 /* Real-time Clock module */
2423 struct omap_rtc_s {
2424 qemu_irq irq;
2425 qemu_irq alarm;
2426 QEMUTimer *clk;
2427
2428 uint8_t interrupts;
2429 uint8_t status;
2430 int16_t comp_reg;
2431 int running;
2432 int pm_am;
2433 int auto_comp;
2434 int round;
2435 struct tm alarm_tm;
2436 time_t alarm_ti;
2437
2438 struct tm current_tm;
2439 time_t ti;
2440 uint64_t tick;
2441 };
2442
2443 static void omap_rtc_interrupts_update(struct omap_rtc_s *s)
2444 {
2445 /* s->alarm is level-triggered */
2446 qemu_set_irq(s->alarm, (s->status >> 6) & 1);
2447 }
2448
2449 static void omap_rtc_alarm_update(struct omap_rtc_s *s)
2450 {
2451 s->alarm_ti = mktimegm(&s->alarm_tm);
2452 if (s->alarm_ti == -1)
2453 printf("%s: conversion failed\n", __FUNCTION__);
2454 }
2455
2456 static uint32_t omap_rtc_read(void *opaque, target_phys_addr_t addr)
2457 {
2458 struct omap_rtc_s *s = (struct omap_rtc_s *) opaque;
2459 int offset = addr & OMAP_MPUI_REG_MASK;
2460 uint8_t i;
2461
2462 switch (offset) {
2463 case 0x00: /* SECONDS_REG */
2464 return to_bcd(s->current_tm.tm_sec);
2465
2466 case 0x04: /* MINUTES_REG */
2467 return to_bcd(s->current_tm.tm_min);
2468
2469 case 0x08: /* HOURS_REG */
2470 if (s->pm_am)
2471 return ((s->current_tm.tm_hour > 11) << 7) |
2472 to_bcd(((s->current_tm.tm_hour - 1) % 12) + 1);
2473 else
2474 return to_bcd(s->current_tm.tm_hour);
2475
2476 case 0x0c: /* DAYS_REG */
2477 return to_bcd(s->current_tm.tm_mday);
2478
2479 case 0x10: /* MONTHS_REG */
2480 return to_bcd(s->current_tm.tm_mon + 1);
2481
2482 case 0x14: /* YEARS_REG */
2483 return to_bcd(s->current_tm.tm_year % 100);
2484
2485 case 0x18: /* WEEK_REG */
2486 return s->current_tm.tm_wday;
2487
2488 case 0x20: /* ALARM_SECONDS_REG */
2489 return to_bcd(s->alarm_tm.tm_sec);
2490
2491 case 0x24: /* ALARM_MINUTES_REG */
2492 return to_bcd(s->alarm_tm.tm_min);
2493
2494 case 0x28: /* ALARM_HOURS_REG */
2495 if (s->pm_am)
2496 return ((s->alarm_tm.tm_hour > 11) << 7) |
2497 to_bcd(((s->alarm_tm.tm_hour - 1) % 12) + 1);
2498 else
2499 return to_bcd(s->alarm_tm.tm_hour);
2500
2501 case 0x2c: /* ALARM_DAYS_REG */
2502 return to_bcd(s->alarm_tm.tm_mday);
2503
2504 case 0x30: /* ALARM_MONTHS_REG */
2505 return to_bcd(s->alarm_tm.tm_mon + 1);
2506
2507 case 0x34: /* ALARM_YEARS_REG */
2508 return to_bcd(s->alarm_tm.tm_year % 100);
2509
2510 case 0x40: /* RTC_CTRL_REG */
2511 return (s->pm_am << 3) | (s->auto_comp << 2) |
2512 (s->round << 1) | s->running;
2513
2514 case 0x44: /* RTC_STATUS_REG */
2515 i = s->status;
2516 s->status &= ~0x3d;
2517 return i;
2518
2519 case 0x48: /* RTC_INTERRUPTS_REG */
2520 return s->interrupts;
2521
2522 case 0x4c: /* RTC_COMP_LSB_REG */
2523 return ((uint16_t) s->comp_reg) & 0xff;
2524
2525 case 0x50: /* RTC_COMP_MSB_REG */
2526 return ((uint16_t) s->comp_reg) >> 8;
2527 }
2528
2529 OMAP_BAD_REG(addr);
2530 return 0;
2531 }
2532
2533 static void omap_rtc_write(void *opaque, target_phys_addr_t addr,
2534 uint32_t value)
2535 {
2536 struct omap_rtc_s *s = (struct omap_rtc_s *) opaque;
2537 int offset = addr & OMAP_MPUI_REG_MASK;
2538 struct tm new_tm;
2539 time_t ti[2];
2540
2541 switch (offset) {
2542 case 0x00: /* SECONDS_REG */
2543 #ifdef ALMDEBUG
2544 printf("RTC SEC_REG <-- %02x\n", value);
2545 #endif
2546 s->ti -= s->current_tm.tm_sec;
2547 s->ti += from_bcd(value);
2548 return;
2549
2550 case 0x04: /* MINUTES_REG */
2551 #ifdef ALMDEBUG
2552 printf("RTC MIN_REG <-- %02x\n", value);
2553 #endif
2554 s->ti -= s->current_tm.tm_min * 60;
2555 s->ti += from_bcd(value) * 60;
2556 return;
2557
2558 case 0x08: /* HOURS_REG */
2559 #ifdef ALMDEBUG
2560 printf("RTC HRS_REG <-- %02x\n", value);
2561 #endif
2562 s->ti -= s->current_tm.tm_hour * 3600;
2563 if (s->pm_am) {
2564 s->ti += (from_bcd(value & 0x3f) & 12) * 3600;
2565 s->ti += ((value >> 7) & 1) * 43200;
2566 } else
2567 s->ti += from_bcd(value & 0x3f) * 3600;
2568 return;
2569
2570 case 0x0c: /* DAYS_REG */
2571 #ifdef ALMDEBUG
2572 printf("RTC DAY_REG <-- %02x\n", value);
2573 #endif
2574 s->ti -= s->current_tm.tm_mday * 86400;
2575 s->ti += from_bcd(value) * 86400;
2576 return;
2577
2578 case 0x10: /* MONTHS_REG */
2579 #ifdef ALMDEBUG
2580 printf("RTC MTH_REG <-- %02x\n", value);
2581 #endif
2582 memcpy(&new_tm, &s->current_tm, sizeof(new_tm));
2583 new_tm.tm_mon = from_bcd(value);
2584 ti[0] = mktimegm(&s->current_tm);
2585 ti[1] = mktimegm(&new_tm);
2586
2587 if (ti[0] != -1 && ti[1] != -1) {
2588 s->ti -= ti[0];
2589 s->ti += ti[1];
2590 } else {
2591 /* A less accurate version */
2592 s->ti -= s->current_tm.tm_mon * 2592000;
2593 s->ti += from_bcd(value) * 2592000;
2594 }
2595 return;
2596
2597 case 0x14: /* YEARS_REG */
2598 #ifdef ALMDEBUG
2599 printf("RTC YRS_REG <-- %02x\n", value);
2600 #endif
2601 memcpy(&new_tm, &s->current_tm, sizeof(new_tm));
2602 new_tm.tm_year += from_bcd(value) - (new_tm.tm_year % 100);
2603 ti[0] = mktimegm(&s->current_tm);
2604 ti[1] = mktimegm(&new_tm);
2605
2606 if (ti[0] != -1 && ti[1] != -1) {
2607 s->ti -= ti[0];
2608 s->ti += ti[1];
2609 } else {
2610 /* A less accurate version */
2611 s->ti -= (s->current_tm.tm_year % 100) * 31536000;
2612 s->ti += from_bcd(value) * 31536000;
2613 }
2614 return;
2615
2616 case 0x18: /* WEEK_REG */
2617 return; /* Ignored */
2618
2619 case 0x20: /* ALARM_SECONDS_REG */
2620 #ifdef ALMDEBUG
2621 printf("ALM SEC_REG <-- %02x\n", value);
2622 #endif
2623 s->alarm_tm.tm_sec = from_bcd(value);
2624 omap_rtc_alarm_update(s);
2625 return;
2626
2627 case 0x24: /* ALARM_MINUTES_REG */
2628 #ifdef ALMDEBUG
2629 printf("ALM MIN_REG <-- %02x\n", value);
2630 #endif
2631 s->alarm_tm.tm_min = from_bcd(value);
2632 omap_rtc_alarm_update(s);
2633 return;
2634
2635 case 0x28: /* ALARM_HOURS_REG */
2636 #ifdef ALMDEBUG
2637 printf("ALM HRS_REG <-- %02x\n", value);
2638 #endif
2639 if (s->pm_am)
2640 s->alarm_tm.tm_hour =
2641 ((from_bcd(value & 0x3f)) % 12) +
2642 ((value >> 7) & 1) * 12;
2643 else
2644 s->alarm_tm.tm_hour = from_bcd(value);
2645 omap_rtc_alarm_update(s);
2646 return;
2647
2648 case 0x2c: /* ALARM_DAYS_REG */
2649 #ifdef ALMDEBUG
2650 printf("ALM DAY_REG <-- %02x\n", value);
2651 #endif
2652 s->alarm_tm.tm_mday = from_bcd(value);
2653 omap_rtc_alarm_update(s);
2654 return;
2655
2656 case 0x30: /* ALARM_MONTHS_REG */
2657 #ifdef ALMDEBUG
2658 printf("ALM MON_REG <-- %02x\n", value);
2659 #endif
2660 s->alarm_tm.tm_mon = from_bcd(value);
2661 omap_rtc_alarm_update(s);
2662 return;
2663
2664 case 0x34: /* ALARM_YEARS_REG */
2665 #ifdef ALMDEBUG
2666 printf("ALM YRS_REG <-- %02x\n", value);
2667 #endif
2668 s->alarm_tm.tm_year = from_bcd(value);
2669 omap_rtc_alarm_update(s);
2670 return;
2671
2672 case 0x40: /* RTC_CTRL_REG */
2673 #ifdef ALMDEBUG
2674 printf("RTC CONTROL <-- %02x\n", value);
2675 #endif
2676 s->pm_am = (value >> 3) & 1;
2677 s->auto_comp = (value >> 2) & 1;
2678 s->round = (value >> 1) & 1;
2679 s->running = value & 1;
2680 s->status &= 0xfd;
2681 s->status |= s->running << 1;
2682 return;
2683
2684 case 0x44: /* RTC_STATUS_REG */
2685 #ifdef ALMDEBUG
2686 printf("RTC STATUSL <-- %02x\n", value);
2687 #endif
2688 s->status &= ~((value & 0xc0) ^ 0x80);
2689 omap_rtc_interrupts_update(s);
2690 return;
2691
2692 case 0x48: /* RTC_INTERRUPTS_REG */
2693 #ifdef ALMDEBUG
2694 printf("RTC INTRS <-- %02x\n", value);
2695 #endif
2696 s->interrupts = value;
2697 return;
2698
2699 case 0x4c: /* RTC_COMP_LSB_REG */
2700 #ifdef ALMDEBUG
2701 printf("RTC COMPLSB <-- %02x\n", value);
2702 #endif
2703 s->comp_reg &= 0xff00;
2704 s->comp_reg |= 0x00ff & value;
2705 return;
2706
2707 case 0x50: /* RTC_COMP_MSB_REG */
2708 #ifdef ALMDEBUG
2709 printf("RTC COMPMSB <-- %02x\n", value);
2710 #endif
2711 s->comp_reg &= 0x00ff;
2712 s->comp_reg |= 0xff00 & (value << 8);
2713 return;
2714
2715 default:
2716 OMAP_BAD_REG(addr);
2717 return;
2718 }
2719 }
2720
2721 static CPUReadMemoryFunc * const omap_rtc_readfn[] = {
2722 omap_rtc_read,
2723 omap_badwidth_read8,
2724 omap_badwidth_read8,
2725 };
2726
2727 static CPUWriteMemoryFunc * const omap_rtc_writefn[] = {
2728 omap_rtc_write,
2729 omap_badwidth_write8,
2730 omap_badwidth_write8,
2731 };
2732
2733 static void omap_rtc_tick(void *opaque)
2734 {
2735 struct omap_rtc_s *s = opaque;
2736
2737 if (s->round) {
2738 /* Round to nearest full minute. */
2739 if (s->current_tm.tm_sec < 30)
2740 s->ti -= s->current_tm.tm_sec;
2741 else
2742 s->ti += 60 - s->current_tm.tm_sec;
2743
2744 s->round = 0;
2745 }
2746
2747 memcpy(&s->current_tm, localtime(&s->ti), sizeof(s->current_tm));
2748
2749 if ((s->interrupts & 0x08) && s->ti == s->alarm_ti) {
2750 s->status |= 0x40;
2751 omap_rtc_interrupts_update(s);
2752 }
2753
2754 if (s->interrupts & 0x04)
2755 switch (s->interrupts & 3) {
2756 case 0:
2757 s->status |= 0x04;
2758 qemu_irq_pulse(s->irq);
2759 break;
2760 case 1:
2761 if (s->current_tm.tm_sec)
2762 break;
2763 s->status |= 0x08;
2764 qemu_irq_pulse(s->irq);
2765 break;
2766 case 2:
2767 if (s->current_tm.tm_sec || s->current_tm.tm_min)
2768 break;
2769 s->status |= 0x10;
2770 qemu_irq_pulse(s->irq);
2771 break;
2772 case 3:
2773 if (s->current_tm.tm_sec ||
2774 s->current_tm.tm_min || s->current_tm.tm_hour)
2775 break;
2776 s->status |= 0x20;
2777 qemu_irq_pulse(s->irq);
2778 break;
2779 }
2780
2781 /* Move on */
2782 if (s->running)
2783 s->ti ++;
2784 s->tick += 1000;
2785
2786 /*
2787 * Every full hour add a rough approximation of the compensation
2788 * register to the 32kHz Timer (which drives the RTC) value.
2789 */
2790 if (s->auto_comp && !s->current_tm.tm_sec && !s->current_tm.tm_min)
2791 s->tick += s->comp_reg * 1000 / 32768;
2792
2793 qemu_mod_timer(s->clk, s->tick);
2794 }
2795
2796 static void omap_rtc_reset(struct omap_rtc_s *s)
2797 {
2798 struct tm tm;
2799
2800 s->interrupts = 0;
2801 s->comp_reg = 0;
2802 s->running = 0;
2803 s->pm_am = 0;
2804 s->auto_comp = 0;
2805 s->round = 0;
2806 s->tick = qemu_get_clock_ms(rt_clock);
2807 memset(&s->alarm_tm, 0, sizeof(s->alarm_tm));
2808 s->alarm_tm.tm_mday = 0x01;
2809 s->status = 1 << 7;
2810 qemu_get_timedate(&tm, 0);
2811 s->ti = mktimegm(&tm);
2812
2813 omap_rtc_alarm_update(s);
2814 omap_rtc_tick(s);
2815 }
2816
2817 static struct omap_rtc_s *omap_rtc_init(target_phys_addr_t base,
2818 qemu_irq *irq, omap_clk clk)
2819 {
2820 int iomemtype;
2821 struct omap_rtc_s *s = (struct omap_rtc_s *)
2822 qemu_mallocz(sizeof(struct omap_rtc_s));
2823
2824 s->irq = irq[0];
2825 s->alarm = irq[1];
2826 s->clk = qemu_new_timer_ms(rt_clock, omap_rtc_tick, s);
2827
2828 omap_rtc_reset(s);
2829
2830 iomemtype = cpu_register_io_memory(omap_rtc_readfn,
2831 omap_rtc_writefn, s, DEVICE_NATIVE_ENDIAN);
2832 cpu_register_physical_memory(base, 0x800, iomemtype);
2833
2834 return s;
2835 }
2836
2837 /* Multi-channel Buffered Serial Port interfaces */
2838 struct omap_mcbsp_s {
2839 qemu_irq txirq;
2840 qemu_irq rxirq;
2841 qemu_irq txdrq;
2842 qemu_irq rxdrq;
2843
2844 uint16_t spcr[2];
2845 uint16_t rcr[2];
2846 uint16_t xcr[2];
2847 uint16_t srgr[2];
2848 uint16_t mcr[2];
2849 uint16_t pcr;
2850 uint16_t rcer[8];
2851 uint16_t xcer[8];
2852 int tx_rate;
2853 int rx_rate;
2854 int tx_req;
2855 int rx_req;
2856
2857 I2SCodec *codec;
2858 QEMUTimer *source_timer;
2859 QEMUTimer *sink_timer;
2860 };
2861
2862 static void omap_mcbsp_intr_update(struct omap_mcbsp_s *s)
2863 {
2864 int irq;
2865
2866 switch ((s->spcr[0] >> 4) & 3) { /* RINTM */
2867 case 0:
2868 irq = (s->spcr[0] >> 1) & 1; /* RRDY */
2869 break;
2870 case 3:
2871 irq = (s->spcr[0] >> 3) & 1; /* RSYNCERR */
2872 break;
2873 default:
2874 irq = 0;
2875 break;
2876 }
2877
2878 if (irq)
2879 qemu_irq_pulse(s->rxirq);
2880
2881 switch ((s->spcr[1] >> 4) & 3) { /* XINTM */
2882 case 0:
2883 irq = (s->spcr[1] >> 1) & 1; /* XRDY */
2884 break;
2885 case 3:
2886 irq = (s->spcr[1] >> 3) & 1; /* XSYNCERR */
2887 break;
2888 default:
2889 irq = 0;
2890 break;
2891 }
2892
2893 if (irq)
2894 qemu_irq_pulse(s->txirq);
2895 }
2896
2897 static void omap_mcbsp_rx_newdata(struct omap_mcbsp_s *s)
2898 {
2899 if ((s->spcr[0] >> 1) & 1) /* RRDY */
2900 s->spcr[0] |= 1 << 2; /* RFULL */
2901 s->spcr[0] |= 1 << 1; /* RRDY */
2902 qemu_irq_raise(s->rxdrq);
2903 omap_mcbsp_intr_update(s);
2904 }
2905
2906 static void omap_mcbsp_source_tick(void *opaque)
2907 {
2908 struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque;
2909 static const int bps[8] = { 0, 1, 1, 2, 2, 2, -255, -255 };
2910
2911 if (!s->rx_rate)
2912 return;
2913 if (s->rx_req)
2914 printf("%s: Rx FIFO overrun\n", __FUNCTION__);
2915
2916 s->rx_req = s->rx_rate << bps[(s->rcr[0] >> 5) & 7];
2917
2918 omap_mcbsp_rx_newdata(s);
2919 qemu_mod_timer(s->source_timer, qemu_get_clock_ns(vm_clock) +
2920 get_ticks_per_sec());
2921 }
2922
2923 static void omap_mcbsp_rx_start(struct omap_mcbsp_s *s)
2924 {
2925 if (!s->codec || !s->codec->rts)
2926 omap_mcbsp_source_tick(s);
2927 else if (s->codec->in.len) {
2928 s->rx_req = s->codec->in.len;
2929 omap_mcbsp_rx_newdata(s);
2930 }
2931 }
2932
2933 static void omap_mcbsp_rx_stop(struct omap_mcbsp_s *s)
2934 {
2935 qemu_del_timer(s->source_timer);
2936 }
2937
2938 static void omap_mcbsp_rx_done(struct omap_mcbsp_s *s)
2939 {
2940 s->spcr[0] &= ~(1 << 1); /* RRDY */
2941 qemu_irq_lower(s->rxdrq);
2942 omap_mcbsp_intr_update(s);
2943 }
2944
2945 static void omap_mcbsp_tx_newdata(struct omap_mcbsp_s *s)
2946 {
2947 s->spcr[1] |= 1 << 1; /* XRDY */
2948 qemu_irq_raise(s->txdrq);
2949 omap_mcbsp_intr_update(s);
2950 }
2951
2952 static void omap_mcbsp_sink_tick(void *opaque)
2953 {
2954 struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque;
2955 static const int bps[8] = { 0, 1, 1, 2, 2, 2, -255, -255 };
2956
2957 if (!s->tx_rate)
2958 return;
2959 if (s->tx_req)
2960 printf("%s: Tx FIFO underrun\n", __FUNCTION__);
2961
2962 s->tx_req = s->tx_rate << bps[(s->xcr[0] >> 5) & 7];
2963
2964 omap_mcbsp_tx_newdata(s);
2965 qemu_mod_timer(s->sink_timer, qemu_get_clock_ns(vm_clock) +
2966 get_ticks_per_sec());
2967 }
2968
2969 static void omap_mcbsp_tx_start(struct omap_mcbsp_s *s)
2970 {
2971 if (!s->codec || !s->codec->cts)
2972 omap_mcbsp_sink_tick(s);
2973 else if (s->codec->out.size) {
2974 s->tx_req = s->codec->out.size;
2975 omap_mcbsp_tx_newdata(s);
2976 }
2977 }
2978
2979 static void omap_mcbsp_tx_done(struct omap_mcbsp_s *s)
2980 {
2981 s->spcr[1] &= ~(1 << 1); /* XRDY */
2982 qemu_irq_lower(s->txdrq);
2983 omap_mcbsp_intr_update(s);
2984 if (s->codec && s->codec->cts)
2985 s->codec->tx_swallow(s->codec->opaque);
2986 }
2987
2988 static void omap_mcbsp_tx_stop(struct omap_mcbsp_s *s)
2989 {
2990 s->tx_req = 0;
2991 omap_mcbsp_tx_done(s);
2992 qemu_del_timer(s->sink_timer);
2993 }
2994
2995 static void omap_mcbsp_req_update(struct omap_mcbsp_s *s)
2996 {
2997 int prev_rx_rate, prev_tx_rate;
2998 int rx_rate = 0, tx_rate = 0;
2999 int cpu_rate = 1500000; /* XXX */
3000
3001 /* TODO: check CLKSTP bit */
3002 if (s->spcr[1] & (1 << 6)) { /* GRST */
3003 if (s->spcr[0] & (1 << 0)) { /* RRST */
3004 if ((s->srgr[1] & (1 << 13)) && /* CLKSM */
3005 (s->pcr & (1 << 8))) { /* CLKRM */
3006 if (~s->pcr & (1 << 7)) /* SCLKME */
3007 rx_rate = cpu_rate /
3008 ((s->srgr[0] & 0xff) + 1); /* CLKGDV */
3009 } else
3010 if (s->codec)
3011 rx_rate = s->codec->rx_rate;
3012 }
3013
3014 if (s->spcr[1] & (1 << 0)) { /* XRST */
3015 if ((s->srgr[1] & (1 << 13)) && /* CLKSM */
3016 (s->pcr & (1 << 9))) { /* CLKXM */
3017 if (~s->pcr & (1 << 7)) /* SCLKME */
3018 tx_rate = cpu_rate /
3019 ((s->srgr[0] & 0xff) + 1); /* CLKGDV */
3020 } else
3021 if (s->codec)
3022 tx_rate = s->codec->tx_rate;
3023 }
3024 }
3025 prev_tx_rate = s->tx_rate;
3026 prev_rx_rate = s->rx_rate;
3027 s->tx_rate = tx_rate;
3028 s->rx_rate = rx_rate;
3029
3030 if (s->codec)
3031 s->codec->set_rate(s->codec->opaque, rx_rate, tx_rate);
3032
3033 if (!prev_tx_rate && tx_rate)
3034 omap_mcbsp_tx_start(s);
3035 else if (s->tx_rate && !tx_rate)
3036 omap_mcbsp_tx_stop(s);
3037
3038 if (!prev_rx_rate && rx_rate)
3039 omap_mcbsp_rx_start(s);
3040 else if (prev_tx_rate && !tx_rate)
3041 omap_mcbsp_rx_stop(s);
3042 }
3043
3044 static uint32_t omap_mcbsp_read(void *opaque, target_phys_addr_t addr)
3045 {
3046 struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque;
3047 int offset = addr & OMAP_MPUI_REG_MASK;
3048 uint16_t ret;
3049
3050 switch (offset) {
3051 case 0x00: /* DRR2 */
3052 if (((s->rcr[0] >> 5) & 7) < 3) /* RWDLEN1 */
3053 return 0x0000;
3054 /* Fall through. */
3055 case 0x02: /* DRR1 */
3056 if (s->rx_req < 2) {
3057 printf("%s: Rx FIFO underrun\n", __FUNCTION__);
3058 omap_mcbsp_rx_done(s);
3059 } else {
3060 s->tx_req -= 2;
3061 if (s->codec && s->codec->in.len >= 2) {
3062 ret = s->codec->in.fifo[s->codec->in.start ++] << 8;
3063 ret |= s->codec->in.fifo[s->codec->in.start ++];
3064 s->codec->in.len -= 2;
3065 } else
3066 ret = 0x0000;
3067 if (!s->tx_req)
3068 omap_mcbsp_rx_done(s);
3069 return ret;
3070 }
3071 return 0x0000;
3072
3073 case 0x04: /* DXR2 */
3074 case 0x06: /* DXR1 */
3075 return 0x0000;
3076
3077 case 0x08: /* SPCR2 */
3078 return s->spcr[1];
3079 case 0x0a: /* SPCR1 */
3080 return s->spcr[0];
3081 case 0x0c: /* RCR2 */
3082 return s->rcr[1];
3083 case 0x0e: /* RCR1 */
3084 return s->rcr[0];
3085 case 0x10: /* XCR2 */
3086 return s->xcr[1];
3087 case 0x12: /* XCR1 */
3088 return s->xcr[0];
3089 case 0x14: /* SRGR2 */
3090 return s->srgr[1];
3091 case 0x16: /* SRGR1 */
3092 return s->srgr[0];
3093 case 0x18: /* MCR2 */
3094 return s->mcr[1];
3095 case 0x1a: /* MCR1 */
3096 return s->mcr[0];
3097 case 0x1c: /* RCERA */
3098 return s->rcer[0];
3099 case 0x1e: /* RCERB */
3100 return s->rcer[1];
3101 case 0x20: /* XCERA */
3102 return s->xcer[0];
3103 case 0x22: /* XCERB */
3104 return s->xcer[1];
3105 case 0x24: /* PCR0 */
3106 return s->pcr;
3107 case 0x26: /* RCERC */
3108 return s->rcer[2];
3109 case 0x28: /* RCERD */
3110 return s->rcer[3];
3111 case 0x2a: /* XCERC */
3112 return s->xcer[2];
3113 case 0x2c: /* XCERD */
3114 return s->xcer[3];
3115 case 0x2e: /* RCERE */
3116 return s->rcer[4];
3117 case 0x30: /* RCERF */
3118 return s->rcer[5];
3119 case 0x32: /* XCERE */
3120 return s->xcer[4];
3121 case 0x34: /* XCERF */
3122 return s->xcer[5];
3123 case 0x36: /* RCERG */
3124 return s->rcer[6];
3125 case 0x38: /* RCERH */
3126 return s->rcer[7];
3127 case 0x3a: /* XCERG */
3128 return s->xcer[6];
3129 case 0x3c: /* XCERH */
3130 return s->xcer[7];
3131 }
3132
3133 OMAP_BAD_REG(addr);
3134 return 0;
3135 }
3136
3137 static void omap_mcbsp_writeh(void *opaque, target_phys_addr_t addr,
3138 uint32_t value)
3139 {
3140 struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque;
3141 int offset = addr & OMAP_MPUI_REG_MASK;
3142
3143 switch (offset) {
3144 case 0x00: /* DRR2 */
3145 case 0x02: /* DRR1 */
3146 OMAP_RO_REG(addr);
3147 return;
3148
3149 case 0x04: /* DXR2 */
3150 if (((s->xcr[0] >> 5) & 7) < 3) /* XWDLEN1 */
3151 return;
3152 /* Fall through. */
3153 case 0x06: /* DXR1 */
3154 if (s->tx_req > 1) {
3155 s->tx_req -= 2;
3156 if (s->codec && s->codec->cts) {
3157 s->codec->out.fifo[s->codec->out.len ++] = (value >> 8) & 0xff;
3158 s->codec->out.fifo[s->codec->out.len ++] = (value >> 0) & 0xff;
3159 }
3160 if (s->tx_req < 2)
3161 omap_mcbsp_tx_done(s);
3162 } else
3163 printf("%s: Tx FIFO overrun\n", __FUNCTION__);
3164 return;
3165
3166 case 0x08: /* SPCR2 */
3167 s->spcr[1] &= 0x0002;
3168 s->spcr[1] |= 0x03f9 & value;
3169 s->spcr[1] |= 0x0004 & (value << 2); /* XEMPTY := XRST */
3170 if (~value & 1) /* XRST */
3171 s->spcr[1] &= ~6;
3172 omap_mcbsp_req_update(s);
3173 return;
3174 case 0x0a: /* SPCR1 */
3175 s->spcr[0] &= 0x0006;
3176 s->spcr[0] |= 0xf8f9 & value;
3177 if (value & (1 << 15)) /* DLB */
3178 printf("%s: Digital Loopback mode enable attempt\n", __FUNCTION__);
3179 if (~value & 1) { /* RRST */
3180 s->spcr[0] &= ~6;
3181 s->rx_req = 0;
3182 omap_mcbsp_rx_done(s);
3183 }
3184 omap_mcbsp_req_update(s);
3185 return;
3186
3187 case 0x0c: /* RCR2 */
3188 s->rcr[1] = value & 0xffff;
3189 return;
3190 case 0x0e: /* RCR1 */
3191 s->rcr[0] = value & 0x7fe0;
3192 return;
3193 case 0x10: /* XCR2 */
3194 s->xcr[1] = value & 0xffff;
3195 return;
3196 case 0x12: /* XCR1 */
3197 s->xcr[0] = value & 0x7fe0;
3198 return;
3199 case 0x14: /* SRGR2 */
3200 s->srgr[1] = value & 0xffff;
3201 omap_mcbsp_req_update(s);
3202 return;
3203 case 0x16: /* SRGR1 */
3204 s->srgr[0] = value & 0xffff;
3205 omap_mcbsp_req_update(s);
3206 return;
3207 case 0x18: /* MCR2 */
3208 s->mcr[1] = value & 0x03e3;
3209 if (value & 3) /* XMCM */
3210 printf("%s: Tx channel selection mode enable attempt\n",
3211 __FUNCTION__);
3212 return;
3213 case 0x1a: /* MCR1 */
3214 s->mcr[0] = value & 0x03e1;
3215 if (value & 1) /* RMCM */
3216 printf("%s: Rx channel selection mode enable attempt\n",
3217 __FUNCTION__);
3218 return;
3219 case 0x1c: /* RCERA */
3220 s->rcer[0] = value & 0xffff;
3221 return;
3222 case 0x1e: /* RCERB */
3223 s->rcer[1] = value & 0xffff;
3224 return;
3225 case 0x20: /* XCERA */
3226 s->xcer[0] = value & 0xffff;
3227 return;
3228 case 0x22: /* XCERB */
3229 s->xcer[1] = value & 0xffff;
3230 return;
3231 case 0x24: /* PCR0 */
3232 s->pcr = value & 0x7faf;
3233 return;
3234 case 0x26: /* RCERC */
3235 s->rcer[2] = value & 0xffff;
3236 return;
3237 case 0x28: /* RCERD */
3238 s->rcer[3] = value & 0xffff;
3239 return;
3240 case 0x2a: /* XCERC */
3241 s->xcer[2] = value & 0xffff;
3242 return;
3243 case 0x2c: /* XCERD */
3244 s->xcer[3] = value & 0xffff;
3245 return;
3246 case 0x2e: /* RCERE */
3247 s->rcer[4] = value & 0xffff;
3248 return;
3249 case 0x30: /* RCERF */
3250 s->rcer[5] = value & 0xffff;
3251 return;
3252 case 0x32: /* XCERE */
3253 s->xcer[4] = value & 0xffff;
3254 return;
3255 case 0x34: /* XCERF */
3256 s->xcer[5] = value & 0xffff;
3257 return;
3258 case 0x36: /* RCERG */
3259 s->rcer[6] = value & 0xffff;
3260 return;
3261 case 0x38: /* RCERH */
3262 s->rcer[7] = value & 0xffff;
3263 return;
3264 case 0x3a: /* XCERG */
3265 s->xcer[6] = value & 0xffff;
3266 return;
3267 case 0x3c: /* XCERH */
3268 s->xcer[7] = value & 0xffff;
3269 return;
3270 }
3271
3272 OMAP_BAD_REG(addr);
3273 }
3274
3275 static void omap_mcbsp_writew(void *opaque, target_phys_addr_t addr,
3276 uint32_t value)
3277 {
3278 struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque;
3279 int offset = addr & OMAP_MPUI_REG_MASK;
3280
3281 if (offset == 0x04) { /* DXR */
3282 if (((s->xcr[0] >> 5) & 7) < 3) /* XWDLEN1 */
3283 return;
3284 if (s->tx_req > 3) {
3285 s->tx_req -= 4;
3286 if (s->codec && s->codec->cts) {
3287 s->codec->out.fifo[s->codec->out.len ++] =
3288 (value >> 24) & 0xff;
3289 s->codec->out.fifo[s->codec->out.len ++] =
3290 (value >> 16) & 0xff;
3291 s->codec->out.fifo[s->codec->out.len ++] =
3292 (value >> 8) & 0xff;
3293 s->codec->out.fifo[s->codec->out.len ++] =
3294 (value >> 0) & 0xff;
3295 }
3296 if (s->tx_req < 4)
3297 omap_mcbsp_tx_done(s);
3298 } else
3299 printf("%s: Tx FIFO overrun\n", __FUNCTION__);
3300 return;
3301 }
3302
3303 omap_badwidth_write16(opaque, addr, value);
3304 }
3305
3306 static CPUReadMemoryFunc * const omap_mcbsp_readfn[] = {
3307 omap_badwidth_read16,
3308 omap_mcbsp_read,
3309 omap_badwidth_read16,
3310 };
3311
3312 static CPUWriteMemoryFunc * const omap_mcbsp_writefn[] = {
3313 omap_badwidth_write16,
3314 omap_mcbsp_writeh,
3315 omap_mcbsp_writew,
3316 };
3317
3318 static void omap_mcbsp_reset(struct omap_mcbsp_s *s)
3319 {
3320 memset(&s->spcr, 0, sizeof(s->spcr));
3321 memset(&s->rcr, 0, sizeof(s->rcr));
3322 memset(&s->xcr, 0, sizeof(s->xcr));
3323 s->srgr[0] = 0x0001;
3324 s->srgr[1] = 0x2000;
3325 memset(&s->mcr, 0, sizeof(s->mcr));
3326 memset(&s->pcr, 0, sizeof(s->pcr));
3327 memset(&s->rcer, 0, sizeof(s->rcer));
3328 memset(&s->xcer, 0, sizeof(s->xcer));
3329 s->tx_req = 0;
3330 s->rx_req = 0;
3331 s->tx_rate = 0;
3332 s->rx_rate = 0;
3333 qemu_del_timer(s->source_timer);
3334 qemu_del_timer(s->sink_timer);
3335 }
3336
3337 struct omap_mcbsp_s *omap_mcbsp_init(target_phys_addr_t base,
3338 qemu_irq *irq, qemu_irq *dma, omap_clk clk)
3339 {
3340 int iomemtype;
3341 struct omap_mcbsp_s *s = (struct omap_mcbsp_s *)
3342 qemu_mallocz(sizeof(struct omap_mcbsp_s));
3343
3344 s->txirq = irq[0];
3345 s->rxirq = irq[1];
3346 s->txdrq = dma[0];
3347 s->rxdrq = dma[1];
3348 s->sink_timer = qemu_new_timer_ns(vm_clock, omap_mcbsp_sink_tick, s);
3349 s->source_timer = qemu_new_timer_ns(vm_clock, omap_mcbsp_source_tick, s);
3350 omap_mcbsp_reset(s);
3351
3352 iomemtype = cpu_register_io_memory(omap_mcbsp_readfn,
3353 omap_mcbsp_writefn, s, DEVICE_NATIVE_ENDIAN);
3354 cpu_register_physical_memory(base, 0x800, iomemtype);
3355
3356 return s;
3357 }
3358
3359 static void omap_mcbsp_i2s_swallow(void *opaque, int line, int level)
3360 {
3361 struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque;
3362
3363 if (s->rx_rate) {
3364 s->rx_req = s->codec->in.len;
3365 omap_mcbsp_rx_newdata(s);
3366 }
3367 }
3368
3369 static void omap_mcbsp_i2s_start(void *opaque, int line, int level)
3370 {
3371 struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque;
3372
3373 if (s->tx_rate) {
3374 s->tx_req = s->codec->out.size;
3375 omap_mcbsp_tx_newdata(s);
3376 }
3377 }
3378
3379 void omap_mcbsp_i2s_attach(struct omap_mcbsp_s *s, I2SCodec *slave)
3380 {
3381 s->codec = slave;
3382 slave->rx_swallow = qemu_allocate_irqs(omap_mcbsp_i2s_swallow, s, 1)[0];
3383 slave->tx_start = qemu_allocate_irqs(omap_mcbsp_i2s_start, s, 1)[0];
3384 }
3385
3386 /* LED Pulse Generators */
3387 struct omap_lpg_s {
3388 QEMUTimer *tm;
3389
3390 uint8_t control;
3391 uint8_t power;
3392 int64_t on;
3393 int64_t period;
3394 int clk;
3395 int cycle;
3396 };
3397
3398 static void omap_lpg_tick(void *opaque)
3399 {
3400 struct omap_lpg_s *s = opaque;
3401
3402 if (s->cycle)
3403 qemu_mod_timer(s->tm, qemu_get_clock_ms(rt_clock) + s->period - s->on);
3404 else
3405 qemu_mod_timer(s->tm, qemu_get_clock_ms(rt_clock) + s->on);
3406
3407 s->cycle = !s->cycle;
3408 printf("%s: LED is %s\n", __FUNCTION__, s->cycle ? "on" : "off");
3409 }
3410
3411 static void omap_lpg_update(struct omap_lpg_s *s)
3412 {
3413 int64_t on, period = 1, ticks = 1000;
3414 static const int per[8] = { 1, 2, 4, 8, 12, 16, 20, 24 };
3415
3416 if (~s->control & (1 << 6)) /* LPGRES */
3417 on = 0;
3418 else if (s->control & (1 << 7)) /* PERM_ON */
3419 on = period;
3420 else {
3421 period = muldiv64(ticks, per[s->control & 7], /* PERCTRL */
3422 256 / 32);
3423 on = (s->clk && s->power) ? muldiv64(ticks,
3424 per[(s->control >> 3) & 7], 256) : 0; /* ONCTRL */
3425 }
3426
3427 qemu_del_timer(s->tm);
3428 if (on == period && s->on < s->period)
3429 printf("%s: LED is on\n", __FUNCTION__);
3430 else if (on == 0 && s->on)
3431 printf("%s: LED is off\n", __FUNCTION__);
3432 else if (on && (on != s->on || period != s->period)) {
3433 s->cycle = 0;
3434 s->on = on;
3435 s->period = period;
3436 omap_lpg_tick(s);
3437 return;
3438 }
3439
3440 s->on = on;
3441 s->period = period;
3442 }
3443
3444 static void omap_lpg_reset(struct omap_lpg_s *s)
3445 {
3446 s->control = 0x00;
3447 s->power = 0x00;
3448 s->clk = 1;
3449 omap_lpg_update(s);
3450 }
3451
3452 static uint32_t omap_lpg_read(void *opaque, target_phys_addr_t addr)
3453 {
3454 struct omap_lpg_s *s = (struct omap_lpg_s *) opaque;
3455 int offset = addr & OMAP_MPUI_REG_MASK;
3456
3457 switch (offset) {
3458 case 0x00: /* LCR */
3459 return s->control;
3460
3461 case 0x04: /* PMR */
3462 return s->power;
3463 }
3464
3465 OMAP_BAD_REG(addr);
3466 return 0;
3467 }
3468
3469 static void omap_lpg_write(void *opaque, target_phys_addr_t addr,
3470 uint32_t value)
3471 {
3472 struct omap_lpg_s *s = (struct omap_lpg_s *) opaque;
3473 int offset = addr & OMAP_MPUI_REG_MASK;
3474
3475 switch (offset) {
3476 case 0x00: /* LCR */
3477 if (~value & (1 << 6)) /* LPGRES */
3478 omap_lpg_reset(s);
3479 s->control = value & 0xff;
3480 omap_lpg_update(s);
3481 return;
3482
3483 case 0x04: /* PMR */
3484 s->power = value & 0x01;
3485 omap_lpg_update(s);
3486 return;
3487
3488 default:
3489 OMAP_BAD_REG(addr);
3490 return;
3491 }
3492 }
3493
3494 static CPUReadMemoryFunc * const omap_lpg_readfn[] = {
3495 omap_lpg_read,
3496 omap_badwidth_read8,
3497 omap_badwidth_read8,
3498 };
3499
3500 static CPUWriteMemoryFunc * const omap_lpg_writefn[] = {
3501 omap_lpg_write,
3502 omap_badwidth_write8,
3503 omap_badwidth_write8,
3504 };
3505
3506 static void omap_lpg_clk_update(void *opaque, int line, int on)
3507 {
3508 struct omap_lpg_s *s = (struct omap_lpg_s *) opaque;
3509
3510 s->clk = on;
3511 omap_lpg_update(s);
3512 }
3513
3514 static struct omap_lpg_s *omap_lpg_init(target_phys_addr_t base, omap_clk clk)
3515 {
3516 int iomemtype;
3517 struct omap_lpg_s *s = (struct omap_lpg_s *)
3518 qemu_mallocz(sizeof(struct omap_lpg_s));
3519
3520 s->tm = qemu_new_timer_ms(rt_clock, omap_lpg_tick, s);
3521
3522 omap_lpg_reset(s);
3523
3524 iomemtype = cpu_register_io_memory(omap_lpg_readfn,
3525 omap_lpg_writefn, s, DEVICE_NATIVE_ENDIAN);
3526 cpu_register_physical_memory(base, 0x800, iomemtype);
3527
3528 omap_clk_adduser(clk, qemu_allocate_irqs(omap_lpg_clk_update, s, 1)[0]);
3529
3530 return s;
3531 }
3532
3533 /* MPUI Peripheral Bridge configuration */
3534 static uint32_t omap_mpui_io_read(void *opaque, target_phys_addr_t addr)
3535 {
3536 if (addr == OMAP_MPUI_BASE) /* CMR */
3537 return 0xfe4d;
3538
3539 OMAP_BAD_REG(addr);
3540 return 0;
3541 }
3542
3543 static CPUReadMemoryFunc * const omap_mpui_io_readfn[] = {
3544 omap_badwidth_read16,
3545 omap_mpui_io_read,
3546 omap_badwidth_read16,
3547 };
3548
3549 static CPUWriteMemoryFunc * const omap_mpui_io_writefn[] = {
3550 omap_badwidth_write16,
3551 omap_badwidth_write16,
3552 omap_badwidth_write16,
3553 };
3554
3555 static void omap_setup_mpui_io(struct omap_mpu_state_s *mpu)
3556 {
3557 int iomemtype = cpu_register_io_memory(omap_mpui_io_readfn,
3558 omap_mpui_io_writefn, mpu, DEVICE_NATIVE_ENDIAN);
3559 cpu_register_physical_memory(OMAP_MPUI_BASE, 0x7fff, iomemtype);
3560 }
3561
3562 /* General chip reset */
3563 static void omap1_mpu_reset(void *opaque)
3564 {
3565 struct omap_mpu_state_s *mpu = (struct omap_mpu_state_s *) opaque;
3566
3567 omap_inth_reset(mpu->ih[0]);
3568 omap_inth_reset(mpu->ih[1]);
3569 omap_dma_reset(mpu->dma);
3570 omap_mpu_timer_reset(mpu->timer[0]);
3571 omap_mpu_timer_reset(mpu->timer[1]);
3572 omap_mpu_timer_reset(mpu->timer[2]);
3573 omap_wd_timer_reset(mpu->wdt);
3574 omap_os_timer_reset(mpu->os_timer);
3575 omap_lcdc_reset(mpu->lcd);
3576 omap_ulpd_pm_reset(mpu);
3577 omap_pin_cfg_reset(mpu);
3578 omap_mpui_reset(mpu);
3579 omap_tipb_bridge_reset(mpu->private_tipb);
3580 omap_tipb_bridge_reset(mpu->public_tipb);
3581 omap_dpll_reset(&mpu->dpll[0]);
3582 omap_dpll_reset(&mpu->dpll[1]);
3583 omap_dpll_reset(&mpu->dpll[2]);
3584 omap_uart_reset(mpu->uart[0]);
3585 omap_uart_reset(mpu->uart[1]);
3586 omap_uart_reset(mpu->uart[2]);
3587 omap_mmc_reset(mpu->mmc);
3588 omap_mpuio_reset(mpu->mpuio);
3589 omap_uwire_reset(mpu->microwire);
3590 omap_pwl_reset(mpu);
3591 omap_pwt_reset(mpu);
3592 omap_i2c_reset(mpu->i2c[0]);
3593 omap_rtc_reset(mpu->rtc);
3594 omap_mcbsp_reset(mpu->mcbsp1);
3595 omap_mcbsp_reset(mpu->mcbsp2);
3596 omap_mcbsp_reset(mpu->mcbsp3);
3597 omap_lpg_reset(mpu->led[0]);
3598 omap_lpg_reset(mpu->led[1]);
3599 omap_clkm_reset(mpu);
3600 cpu_reset(mpu->env);
3601 }
3602
3603 static const struct omap_map_s {
3604 target_phys_addr_t phys_dsp;
3605 target_phys_addr_t phys_mpu;
3606 uint32_t size;
3607 const char *name;
3608 } omap15xx_dsp_mm[] = {
3609 /* Strobe 0 */
3610 { 0xe1010000, 0xfffb0000, 0x800, "UART1 BT" }, /* CS0 */
3611 { 0xe1010800, 0xfffb0800, 0x800, "UART2 COM" }, /* CS1 */
3612 { 0xe1011800, 0xfffb1800, 0x800, "McBSP1 audio" }, /* CS3 */
3613 { 0xe1012000, 0xfffb2000, 0x800, "MCSI2 communication" }, /* CS4 */
3614 { 0xe1012800, 0xfffb2800, 0x800, "MCSI1 BT u-Law" }, /* CS5 */
3615 { 0xe1013000, 0xfffb3000, 0x800, "uWire" }, /* CS6 */
3616 { 0xe1013800, 0xfffb3800, 0x800, "I^2C" }, /* CS7 */
3617 { 0xe1014000, 0xfffb4000, 0x800, "USB W2FC" }, /* CS8 */
3618 { 0xe1014800, 0xfffb4800, 0x800, "RTC" }, /* CS9 */
3619 { 0xe1015000, 0xfffb5000, 0x800, "MPUIO" }, /* CS10 */
3620 { 0xe1015800, 0xfffb5800, 0x800, "PWL" }, /* CS11 */
3621 { 0xe1016000, 0xfffb6000, 0x800, "PWT" }, /* CS12 */
3622 { 0xe1017000, 0xfffb7000, 0x800, "McBSP3" }, /* CS14 */
3623 { 0xe1017800, 0xfffb7800, 0x800, "MMC" }, /* CS15 */
3624 { 0xe1019000, 0xfffb9000, 0x800, "32-kHz timer" }, /* CS18 */
3625 { 0xe1019800, 0xfffb9800, 0x800, "UART3" }, /* CS19 */
3626 { 0xe101c800, 0xfffbc800, 0x800, "TIPB switches" }, /* CS25 */
3627 /* Strobe 1 */
3628 { 0xe101e000, 0xfffce000, 0x800, "GPIOs" }, /* CS28 */
3629
3630 { 0 }
3631 };
3632
3633 static void omap_setup_dsp_mapping(const struct omap_map_s *map)
3634 {
3635 int io;
3636
3637 for (; map->phys_dsp; map ++) {
3638 io = cpu_get_physical_page_desc(map->phys_mpu);
3639
3640 cpu_register_physical_memory(map->phys_dsp, map->size, io);
3641 }
3642 }
3643
3644 void omap_mpu_wakeup(void *opaque, int irq, int req)
3645 {
3646 struct omap_mpu_state_s *mpu = (struct omap_mpu_state_s *) opaque;
3647
3648 if (mpu->env->halted)
3649 cpu_interrupt(mpu->env, CPU_INTERRUPT_EXITTB);
3650 }
3651
3652 static const struct dma_irq_map omap1_dma_irq_map[] = {
3653 { 0, OMAP_INT_DMA_CH0_6 },
3654 { 0, OMAP_INT_DMA_CH1_7 },
3655 { 0, OMAP_INT_DMA_CH2_8 },
3656 { 0, OMAP_INT_DMA_CH3 },
3657 { 0, OMAP_INT_DMA_CH4 },
3658 { 0, OMAP_INT_DMA_CH5 },
3659 { 1, OMAP_INT_1610_DMA_CH6 },
3660 { 1, OMAP_INT_1610_DMA_CH7 },
3661 { 1, OMAP_INT_1610_DMA_CH8 },
3662 { 1, OMAP_INT_1610_DMA_CH9 },
3663 { 1, OMAP_INT_1610_DMA_CH10 },
3664 { 1, OMAP_INT_1610_DMA_CH11 },
3665 { 1, OMAP_INT_1610_DMA_CH12 },
3666 { 1, OMAP_INT_1610_DMA_CH13 },
3667 { 1, OMAP_INT_1610_DMA_CH14 },
3668 { 1, OMAP_INT_1610_DMA_CH15 }
3669 };
3670
3671 /* DMA ports for OMAP1 */
3672 static int omap_validate_emiff_addr(struct omap_mpu_state_s *s,
3673 target_phys_addr_t addr)
3674 {
3675 return range_covers_byte(OMAP_EMIFF_BASE, s->sdram_size, addr);
3676 }
3677
3678 static int omap_validate_emifs_addr(struct omap_mpu_state_s *s,
3679 target_phys_addr_t addr)
3680 {
3681 return range_covers_byte(OMAP_EMIFS_BASE, OMAP_EMIFF_BASE - OMAP_EMIFS_BASE,
3682 addr);
3683 }
3684
3685 static int omap_validate_imif_addr(struct omap_mpu_state_s *s,
3686 target_phys_addr_t addr)
3687 {
3688 return range_covers_byte(OMAP_IMIF_BASE, s->sram_size, addr);
3689 }
3690
3691 static int omap_validate_tipb_addr(struct omap_mpu_state_s *s,
3692 target_phys_addr_t addr)
3693 {
3694 return range_covers_byte(0xfffb0000, 0xffff0000 - 0xfffb0000, addr);
3695 }
3696
3697 static int omap_validate_local_addr(struct omap_mpu_state_s *s,
3698 target_phys_addr_t addr)
3699 {
3700 return range_covers_byte(OMAP_LOCALBUS_BASE, 0x1000000, addr);
3701 }
3702
3703 static int omap_validate_tipb_mpui_addr(struct omap_mpu_state_s *s,
3704 target_phys_addr_t addr)
3705 {
3706 return range_covers_byte(0xe1010000, 0xe1020004 - 0xe1010000, addr);
3707 }
3708
3709 struct omap_mpu_state_s *omap310_mpu_init(unsigned long sdram_size,
3710 const char *core)
3711 {
3712 int i;
3713 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *)
3714 qemu_mallocz(sizeof(struct omap_mpu_state_s));
3715 ram_addr_t imif_base, emiff_base;
3716 qemu_irq *cpu_irq;
3717 qemu_irq dma_irqs[6];
3718 DriveInfo *dinfo;
3719
3720 if (!core)
3721 core = "ti925t";
3722
3723 /* Core */
3724 s->mpu_model = omap310;
3725 s->env = cpu_init(core);
3726 if (!s->env) {
3727 fprintf(stderr, "Unable to find CPU definition\n");
3728 exit(1);
3729 }
3730 s->sdram_size = sdram_size;
3731 s->sram_size = OMAP15XX_SRAM_SIZE;
3732
3733 s->wakeup = qemu_allocate_irqs(omap_mpu_wakeup, s, 1)[0];
3734
3735 /* Clocks */
3736 omap_clk_init(s);
3737
3738 /* Memory-mapped stuff */
3739 cpu_register_physical_memory(OMAP_EMIFF_BASE, s->sdram_size,
3740 (emiff_base = qemu_ram_alloc(NULL, "omap1.dram",
3741 s->sdram_size)) | IO_MEM_RAM);
3742 cpu_register_physical_memory(OMAP_IMIF_BASE, s->sram_size,
3743 (imif_base = qemu_ram_alloc(NULL, "omap1.sram",
3744 s->sram_size)) | IO_MEM_RAM);
3745
3746 omap_clkm_init(0xfffece00, 0xe1008000, s);
3747
3748 cpu_irq = arm_pic_init_cpu(s->env);
3749 s->ih[0] = omap_inth_init(0xfffecb00, 0x100, 1, &s->irq[0],
3750 cpu_irq[ARM_PIC_CPU_IRQ], cpu_irq[ARM_PIC_CPU_FIQ],
3751 omap_findclk(s, "arminth_ck"));
3752 s->ih[1] = omap_inth_init(0xfffe0000, 0x800, 1, &s->irq[1],
3753 omap_inth_get_pin(s->ih[0], OMAP_INT_15XX_IH2_IRQ),
3754 NULL, omap_findclk(s, "arminth_ck"));
3755
3756 for (i = 0; i < 6; i ++)
3757 dma_irqs[i] =
3758 s->irq[omap1_dma_irq_map[i].ih][omap1_dma_irq_map[i].intr];
3759 s->dma = omap_dma_init(0xfffed800, dma_irqs, s->irq[0][OMAP_INT_DMA_LCD],
3760 s, omap_findclk(s, "dma_ck"), omap_dma_3_1);
3761
3762 s->port[emiff ].addr_valid = omap_validate_emiff_addr;
3763 s->port[emifs ].addr_valid = omap_validate_emifs_addr;
3764 s->port[imif ].addr_valid = omap_validate_imif_addr;
3765 s->port[tipb ].addr_valid = omap_validate_tipb_addr;
3766 s->port[local ].addr_valid = omap_validate_local_addr;
3767 s->port[tipb_mpui].addr_valid = omap_validate_tipb_mpui_addr;
3768
3769 /* Register SDRAM and SRAM DMA ports for fast transfers. */
3770 soc_dma_port_add_mem_ram(s->dma,
3771 emiff_base, OMAP_EMIFF_BASE, s->sdram_size);
3772 soc_dma_port_add_mem_ram(s->dma,
3773 imif_base, OMAP_IMIF_BASE, s->sram_size);
3774
3775 s->timer[0] = omap_mpu_timer_init(0xfffec500,
3776 s->irq[0][OMAP_INT_TIMER1],
3777 omap_findclk(s, "mputim_ck"));
3778 s->timer[1] = omap_mpu_timer_init(0xfffec600,
3779 s->irq[0][OMAP_INT_TIMER2],
3780 omap_findclk(s, "mputim_ck"));
3781 s->timer[2] = omap_mpu_timer_init(0xfffec700,
3782 s->irq[0][OMAP_INT_TIMER3],
3783 omap_findclk(s, "mputim_ck"));
3784
3785 s->wdt = omap_wd_timer_init(0xfffec800,
3786 s->irq[0][OMAP_INT_WD_TIMER],
3787 omap_findclk(s, "armwdt_ck"));
3788
3789 s->os_timer = omap_os_timer_init(0xfffb9000,
3790 s->irq[1][OMAP_INT_OS_TIMER],
3791 omap_findclk(s, "clk32-kHz"));
3792
3793 s->lcd = omap_lcdc_init(0xfffec000, s->irq[0][OMAP_INT_LCD_CTRL],
3794 omap_dma_get_lcdch(s->dma), imif_base, emiff_base,
3795 omap_findclk(s, "lcd_ck"));
3796
3797 omap_ulpd_pm_init(0xfffe0800, s);
3798 omap_pin_cfg_init(0xfffe1000, s);
3799 omap_id_init(s);
3800
3801 omap_mpui_init(0xfffec900, s);
3802
3803 s->private_tipb = omap_tipb_bridge_init(0xfffeca00,
3804 s->irq[0][OMAP_INT_BRIDGE_PRIV],
3805 omap_findclk(s, "tipb_ck"));
3806 s->public_tipb = omap_tipb_bridge_init(0xfffed300,
3807 s->irq[0][OMAP_INT_BRIDGE_PUB],
3808 omap_findclk(s, "tipb_ck"));
3809
3810 omap_tcmi_init(0xfffecc00, s);
3811
3812 s->uart[0] = omap_uart_init(0xfffb0000, s->irq[1][OMAP_INT_UART1],
3813 omap_findclk(s, "uart1_ck"),
3814 omap_findclk(s, "uart1_ck"),
3815 s->drq[OMAP_DMA_UART1_TX], s->drq[OMAP_DMA_UART1_RX],
3816 "uart1",
3817 serial_hds[0]);
3818 s->uart[1] = omap_uart_init(0xfffb0800, s->irq[1][OMAP_INT_UART2],
3819 omap_findclk(s, "uart2_ck"),
3820 omap_findclk(s, "uart2_ck"),
3821 s->drq[OMAP_DMA_UART2_TX], s->drq[OMAP_DMA_UART2_RX],
3822 "uart2",
3823 serial_hds[0] ? serial_hds[1] : NULL);
3824 s->uart[2] = omap_uart_init(0xfffb9800, s->irq[0][OMAP_INT_UART3],
3825 omap_findclk(s, "uart3_ck"),
3826 omap_findclk(s, "uart3_ck"),
3827 s->drq[OMAP_DMA_UART3_TX], s->drq[OMAP_DMA_UART3_RX],
3828 "uart3",
3829 serial_hds[0] && serial_hds[1] ? serial_hds[2] : NULL);
3830
3831 omap_dpll_init(&s->dpll[0], 0xfffecf00, omap_findclk(s, "dpll1"));
3832 omap_dpll_init(&s->dpll[1], 0xfffed000, omap_findclk(s, "dpll2"));
3833 omap_dpll_init(&s->dpll[2], 0xfffed100, omap_findclk(s, "dpll3"));
3834
3835 dinfo = drive_get(IF_SD, 0, 0);
3836 if (!dinfo) {
3837 fprintf(stderr, "qemu: missing SecureDigital device\n");
3838 exit(1);
3839 }
3840 s->mmc = omap_mmc_init(0xfffb7800, dinfo->bdrv,
3841 s->irq[1][OMAP_INT_OQN], &s->drq[OMAP_DMA_MMC_TX],
3842 omap_findclk(s, "mmc_ck"));
3843
3844 s->mpuio = omap_mpuio_init(0xfffb5000,
3845 s->irq[1][OMAP_INT_KEYBOARD], s->irq[1][OMAP_INT_MPUIO],
3846 s->wakeup, omap_findclk(s, "clk32-kHz"));
3847
3848 s->gpio = qdev_create(NULL, "omap-gpio");
3849 qdev_prop_set_int32(s->gpio, "mpu_model", s->mpu_model);
3850 qdev_init_nofail(s->gpio);
3851 sysbus_connect_irq(sysbus_from_qdev(s->gpio), 0,
3852 s->irq[0][OMAP_INT_GPIO_BANK1]);
3853 sysbus_mmio_map(sysbus_from_qdev(s->gpio), 0, 0xfffce000);
3854
3855 s->microwire = omap_uwire_init(0xfffb3000, &s->irq[1][OMAP_INT_uWireTX],
3856 s->drq[OMAP_DMA_UWIRE_TX], omap_findclk(s, "mpuper_ck"));
3857
3858 omap_pwl_init(0xfffb5800, s, omap_findclk(s, "armxor_ck"));
3859 omap_pwt_init(0xfffb6000, s, omap_findclk(s, "armxor_ck"));
3860
3861 s->i2c[0] = omap_i2c_init(0xfffb3800, s->irq[1][OMAP_INT_I2C],
3862 &s->drq[OMAP_DMA_I2C_RX], omap_findclk(s, "mpuper_ck"));
3863
3864 s->rtc = omap_rtc_init(0xfffb4800, &s->irq[1][OMAP_INT_RTC_TIMER],
3865 omap_findclk(s, "clk32-kHz"));
3866
3867 s->mcbsp1 = omap_mcbsp_init(0xfffb1800, &s->irq[1][OMAP_INT_McBSP1TX],
3868 &s->drq[OMAP_DMA_MCBSP1_TX], omap_findclk(s, "dspxor_ck"));
3869 s->mcbsp2 = omap_mcbsp_init(0xfffb1000, &s->irq[0][OMAP_INT_310_McBSP2_TX],
3870 &s->drq[OMAP_DMA_MCBSP2_TX], omap_findclk(s, "mpuper_ck"));
3871 s->mcbsp3 = omap_mcbsp_init(0xfffb7000, &s->irq[1][OMAP_INT_McBSP3TX],
3872 &s->drq[OMAP_DMA_MCBSP3_TX], omap_findclk(s, "dspxor_ck"));
3873
3874 s->led[0] = omap_lpg_init(0xfffbd000, omap_findclk(s, "clk32-kHz"));
3875 s->led[1] = omap_lpg_init(0xfffbd800, omap_findclk(s, "clk32-kHz"));
3876
3877 /* Register mappings not currenlty implemented:
3878 * MCSI2 Comm fffb2000 - fffb27ff (not mapped on OMAP310)
3879 * MCSI1 Bluetooth fffb2800 - fffb2fff (not mapped on OMAP310)
3880 * USB W2FC fffb4000 - fffb47ff
3881 * Camera Interface fffb6800 - fffb6fff
3882 * USB Host fffba000 - fffba7ff
3883 * FAC fffba800 - fffbafff
3884 * HDQ/1-Wire fffbc000 - fffbc7ff
3885 * TIPB switches fffbc800 - fffbcfff
3886 * Mailbox fffcf000 - fffcf7ff
3887 * Local bus IF fffec100 - fffec1ff
3888 * Local bus MMU fffec200 - fffec2ff
3889 * DSP MMU fffed200 - fffed2ff
3890 */
3891
3892 omap_setup_dsp_mapping(omap15xx_dsp_mm);
3893 omap_setup_mpui_io(s);
3894
3895 qemu_register_reset(omap1_mpu_reset, s);
3896
3897 return s;
3898 }
Anthony Liguori's QEMU tree