hw/intc/arm_gic_common.c

   1 /*
   2  * ARM GIC support - common bits of emulated and KVM kernel model
   3  *
   4  * Copyright (c) 2012 Linaro Limited
   5  * Written by Peter Maydell
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation, either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License along
  18  * with this program; if not, see <http://www.gnu.org/licenses/>.
  19  */
  20
  21 #include "qemu/osdep.h"
  22 #include "qapi/error.h"
  23 #include "qemu/module.h"
  24 #include "gic_internal.h"
  25 #include "hw/arm/linux-boot-if.h"
  26 #include "hw/qdev-properties.h"
  27 #include "migration/vmstate.h"
  28
  29 static int gic_pre_save(void *opaque)
  30 {
  31     GICState *s = (GICState *)opaque;
  32     ARMGICCommonClass *c = ARM_GIC_COMMON_GET_CLASS(s);
  33
  34     if (c->pre_save) {
  35         c->pre_save(s);
  36     }
  37
  38     return 0;
  39 }
  40
  41 static int gic_post_load(void *opaque, int version_id)
  42 {
  43     GICState *s = (GICState *)opaque;
  44     ARMGICCommonClass *c = ARM_GIC_COMMON_GET_CLASS(s);
  45
  46     if (c->post_load) {
  47         c->post_load(s);
  48     }
  49     return 0;
  50 }
  51
  52 static bool gic_virt_state_needed(void *opaque)
  53 {
  54     GICState *s = (GICState *)opaque;
  55
  56     return s->virt_extn;
  57 }
  58
  59 static const VMStateDescription vmstate_gic_irq_state = {
  60     .name = "arm_gic_irq_state",
  61     .version_id = 1,
  62     .minimum_version_id = 1,
  63     .fields = (VMStateField[]) {
  64         VMSTATE_UINT8(enabled, gic_irq_state),
  65         VMSTATE_UINT8(pending, gic_irq_state),
  66         VMSTATE_UINT8(active, gic_irq_state),
  67         VMSTATE_UINT8(level, gic_irq_state),
  68         VMSTATE_BOOL(model, gic_irq_state),
  69         VMSTATE_BOOL(edge_trigger, gic_irq_state),
  70         VMSTATE_UINT8(group, gic_irq_state),
  71         VMSTATE_END_OF_LIST()
  72     }
  73 };
  74
  75 static const VMStateDescription vmstate_gic_virt_state = {
  76     .name = "arm_gic_virt_state",
  77     .version_id = 1,
  78     .minimum_version_id = 1,
  79     .needed = gic_virt_state_needed,
  80     .fields = (VMStateField[]) {
  81         /* Virtual interface */
  82         VMSTATE_UINT32_ARRAY(h_hcr, GICState, GIC_NCPU),
  83         VMSTATE_UINT32_ARRAY(h_misr, GICState, GIC_NCPU),
  84         VMSTATE_UINT32_2DARRAY(h_lr, GICState, GIC_MAX_LR, GIC_NCPU),
  85         VMSTATE_UINT32_ARRAY(h_apr, GICState, GIC_NCPU),
  86
  87         /* Virtual CPU interfaces */
  88         VMSTATE_UINT32_SUB_ARRAY(cpu_ctlr, GICState, GIC_NCPU, GIC_NCPU),
  89         VMSTATE_UINT16_SUB_ARRAY(priority_mask, GICState, GIC_NCPU, GIC_NCPU),
  90         VMSTATE_UINT16_SUB_ARRAY(running_priority, GICState, GIC_NCPU, GIC_NCPU),
  91         VMSTATE_UINT16_SUB_ARRAY(current_pending, GICState, GIC_NCPU, GIC_NCPU),
  92         VMSTATE_UINT8_SUB_ARRAY(bpr, GICState, GIC_NCPU, GIC_NCPU),
  93         VMSTATE_UINT8_SUB_ARRAY(abpr, GICState, GIC_NCPU, GIC_NCPU),
  94
  95         VMSTATE_END_OF_LIST()
  96     }
  97 };
  98
  99 static const VMStateDescription vmstate_gic = {
 100     .name = "arm_gic",
 101     .version_id = 12,
 102     .minimum_version_id = 12,
 103     .pre_save = gic_pre_save,
 104     .post_load = gic_post_load,
 105     .fields = (VMStateField[]) {
 106         VMSTATE_UINT32(ctlr, GICState),
 107         VMSTATE_UINT32_SUB_ARRAY(cpu_ctlr, GICState, 0, GIC_NCPU),
 108         VMSTATE_STRUCT_ARRAY(irq_state, GICState, GIC_MAXIRQ, 1,
 109                              vmstate_gic_irq_state, gic_irq_state),
 110         VMSTATE_UINT8_ARRAY(irq_target, GICState, GIC_MAXIRQ),
 111         VMSTATE_UINT8_2DARRAY(priority1, GICState, GIC_INTERNAL, GIC_NCPU),
 112         VMSTATE_UINT8_ARRAY(priority2, GICState, GIC_MAXIRQ - GIC_INTERNAL),
 113         VMSTATE_UINT8_2DARRAY(sgi_pending, GICState, GIC_NR_SGIS, GIC_NCPU),
 114         VMSTATE_UINT16_SUB_ARRAY(priority_mask, GICState, 0, GIC_NCPU),
 115         VMSTATE_UINT16_SUB_ARRAY(running_priority, GICState, 0, GIC_NCPU),
 116         VMSTATE_UINT16_SUB_ARRAY(current_pending, GICState, 0, GIC_NCPU),
 117         VMSTATE_UINT8_SUB_ARRAY(bpr, GICState, 0, GIC_NCPU),
 118         VMSTATE_UINT8_SUB_ARRAY(abpr, GICState, 0, GIC_NCPU),
 119         VMSTATE_UINT32_2DARRAY(apr, GICState, GIC_NR_APRS, GIC_NCPU),
 120         VMSTATE_UINT32_2DARRAY(nsapr, GICState, GIC_NR_APRS, GIC_NCPU),
 121         VMSTATE_END_OF_LIST()
 122     },
 123     .subsections = (const VMStateDescription * []) {
 124         &vmstate_gic_virt_state,
 125         NULL
 126     }
 127 };
 128
 129 void gic_init_irqs_and_mmio(GICState *s, qemu_irq_handler handler,
 130                             const MemoryRegionOps *ops,
 131                             const MemoryRegionOps *virt_ops)
 132 {
 133     SysBusDevice *sbd = SYS_BUS_DEVICE(s);
 134     int i = s->num_irq - GIC_INTERNAL;
 135
 136     /* For the GIC, also expose incoming GPIO lines for PPIs for each CPU.
 137      * GPIO array layout is thus:
 138      *  [0..N-1] SPIs
 139      *  [N..N+31] PPIs for CPU 0
 140      *  [N+32..N+63] PPIs for CPU 1
 141      *   ...
 142      */
 143     i += (GIC_INTERNAL * s->num_cpu);
 144     qdev_init_gpio_in(DEVICE(s), handler, i);
 145
 146     for (i = 0; i < s->num_cpu; i++) {
 147         sysbus_init_irq(sbd, &s->parent_irq[i]);
 148     }
 149     for (i = 0; i < s->num_cpu; i++) {
 150         sysbus_init_irq(sbd, &s->parent_fiq[i]);
 151     }
 152     for (i = 0; i < s->num_cpu; i++) {
 153         sysbus_init_irq(sbd, &s->parent_virq[i]);
 154     }
 155     for (i = 0; i < s->num_cpu; i++) {
 156         sysbus_init_irq(sbd, &s->parent_vfiq[i]);
 157     }
 158     if (s->virt_extn) {
 159         for (i = 0; i < s->num_cpu; i++) {
 160             sysbus_init_irq(sbd, &s->maintenance_irq[i]);
 161         }
 162     }
 163
 164     /* Distributor */
 165     memory_region_init_io(&s->iomem, OBJECT(s), ops, s, "gic_dist", 0x1000);
 166     sysbus_init_mmio(sbd, &s->iomem);
 167
 168     /* This is the main CPU interface "for this core". It is always
 169      * present because it is required by both software emulation and KVM.
 170      */
 171     memory_region_init_io(&s->cpuiomem[0], OBJECT(s), ops ? &ops[1] : NULL,
 172                           s, "gic_cpu", s->revision == 2 ? 0x2000 : 0x100);
 173     sysbus_init_mmio(sbd, &s->cpuiomem[0]);
 174
 175     if (s->virt_extn) {
 176         memory_region_init_io(&s->vifaceiomem[0], OBJECT(s), virt_ops,
 177                               s, "gic_viface", 0x1000);
 178         sysbus_init_mmio(sbd, &s->vifaceiomem[0]);
 179
 180         memory_region_init_io(&s->vcpuiomem, OBJECT(s),
 181                               virt_ops ? &virt_ops[1] : NULL,
 182                               s, "gic_vcpu", 0x2000);
 183         sysbus_init_mmio(sbd, &s->vcpuiomem);
 184     }
 185 }
 186
 187 static void arm_gic_common_realize(DeviceState *dev, Error **errp)
 188 {
 189     GICState *s = ARM_GIC_COMMON(dev);
 190     int num_irq = s->num_irq;
 191
 192     if (s->num_cpu > GIC_NCPU) {
 193         error_setg(errp, "requested %u CPUs exceeds GIC maximum %d",
 194                    s->num_cpu, GIC_NCPU);
 195         return;
 196     }
 197     if (s->num_irq > GIC_MAXIRQ) {
 198         error_setg(errp,
 199                    "requested %u interrupt lines exceeds GIC maximum %d",
 200                    num_irq, GIC_MAXIRQ);
 201         return;
 202     }
 203     /* ITLinesNumber is represented as (N / 32) - 1 (see
 204      * gic_dist_readb) so this is an implementation imposed
 205      * restriction, not an architectural one:
 206      */
 207     if (s->num_irq < 32 || (s->num_irq % 32)) {
 208         error_setg(errp,
 209                    "%d interrupt lines unsupported: not divisible by 32",
 210                    num_irq);
 211         return;
 212     }
 213
 214     if (s->security_extn &&
 215         (s->revision == REV_11MPCORE)) {
 216         error_setg(errp, "this GIC revision does not implement "
 217                    "the security extensions");
 218         return;
 219     }
 220
 221     if (s->virt_extn) {
 222         if (s->revision != 2) {
 223             error_setg(errp, "GIC virtualization extensions are only "
 224                        "supported by revision 2");
 225             return;
 226         }
 227
 228         /* For now, set the number of implemented LRs to 4, as found in most
 229          * real GICv2. This could be promoted as a QOM property if we need to
 230          * emulate a variant with another num_lrs.
 231          */
 232         s->num_lrs = 4;
 233     }
 234 }
 235
 236 static inline void arm_gic_common_reset_irq_state(GICState *s, int first_cpu,
 237                                                   int resetprio)
 238 {
 239     int i, j;
 240
 241     for (i = first_cpu; i < first_cpu + s->num_cpu; i++) {
 242         if (s->revision == REV_11MPCORE) {
 243             s->priority_mask[i] = 0xf0;
 244         } else {
 245             s->priority_mask[i] = resetprio;
 246         }
 247         s->current_pending[i] = 1023;
 248         s->running_priority[i] = 0x100;
 249         s->cpu_ctlr[i] = 0;
 250         s->bpr[i] = gic_is_vcpu(i) ? GIC_VIRT_MIN_BPR : GIC_MIN_BPR;
 251         s->abpr[i] = gic_is_vcpu(i) ? GIC_VIRT_MIN_ABPR : GIC_MIN_ABPR;
 252
 253         if (!gic_is_vcpu(i)) {
 254             for (j = 0; j < GIC_INTERNAL; j++) {
 255                 s->priority1[j][i] = resetprio;
 256             }
 257             for (j = 0; j < GIC_NR_SGIS; j++) {
 258                 s->sgi_pending[j][i] = 0;
 259             }
 260         }
 261     }
 262 }
 263
 264 static void arm_gic_common_reset_hold(Object *obj)
 265 {
 266     GICState *s = ARM_GIC_COMMON(obj);
 267     int i, j;
 268     int resetprio;
 269
 270     /* If we're resetting a TZ-aware GIC as if secure firmware
 271      * had set it up ready to start a kernel in non-secure,
 272      * we need to set interrupt priorities to a "zero for the
 273      * NS view" value. This is particularly critical for the
 274      * priority_mask[] values, because if they are zero then NS
 275      * code cannot ever rewrite the priority to anything else.
 276      */
 277     if (s->security_extn && s->irq_reset_nonsecure) {
 278         resetprio = 0x80;
 279     } else {
 280         resetprio = 0;
 281     }
 282
 283     memset(s->irq_state, 0, GIC_MAXIRQ * sizeof(gic_irq_state));
 284     arm_gic_common_reset_irq_state(s, 0, resetprio);
 285
 286     if (s->virt_extn) {
 287         /* vCPU states are stored at indexes GIC_NCPU .. GIC_NCPU+num_cpu.
 288          * The exposed vCPU interface does not have security extensions.
 289          */
 290         arm_gic_common_reset_irq_state(s, GIC_NCPU, 0);
 291     }
 292
 293     for (i = 0; i < GIC_NR_SGIS; i++) {
 294         GIC_DIST_SET_ENABLED(i, ALL_CPU_MASK);
 295         GIC_DIST_SET_EDGE_TRIGGER(i);
 296     }
 297
 298     for (i = 0; i < ARRAY_SIZE(s->priority2); i++) {
 299         s->priority2[i] = resetprio;
 300     }
 301
 302     for (i = 0; i < GIC_MAXIRQ; i++) {
 303         /* For uniprocessor GICs all interrupts always target the sole CPU */
 304         if (s->num_cpu == 1) {
 305             s->irq_target[i] = 1;
 306         } else {
 307             s->irq_target[i] = 0;
 308         }
 309     }
 310     if (s->security_extn && s->irq_reset_nonsecure) {
 311         for (i = 0; i < GIC_MAXIRQ; i++) {
 312             GIC_DIST_SET_GROUP(i, ALL_CPU_MASK);
 313         }
 314     }
 315
 316     if (s->virt_extn) {
 317         for (i = 0; i < s->num_lrs; i++) {
 318             for (j = 0; j < s->num_cpu; j++) {
 319                 s->h_lr[i][j] = 0;
 320             }
 321         }
 322
 323         for (i = 0; i < s->num_cpu; i++) {
 324             s->h_hcr[i] = 0;
 325             s->h_misr[i] = 0;
 326         }
 327     }
 328
 329     s->ctlr = 0;
 330 }
 331
 332 static void arm_gic_common_linux_init(ARMLinuxBootIf *obj,
 333                                       bool secure_boot)
 334 {
 335     GICState *s = ARM_GIC_COMMON(obj);
 336
 337     if (s->security_extn && !secure_boot) {
 338         /* We're directly booting a kernel into NonSecure. If this GIC
 339          * implements the security extensions then we must configure it
 340          * to have all the interrupts be NonSecure (this is a job that
 341          * is done by the Secure boot firmware in real hardware, and in
 342          * this mode QEMU is acting as a minimalist firmware-and-bootloader
 343          * equivalent).
 344          */
 345         s->irq_reset_nonsecure = true;
 346     }
 347 }
 348
 349 static Property arm_gic_common_properties[] = {
 350     DEFINE_PROP_UINT32("num-cpu", GICState, num_cpu, 1),
 351     DEFINE_PROP_UINT32("num-irq", GICState, num_irq, 32),
 352     /* Revision can be 1 or 2 for GIC architecture specification
 353      * versions 1 or 2, or 0 to indicate the legacy 11MPCore GIC.
 354      */
 355     DEFINE_PROP_UINT32("revision", GICState, revision, 1),
 356     /* True if the GIC should implement the security extensions */
 357     DEFINE_PROP_BOOL("has-security-extensions", GICState, security_extn, 0),
 358     /* True if the GIC should implement the virtualization extensions */
 359     DEFINE_PROP_BOOL("has-virtualization-extensions", GICState, virt_extn, 0),
 360     DEFINE_PROP_UINT32("num-priority-bits", GICState, n_prio_bits, 8),
 361     DEFINE_PROP_END_OF_LIST(),
 362 };
 363
 364 static void arm_gic_common_class_init(ObjectClass *klass, void *data)
 365 {
 366     DeviceClass *dc = DEVICE_CLASS(klass);
 367     ResettableClass *rc = RESETTABLE_CLASS(klass);
 368     ARMLinuxBootIfClass *albifc = ARM_LINUX_BOOT_IF_CLASS(klass);
 369
 370     rc->phases.hold = arm_gic_common_reset_hold;
 371     dc->realize = arm_gic_common_realize;
 372     device_class_set_props(dc, arm_gic_common_properties);
 373     dc->vmsd = &vmstate_gic;
 374     albifc->arm_linux_init = arm_gic_common_linux_init;
 375 }
 376
 377 static const TypeInfo arm_gic_common_type = {
 378     .name = TYPE_ARM_GIC_COMMON,
 379     .parent = TYPE_SYS_BUS_DEVICE,
 380     .instance_size = sizeof(GICState),
 381     .class_size = sizeof(ARMGICCommonClass),
 382     .class_init = arm_gic_common_class_init,
 383     .abstract = true,
 384     .interfaces = (InterfaceInfo []) {
 385         { TYPE_ARM_LINUX_BOOT_IF },
 386         { },
 387     },
 388 };
 389
 390 static void register_types(void)
 391 {
 392     type_register_static(&arm_gic_common_type);
 393 }
 394
 395 type_init(register_types)