hw/isa/piix3.c

   1 /*
   2  * QEMU PIIX PCI ISA Bridge Emulation
   3  *
   4  * Copyright (c) 2006 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #include "qemu/osdep.h"
  26 #include "qemu/range.h"
  27 #include "qapi/error.h"
  28 #include "hw/dma/i8257.h"
  29 #include "hw/southbridge/piix.h"
  30 #include "hw/irq.h"
  31 #include "hw/isa/isa.h"
  32 #include "hw/xen/xen.h"
  33 #include "sysemu/runstate.h"
  34 #include "migration/vmstate.h"
  35 #include "hw/acpi/acpi_aml_interface.h"
  36
  37 #define XEN_PIIX_NUM_PIRQS      128ULL
  38
  39 static void piix3_set_irq_pic(PIIX3State *piix3, int pic_irq)
  40 {
  41     qemu_set_irq(piix3->pic[pic_irq],
  42                  !!(piix3->pic_levels &
  43                     (((1ULL << PIIX_NUM_PIRQS) - 1) <<
  44                      (pic_irq * PIIX_NUM_PIRQS))));
  45 }
  46
  47 static void piix3_set_irq_level_internal(PIIX3State *piix3, int pirq, int level)
  48 {
  49     int pic_irq;
  50     uint64_t mask;
  51
  52     pic_irq = piix3->dev.config[PIIX_PIRQCA + pirq];
  53     if (pic_irq >= PIIX_NUM_PIC_IRQS) {
  54         return;
  55     }
  56
  57     mask = 1ULL << ((pic_irq * PIIX_NUM_PIRQS) + pirq);
  58     piix3->pic_levels &= ~mask;
  59     piix3->pic_levels |= mask * !!level;
  60 }
  61
  62 static void piix3_set_irq_level(PIIX3State *piix3, int pirq, int level)
  63 {
  64     int pic_irq;
  65
  66     pic_irq = piix3->dev.config[PIIX_PIRQCA + pirq];
  67     if (pic_irq >= PIIX_NUM_PIC_IRQS) {
  68         return;
  69     }
  70
  71     piix3_set_irq_level_internal(piix3, pirq, level);
  72
  73     piix3_set_irq_pic(piix3, pic_irq);
  74 }
  75
  76 static void piix3_set_irq(void *opaque, int pirq, int level)
  77 {
  78     PIIX3State *piix3 = opaque;
  79     piix3_set_irq_level(piix3, pirq, level);
  80 }
  81
  82 static PCIINTxRoute piix3_route_intx_pin_to_irq(void *opaque, int pin)
  83 {
  84     PIIX3State *piix3 = opaque;
  85     int irq = piix3->dev.config[PIIX_PIRQCA + pin];
  86     PCIINTxRoute route;
  87
  88     if (irq < PIIX_NUM_PIC_IRQS) {
  89         route.mode = PCI_INTX_ENABLED;
  90         route.irq = irq;
  91     } else {
  92         route.mode = PCI_INTX_DISABLED;
  93         route.irq = -1;
  94     }
  95     return route;
  96 }
  97
  98 /* irq routing is changed. so rebuild bitmap */
  99 static void piix3_update_irq_levels(PIIX3State *piix3)
 100 {
 101     PCIBus *bus = pci_get_bus(&piix3->dev);
 102     int pirq;
 103
 104     piix3->pic_levels = 0;
 105     for (pirq = 0; pirq < PIIX_NUM_PIRQS; pirq++) {
 106         piix3_set_irq_level(piix3, pirq, pci_bus_get_irq_level(bus, pirq));
 107     }
 108 }
 109
 110 static void piix3_write_config(PCIDevice *dev,
 111                                uint32_t address, uint32_t val, int len)
 112 {
 113     pci_default_write_config(dev, address, val, len);
 114     if (ranges_overlap(address, len, PIIX_PIRQCA, 4)) {
 115         PIIX3State *piix3 = PIIX3_PCI_DEVICE(dev);
 116         int pic_irq;
 117
 118         pci_bus_fire_intx_routing_notifier(pci_get_bus(&piix3->dev));
 119         piix3_update_irq_levels(piix3);
 120         for (pic_irq = 0; pic_irq < PIIX_NUM_PIC_IRQS; pic_irq++) {
 121             piix3_set_irq_pic(piix3, pic_irq);
 122         }
 123     }
 124 }
 125
 126 static void piix3_write_config_xen(PCIDevice *dev,
 127                                    uint32_t address, uint32_t val, int len)
 128 {
 129     int i;
 130
 131     /* Scan for updates to PCI link routes (0x60-0x63). */
 132     for (i = 0; i < len; i++) {
 133         uint8_t v = (val >> (8 * i)) & 0xff;
 134         if (v & 0x80) {
 135             v = 0;
 136         }
 137         v &= 0xf;
 138         if (((address + i) >= PIIX_PIRQCA) && ((address + i) <= PIIX_PIRQCD)) {
 139             xen_set_pci_link_route(address + i - PIIX_PIRQCA, v);
 140         }
 141     }
 142
 143     piix3_write_config(dev, address, val, len);
 144 }
 145
 146 static void piix3_reset(DeviceState *dev)
 147 {
 148     PIIX3State *d = PIIX3_PCI_DEVICE(dev);
 149     uint8_t *pci_conf = d->dev.config;
 150
 151     pci_conf[0x04] = 0x07; /* master, memory and I/O */
 152     pci_conf[0x05] = 0x00;
 153     pci_conf[0x06] = 0x00;
 154     pci_conf[0x07] = 0x02; /* PCI_status_devsel_medium */
 155     pci_conf[0x4c] = 0x4d;
 156     pci_conf[0x4e] = 0x03;
 157     pci_conf[0x4f] = 0x00;
 158     pci_conf[0x60] = 0x80;
 159     pci_conf[0x61] = 0x80;
 160     pci_conf[0x62] = 0x80;
 161     pci_conf[0x63] = 0x80;
 162     pci_conf[0x69] = 0x02;
 163     pci_conf[0x70] = 0x80;
 164     pci_conf[0x76] = 0x0c;
 165     pci_conf[0x77] = 0x0c;
 166     pci_conf[0x78] = 0x02;
 167     pci_conf[0x79] = 0x00;
 168     pci_conf[0x80] = 0x00;
 169     pci_conf[0x82] = 0x00;
 170     pci_conf[0xa0] = 0x08;
 171     pci_conf[0xa2] = 0x00;
 172     pci_conf[0xa3] = 0x00;
 173     pci_conf[0xa4] = 0x00;
 174     pci_conf[0xa5] = 0x00;
 175     pci_conf[0xa6] = 0x00;
 176     pci_conf[0xa7] = 0x00;
 177     pci_conf[0xa8] = 0x0f;
 178     pci_conf[0xaa] = 0x00;
 179     pci_conf[0xab] = 0x00;
 180     pci_conf[0xac] = 0x00;
 181     pci_conf[0xae] = 0x00;
 182
 183     d->pic_levels = 0;
 184     d->rcr = 0;
 185 }
 186
 187 static int piix3_post_load(void *opaque, int version_id)
 188 {
 189     PIIX3State *piix3 = opaque;
 190     int pirq;
 191
 192     /*
 193      * Because the i8259 has not been deserialized yet, qemu_irq_raise
 194      * might bring the system to a different state than the saved one;
 195      * for example, the interrupt could be masked but the i8259 would
 196      * not know that yet and would trigger an interrupt in the CPU.
 197      *
 198      * Here, we update irq levels without raising the interrupt.
 199      * Interrupt state will be deserialized separately through the i8259.
 200      */
 201     piix3->pic_levels = 0;
 202     for (pirq = 0; pirq < PIIX_NUM_PIRQS; pirq++) {
 203         piix3_set_irq_level_internal(piix3, pirq,
 204             pci_bus_get_irq_level(pci_get_bus(&piix3->dev), pirq));
 205     }
 206     return 0;
 207 }
 208
 209 static int piix3_pre_save(void *opaque)
 210 {
 211     int i;
 212     PIIX3State *piix3 = opaque;
 213
 214     for (i = 0; i < ARRAY_SIZE(piix3->pci_irq_levels_vmstate); i++) {
 215         piix3->pci_irq_levels_vmstate[i] =
 216             pci_bus_get_irq_level(pci_get_bus(&piix3->dev), i);
 217     }
 218
 219     return 0;
 220 }
 221
 222 static bool piix3_rcr_needed(void *opaque)
 223 {
 224     PIIX3State *piix3 = opaque;
 225
 226     return (piix3->rcr != 0);
 227 }
 228
 229 static const VMStateDescription vmstate_piix3_rcr = {
 230     .name = "PIIX3/rcr",
 231     .version_id = 1,
 232     .minimum_version_id = 1,
 233     .needed = piix3_rcr_needed,
 234     .fields = (VMStateField[]) {
 235         VMSTATE_UINT8(rcr, PIIX3State),
 236         VMSTATE_END_OF_LIST()
 237     }
 238 };
 239
 240 static const VMStateDescription vmstate_piix3 = {
 241     .name = "PIIX3",
 242     .version_id = 3,
 243     .minimum_version_id = 2,
 244     .post_load = piix3_post_load,
 245     .pre_save = piix3_pre_save,
 246     .fields = (VMStateField[]) {
 247         VMSTATE_PCI_DEVICE(dev, PIIX3State),
 248         VMSTATE_INT32_ARRAY_V(pci_irq_levels_vmstate, PIIX3State,
 249                               PIIX_NUM_PIRQS, 3),
 250         VMSTATE_END_OF_LIST()
 251     },
 252     .subsections = (const VMStateDescription*[]) {
 253         &vmstate_piix3_rcr,
 254         NULL
 255     }
 256 };
 257
 258
 259 static void rcr_write(void *opaque, hwaddr addr, uint64_t val, unsigned len)
 260 {
 261     PIIX3State *d = opaque;
 262
 263     if (val & 4) {
 264         qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
 265         return;
 266     }
 267     d->rcr = val & 2; /* keep System Reset type only */
 268 }
 269
 270 static uint64_t rcr_read(void *opaque, hwaddr addr, unsigned len)
 271 {
 272     PIIX3State *d = opaque;
 273
 274     return d->rcr;
 275 }
 276
 277 static const MemoryRegionOps rcr_ops = {
 278     .read = rcr_read,
 279     .write = rcr_write,
 280     .endianness = DEVICE_LITTLE_ENDIAN,
 281     .impl = {
 282         .min_access_size = 1,
 283         .max_access_size = 1,
 284     },
 285 };
 286
 287 static void pci_piix3_realize(PCIDevice *dev, Error **errp)
 288 {
 289     PIIX3State *d = PIIX3_PCI_DEVICE(dev);
 290     ISABus *isa_bus;
 291
 292     isa_bus = isa_bus_new(DEVICE(d), pci_address_space(dev),
 293                           pci_address_space_io(dev), errp);
 294     if (!isa_bus) {
 295         return;
 296     }
 297
 298     memory_region_init_io(&d->rcr_mem, OBJECT(dev), &rcr_ops, d,
 299                           "piix3-reset-control", 1);
 300     memory_region_add_subregion_overlap(pci_address_space_io(dev),
 301                                         PIIX_RCR_IOPORT, &d->rcr_mem, 1);
 302
 303     i8257_dma_init(isa_bus, 0);
 304 }
 305
 306 static void build_pci_isa_aml(AcpiDevAmlIf *adev, Aml *scope)
 307 {
 308     Aml *field;
 309     Aml *sb_scope = aml_scope("\\_SB");
 310     BusState *bus = qdev_get_child_bus(DEVICE(adev), "isa.0");
 311
 312     /* PIIX PCI to ISA irq remapping */
 313     aml_append(scope, aml_operation_region("P40C", AML_PCI_CONFIG,
 314                                            aml_int(0x60), 0x04));
 315     /* Fields declarion has to happen *after* operation region */
 316     field = aml_field("PCI0.S08.P40C", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE);
 317     aml_append(field, aml_named_field("PRQ0", 8));
 318     aml_append(field, aml_named_field("PRQ1", 8));
 319     aml_append(field, aml_named_field("PRQ2", 8));
 320     aml_append(field, aml_named_field("PRQ3", 8));
 321     aml_append(sb_scope, field);
 322     aml_append(scope, sb_scope);
 323
 324     qbus_build_aml(bus, scope);
 325 }
 326
 327 static void pci_piix3_class_init(ObjectClass *klass, void *data)
 328 {
 329     DeviceClass *dc = DEVICE_CLASS(klass);
 330     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 331     AcpiDevAmlIfClass *adevc = ACPI_DEV_AML_IF_CLASS(klass);
 332
 333     dc->reset       = piix3_reset;
 334     dc->desc        = "ISA bridge";
 335     dc->vmsd        = &vmstate_piix3;
 336     dc->hotpluggable   = false;
 337     k->vendor_id    = PCI_VENDOR_ID_INTEL;
 338     /* 82371SB PIIX3 PCI-to-ISA bridge (Step A1) */
 339     k->device_id    = PCI_DEVICE_ID_INTEL_82371SB_0;
 340     k->class_id     = PCI_CLASS_BRIDGE_ISA;
 341     /*
 342      * Reason: part of PIIX3 southbridge, needs to be wired up by
 343      * pc_piix.c's pc_init1()
 344      */
 345     dc->user_creatable = false;
 346     adevc->build_dev_aml = build_pci_isa_aml;
 347 }
 348
 349 static const TypeInfo piix3_pci_type_info = {
 350     .name = TYPE_PIIX3_PCI_DEVICE,
 351     .parent = TYPE_PCI_DEVICE,
 352     .instance_size = sizeof(PIIX3State),
 353     .abstract = true,
 354     .class_init = pci_piix3_class_init,
 355     .interfaces = (InterfaceInfo[]) {
 356         { INTERFACE_CONVENTIONAL_PCI_DEVICE },
 357         { TYPE_ACPI_DEV_AML_IF },
 358         { },
 359     },
 360 };
 361
 362 static void piix3_realize(PCIDevice *dev, Error **errp)
 363 {
 364     ERRP_GUARD();
 365     PIIX3State *piix3 = PIIX3_PCI_DEVICE(dev);
 366     PCIBus *pci_bus = pci_get_bus(dev);
 367
 368     pci_piix3_realize(dev, errp);
 369     if (*errp) {
 370         return;
 371     }
 372
 373     pci_bus_irqs(pci_bus, piix3_set_irq, piix3, PIIX_NUM_PIRQS);
 374     pci_bus_set_route_irq_fn(pci_bus, piix3_route_intx_pin_to_irq);
 375 }
 376
 377 static void piix3_class_init(ObjectClass *klass, void *data)
 378 {
 379     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 380
 381     k->config_write = piix3_write_config;
 382     k->realize = piix3_realize;
 383 }
 384
 385 static const TypeInfo piix3_info = {
 386     .name          = TYPE_PIIX3_DEVICE,
 387     .parent        = TYPE_PIIX3_PCI_DEVICE,
 388     .class_init    = piix3_class_init,
 389 };
 390
 391 static void piix3_xen_realize(PCIDevice *dev, Error **errp)
 392 {
 393     ERRP_GUARD();
 394     PIIX3State *piix3 = PIIX3_PCI_DEVICE(dev);
 395     PCIBus *pci_bus = pci_get_bus(dev);
 396
 397     pci_piix3_realize(dev, errp);
 398     if (*errp) {
 399         return;
 400     }
 401
 402     /*
 403      * Xen supports additional interrupt routes from the PCI devices to
 404      * the IOAPIC: the four pins of each PCI device on the bus are also
 405      * connected to the IOAPIC directly.
 406      * These additional routes can be discovered through ACPI.
 407      */
 408     pci_bus_irqs(pci_bus, xen_piix3_set_irq, piix3, XEN_PIIX_NUM_PIRQS);
 409 }
 410
 411 static void piix3_xen_class_init(ObjectClass *klass, void *data)
 412 {
 413     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 414
 415     k->config_write = piix3_write_config_xen;
 416     k->realize = piix3_xen_realize;
 417 }
 418
 419 static const TypeInfo piix3_xen_info = {
 420     .name          = TYPE_PIIX3_XEN_DEVICE,
 421     .parent        = TYPE_PIIX3_PCI_DEVICE,
 422     .class_init    = piix3_xen_class_init,
 423 };
 424
 425 static void piix3_register_types(void)
 426 {
 427     type_register_static(&piix3_pci_type_info);
 428     type_register_static(&piix3_info);
 429     type_register_static(&piix3_xen_info);
 430 }
 431
 432 type_init(piix3_register_types)