hw/isa/piix4.c

   1 /*
   2  * QEMU PIIX4 PCI Bridge Emulation
   3  *
   4  * Copyright (c) 2006 Fabrice Bellard
   5  * Copyright (c) 2018 Hervé Poussineau
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a copy
   8  * of this software and associated documentation files (the "Software"), to deal
   9  * in the Software without restriction, including without limitation the rights
  10  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  11  * copies of the Software, and to permit persons to whom the Software is
  12  * furnished to do so, subject to the following conditions:
  13  *
  14  * The above copyright notice and this permission notice shall be included in
  15  * all copies or substantial portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  23  * THE SOFTWARE.
  24  */
  25
  26 #include "qemu/osdep.h"
  27 #include "qapi/error.h"
  28 #include "hw/irq.h"
  29 #include "hw/southbridge/piix.h"
  30 #include "hw/pci/pci.h"
  31 #include "hw/ide/piix.h"
  32 #include "hw/isa/isa.h"
  33 #include "hw/intc/i8259.h"
  34 #include "hw/dma/i8257.h"
  35 #include "hw/timer/i8254.h"
  36 #include "hw/rtc/mc146818rtc.h"
  37 #include "hw/ide/pci.h"
  38 #include "hw/acpi/piix4.h"
  39 #include "hw/usb/hcd-uhci.h"
  40 #include "migration/vmstate.h"
  41 #include "sysemu/reset.h"
  42 #include "sysemu/runstate.h"
  43 #include "qom/object.h"
  44
  45 struct PIIX4State {
  46     PCIDevice dev;
  47     qemu_irq cpu_intr;
  48     qemu_irq *isa;
  49
  50     MC146818RtcState rtc;
  51     PCIIDEState ide;
  52     UHCIState uhci;
  53     PIIX4PMState pm;
  54     /* Reset Control Register */
  55     MemoryRegion rcr_mem;
  56     uint8_t rcr;
  57 };
  58
  59 OBJECT_DECLARE_SIMPLE_TYPE(PIIX4State, PIIX4_PCI_DEVICE)
  60
  61 static void piix4_set_irq(void *opaque, int irq_num, int level)
  62 {
  63     int i, pic_irq, pic_level;
  64     PIIX4State *s = opaque;
  65     PCIBus *bus = pci_get_bus(&s->dev);
  66
  67     /* now we change the pic irq level according to the piix irq mappings */
  68     /* XXX: optimize */
  69     pic_irq = s->dev.config[PIIX_PIRQCA + irq_num];
  70     if (pic_irq < ISA_NUM_IRQS) {
  71         /* The pic level is the logical OR of all the PCI irqs mapped to it. */
  72         pic_level = 0;
  73         for (i = 0; i < PIIX_NUM_PIRQS; i++) {
  74             if (pic_irq == s->dev.config[PIIX_PIRQCA + i]) {
  75                 pic_level |= pci_bus_get_irq_level(bus, i);
  76             }
  77         }
  78         qemu_set_irq(s->isa[pic_irq], pic_level);
  79     }
  80 }
  81
  82 static void piix4_isa_reset(DeviceState *dev)
  83 {
  84     PIIX4State *d = PIIX4_PCI_DEVICE(dev);
  85     uint8_t *pci_conf = d->dev.config;
  86
  87     pci_conf[0x04] = 0x07; // master, memory and I/O
  88     pci_conf[0x05] = 0x00;
  89     pci_conf[0x06] = 0x00;
  90     pci_conf[0x07] = 0x02; // PCI_status_devsel_medium
  91     pci_conf[0x4c] = 0x4d;
  92     pci_conf[0x4e] = 0x03;
  93     pci_conf[0x4f] = 0x00;
  94     pci_conf[0x60] = 0x80;
  95     pci_conf[0x61] = 0x80;
  96     pci_conf[0x62] = 0x80;
  97     pci_conf[0x63] = 0x80;
  98     pci_conf[0x69] = 0x02;
  99     pci_conf[0x70] = 0x80;
 100     pci_conf[0x76] = 0x0c;
 101     pci_conf[0x77] = 0x0c;
 102     pci_conf[0x78] = 0x02;
 103     pci_conf[0x79] = 0x00;
 104     pci_conf[0x80] = 0x00;
 105     pci_conf[0x82] = 0x00;
 106     pci_conf[0xa0] = 0x08;
 107     pci_conf[0xa2] = 0x00;
 108     pci_conf[0xa3] = 0x00;
 109     pci_conf[0xa4] = 0x00;
 110     pci_conf[0xa5] = 0x00;
 111     pci_conf[0xa6] = 0x00;
 112     pci_conf[0xa7] = 0x00;
 113     pci_conf[0xa8] = 0x0f;
 114     pci_conf[0xaa] = 0x00;
 115     pci_conf[0xab] = 0x00;
 116     pci_conf[0xac] = 0x00;
 117     pci_conf[0xae] = 0x00;
 118
 119     d->rcr = 0;
 120 }
 121
 122 static int piix4_post_load(void *opaque, int version_id)
 123 {
 124     PIIX4State *s = opaque;
 125
 126     if (version_id == 2) {
 127         s->rcr = 0;
 128     }
 129
 130     return 0;
 131 }
 132
 133 static const VMStateDescription vmstate_piix4 = {
 134     .name = "PIIX4",
 135     .version_id = 3,
 136     .minimum_version_id = 2,
 137     .post_load = piix4_post_load,
 138     .fields = (VMStateField[]) {
 139         VMSTATE_PCI_DEVICE(dev, PIIX4State),
 140         VMSTATE_UINT8_V(rcr, PIIX4State, 3),
 141         VMSTATE_END_OF_LIST()
 142     }
 143 };
 144
 145 static void piix4_request_i8259_irq(void *opaque, int irq, int level)
 146 {
 147     PIIX4State *s = opaque;
 148     qemu_set_irq(s->cpu_intr, level);
 149 }
 150
 151 static void piix4_set_i8259_irq(void *opaque, int irq, int level)
 152 {
 153     PIIX4State *s = opaque;
 154     qemu_set_irq(s->isa[irq], level);
 155 }
 156
 157 static void piix4_rcr_write(void *opaque, hwaddr addr, uint64_t val,
 158                             unsigned int len)
 159 {
 160     PIIX4State *s = opaque;
 161
 162     if (val & 4) {
 163         qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
 164         return;
 165     }
 166
 167     s->rcr = val & 2; /* keep System Reset type only */
 168 }
 169
 170 static uint64_t piix4_rcr_read(void *opaque, hwaddr addr, unsigned int len)
 171 {
 172     PIIX4State *s = opaque;
 173
 174     return s->rcr;
 175 }
 176
 177 static const MemoryRegionOps piix4_rcr_ops = {
 178     .read = piix4_rcr_read,
 179     .write = piix4_rcr_write,
 180     .endianness = DEVICE_LITTLE_ENDIAN,
 181     .impl = {
 182         .min_access_size = 1,
 183         .max_access_size = 1,
 184     },
 185 };
 186
 187 static void piix4_realize(PCIDevice *dev, Error **errp)
 188 {
 189     PIIX4State *s = PIIX4_PCI_DEVICE(dev);
 190     PCIBus *pci_bus = pci_get_bus(dev);
 191     ISABus *isa_bus;
 192     qemu_irq *i8259_out_irq;
 193
 194     isa_bus = isa_bus_new(DEVICE(dev), pci_address_space(dev),
 195                           pci_address_space_io(dev), errp);
 196     if (!isa_bus) {
 197         return;
 198     }
 199
 200     qdev_init_gpio_in_named(DEVICE(dev), piix4_set_i8259_irq,
 201                             "isa", ISA_NUM_IRQS);
 202     qdev_init_gpio_out_named(DEVICE(dev), &s->cpu_intr,
 203                              "intr", 1);
 204
 205     memory_region_init_io(&s->rcr_mem, OBJECT(dev), &piix4_rcr_ops, s,
 206                           "reset-control", 1);
 207     memory_region_add_subregion_overlap(pci_address_space_io(dev),
 208                                         PIIX_RCR_IOPORT, &s->rcr_mem, 1);
 209
 210     /* initialize i8259 pic */
 211     i8259_out_irq = qemu_allocate_irqs(piix4_request_i8259_irq, s, 1);
 212     s->isa = i8259_init(isa_bus, *i8259_out_irq);
 213
 214     /* initialize ISA irqs */
 215     isa_bus_register_input_irqs(isa_bus, s->isa);
 216
 217     /* initialize pit */
 218     i8254_pit_init(isa_bus, 0x40, 0, NULL);
 219
 220     /* DMA */
 221     i8257_dma_init(isa_bus, 0);
 222
 223     /* RTC */
 224     qdev_prop_set_int32(DEVICE(&s->rtc), "base_year", 2000);
 225     if (!qdev_realize(DEVICE(&s->rtc), BUS(isa_bus), errp)) {
 226         return;
 227     }
 228     s->rtc.irq = isa_get_irq(ISA_DEVICE(&s->rtc), s->rtc.isairq);
 229
 230     /* IDE */
 231     qdev_prop_set_int32(DEVICE(&s->ide), "addr", dev->devfn + 1);
 232     if (!qdev_realize(DEVICE(&s->ide), BUS(pci_bus), errp)) {
 233         return;
 234     }
 235
 236     /* USB */
 237     qdev_prop_set_int32(DEVICE(&s->uhci), "addr", dev->devfn + 2);
 238     if (!qdev_realize(DEVICE(&s->uhci), BUS(pci_bus), errp)) {
 239         return;
 240     }
 241
 242     /* ACPI controller */
 243     qdev_prop_set_int32(DEVICE(&s->pm), "addr", dev->devfn + 3);
 244     if (!qdev_realize(DEVICE(&s->pm), BUS(pci_bus), errp)) {
 245         return;
 246     }
 247     qdev_connect_gpio_out(DEVICE(&s->pm), 0, s->isa[9]);
 248
 249     pci_bus_irqs(pci_bus, piix4_set_irq, s, PIIX_NUM_PIRQS);
 250 }
 251
 252 static void piix4_init(Object *obj)
 253 {
 254     PIIX4State *s = PIIX4_PCI_DEVICE(obj);
 255
 256     object_initialize_child(obj, "rtc", &s->rtc, TYPE_MC146818_RTC);
 257     object_initialize_child(obj, "ide", &s->ide, TYPE_PIIX4_IDE);
 258     object_initialize_child(obj, "uhci", &s->uhci, TYPE_PIIX4_USB_UHCI);
 259
 260     object_initialize_child(obj, "pm", &s->pm, TYPE_PIIX4_PM);
 261     qdev_prop_set_uint32(DEVICE(&s->pm), "smb_io_base", 0x1100);
 262     qdev_prop_set_bit(DEVICE(&s->pm), "smm-enabled", 0);
 263 }
 264
 265 static void piix4_class_init(ObjectClass *klass, void *data)
 266 {
 267     DeviceClass *dc = DEVICE_CLASS(klass);
 268     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 269
 270     k->realize = piix4_realize;
 271     k->vendor_id = PCI_VENDOR_ID_INTEL;
 272     k->device_id = PCI_DEVICE_ID_INTEL_82371AB_0;
 273     k->class_id = PCI_CLASS_BRIDGE_ISA;
 274     dc->reset = piix4_isa_reset;
 275     dc->desc = "ISA bridge";
 276     dc->vmsd = &vmstate_piix4;
 277     /*
 278      * Reason: part of PIIX4 southbridge, needs to be wired up,
 279      * e.g. by mips_malta_init()
 280      */
 281     dc->user_creatable = false;
 282     dc->hotpluggable = false;
 283 }
 284
 285 static const TypeInfo piix4_info = {
 286     .name          = TYPE_PIIX4_PCI_DEVICE,
 287     .parent        = TYPE_PCI_DEVICE,
 288     .instance_size = sizeof(PIIX4State),
 289     .instance_init = piix4_init,
 290     .class_init    = piix4_class_init,
 291     .interfaces = (InterfaceInfo[]) {
 292         { INTERFACE_CONVENTIONAL_PCI_DEVICE },
 293         { },
 294     },
 295 };
 296
 297 static void piix4_register_types(void)
 298 {
 299     type_register_static(&piix4_info);
 300 }
 301
 302 type_init(piix4_register_types)