hw/mips/jazz.c

   1 /*
   2  * QEMU MIPS Jazz support
   3  *
   4  * Copyright (c) 2007-2008 Hervé Poussineau
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #include "qemu/osdep.h"
  26 #include "qemu/datadir.h"
  27 #include "hw/clock.h"
  28 #include "hw/mips/mips.h"
  29 #include "hw/mips/cpudevs.h"
  30 #include "hw/intc/i8259.h"
  31 #include "hw/dma/i8257.h"
  32 #include "hw/char/serial.h"
  33 #include "hw/char/parallel.h"
  34 #include "hw/isa/isa.h"
  35 #include "hw/block/fdc.h"
  36 #include "sysemu/sysemu.h"
  37 #include "hw/boards.h"
  38 #include "net/net.h"
  39 #include "hw/scsi/esp.h"
  40 #include "hw/mips/bios.h"
  41 #include "hw/loader.h"
  42 #include "hw/rtc/mc146818rtc.h"
  43 #include "hw/timer/i8254.h"
  44 #include "hw/display/vga.h"
  45 #include "hw/display/bochs-vbe.h"
  46 #include "hw/audio/pcspk.h"
  47 #include "hw/input/i8042.h"
  48 #include "hw/sysbus.h"
  49 #include "sysemu/qtest.h"
  50 #include "sysemu/reset.h"
  51 #include "qapi/error.h"
  52 #include "qemu/error-report.h"
  53 #include "qemu/help_option.h"
  54 #ifdef CONFIG_TCG
  55 #include "hw/core/tcg-cpu-ops.h"
  56 #endif /* CONFIG_TCG */
  57
  58 enum jazz_model_e {
  59     JAZZ_MAGNUM,
  60     JAZZ_PICA61,
  61 };
  62
  63 static void main_cpu_reset(void *opaque)
  64 {
  65     MIPSCPU *cpu = opaque;
  66
  67     cpu_reset(CPU(cpu));
  68 }
  69
  70 static uint64_t rtc_read(void *opaque, hwaddr addr, unsigned size)
  71 {
  72     uint8_t val;
  73     address_space_read(&address_space_memory, 0x90000071,
  74                        MEMTXATTRS_UNSPECIFIED, &val, 1);
  75     return val;
  76 }
  77
  78 static void rtc_write(void *opaque, hwaddr addr,
  79                       uint64_t val, unsigned size)
  80 {
  81     uint8_t buf = val & 0xff;
  82     address_space_write(&address_space_memory, 0x90000071,
  83                         MEMTXATTRS_UNSPECIFIED, &buf, 1);
  84 }
  85
  86 static const MemoryRegionOps rtc_ops = {
  87     .read = rtc_read,
  88     .write = rtc_write,
  89     .endianness = DEVICE_NATIVE_ENDIAN,
  90 };
  91
  92 static uint64_t dma_dummy_read(void *opaque, hwaddr addr,
  93                                unsigned size)
  94 {
  95     /*
  96      * Nothing to do. That is only to ensure that
  97      * the current DMA acknowledge cycle is completed.
  98      */
  99     return 0xff;
 100 }
 101
 102 static void dma_dummy_write(void *opaque, hwaddr addr,
 103                             uint64_t val, unsigned size)
 104 {
 105     /*
 106      * Nothing to do. That is only to ensure that
 107      * the current DMA acknowledge cycle is completed.
 108      */
 109 }
 110
 111 static const MemoryRegionOps dma_dummy_ops = {
 112     .read = dma_dummy_read,
 113     .write = dma_dummy_write,
 114     .endianness = DEVICE_NATIVE_ENDIAN,
 115 };
 116
 117 #define MAGNUM_BIOS_SIZE_MAX 0x7e000
 118 #define MAGNUM_BIOS_SIZE                                                       \
 119         (BIOS_SIZE < MAGNUM_BIOS_SIZE_MAX ? BIOS_SIZE : MAGNUM_BIOS_SIZE_MAX)
 120
 121 #define SONIC_PROM_SIZE 0x1000
 122
 123 static void mips_jazz_init(MachineState *machine,
 124                            enum jazz_model_e jazz_model)
 125 {
 126     MemoryRegion *address_space = get_system_memory();
 127     char *filename;
 128     int bios_size, n, big_endian;
 129     Clock *cpuclk;
 130     MIPSCPU *cpu;
 131     MIPSCPUClass *mcc;
 132     CPUMIPSState *env;
 133     qemu_irq *i8259;
 134     rc4030_dma *dmas;
 135     IOMMUMemoryRegion *rc4030_dma_mr;
 136     MemoryRegion *isa_mem = g_new(MemoryRegion, 1);
 137     MemoryRegion *isa_io = g_new(MemoryRegion, 1);
 138     MemoryRegion *rtc = g_new(MemoryRegion, 1);
 139     MemoryRegion *dma_dummy = g_new(MemoryRegion, 1);
 140     MemoryRegion *dp8393x_prom = g_new(MemoryRegion, 1);
 141     NICInfo *nd;
 142     DeviceState *dev, *rc4030;
 143     MMIOKBDState *i8042;
 144     SysBusDevice *sysbus;
 145     ISABus *isa_bus;
 146     ISADevice *pit;
 147     DriveInfo *fds[MAX_FD];
 148     MemoryRegion *bios = g_new(MemoryRegion, 1);
 149     MemoryRegion *bios2 = g_new(MemoryRegion, 1);
 150     SysBusESPState *sysbus_esp;
 151     ESPState *esp;
 152     static const struct {
 153         unsigned freq_hz;
 154         unsigned pll_mult;
 155     } ext_clk[] = {
 156         [JAZZ_MAGNUM] = {50000000, 2},
 157         [JAZZ_PICA61] = {33333333, 4},
 158     };
 159
 160 #if TARGET_BIG_ENDIAN
 161     big_endian = 1;
 162 #else
 163     big_endian = 0;
 164 #endif
 165
 166     if (machine->ram_size > 256 * MiB) {
 167         error_report("RAM size more than 256Mb is not supported");
 168         exit(EXIT_FAILURE);
 169     }
 170
 171     cpuclk = clock_new(OBJECT(machine), "cpu-refclk");
 172     clock_set_hz(cpuclk, ext_clk[jazz_model].freq_hz
 173                          * ext_clk[jazz_model].pll_mult);
 174
 175     /* init CPUs */
 176     cpu = mips_cpu_create_with_clock(machine->cpu_type, cpuclk);
 177     env = &cpu->env;
 178     qemu_register_reset(main_cpu_reset, cpu);
 179
 180     /*
 181      * Chipset returns 0 in invalid reads and do not raise data exceptions.
 182      * However, we can't simply add a global memory region to catch
 183      * everything, as this would make all accesses including instruction
 184      * accesses be ignored and not raise exceptions.
 185      *
 186      * NOTE: this behaviour of raising exceptions for bad instruction
 187      * fetches but not bad data accesses was added in commit 54e755588cf1e9
 188      * to restore behaviour broken by c658b94f6e8c206, but it is not clear
 189      * whether the real hardware behaves this way. It is possible that
 190      * real hardware ignores bad instruction fetches as well -- if so then
 191      * we could replace this hijacking of CPU methods with a simple global
 192      * memory region that catches all memory accesses, as we do on Malta.
 193      */
 194     mcc = MIPS_CPU_GET_CLASS(cpu);
 195     mcc->no_data_aborts = true;
 196
 197     /* allocate RAM */
 198     memory_region_add_subregion(address_space, 0, machine->ram);
 199
 200     memory_region_init_rom(bios, NULL, "mips_jazz.bios", MAGNUM_BIOS_SIZE,
 201                            &error_fatal);
 202     memory_region_init_alias(bios2, NULL, "mips_jazz.bios", bios,
 203                              0, MAGNUM_BIOS_SIZE);
 204     memory_region_add_subregion(address_space, 0x1fc00000LL, bios);
 205     memory_region_add_subregion(address_space, 0xfff00000LL, bios2);
 206
 207     /* load the BIOS image. */
 208     filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, machine->firmware ?: BIOS_FILENAME);
 209     if (filename) {
 210         bios_size = load_image_targphys(filename, 0xfff00000LL,
 211                                         MAGNUM_BIOS_SIZE);
 212         g_free(filename);
 213     } else {
 214         bios_size = -1;
 215     }
 216     if ((bios_size < 0 || bios_size > MAGNUM_BIOS_SIZE)
 217         && machine->firmware && !qtest_enabled()) {
 218         error_report("Could not load MIPS bios '%s'", machine->firmware);
 219         exit(1);
 220     }
 221
 222     /* Init CPU internal devices */
 223     cpu_mips_irq_init_cpu(cpu);
 224     cpu_mips_clock_init(cpu);
 225
 226     /* Chipset */
 227     rc4030 = rc4030_init(&dmas, &rc4030_dma_mr);
 228     sysbus = SYS_BUS_DEVICE(rc4030);
 229     sysbus_connect_irq(sysbus, 0, env->irq[6]);
 230     sysbus_connect_irq(sysbus, 1, env->irq[3]);
 231     memory_region_add_subregion(address_space, 0x80000000,
 232                                 sysbus_mmio_get_region(sysbus, 0));
 233     memory_region_add_subregion(address_space, 0xf0000000,
 234                                 sysbus_mmio_get_region(sysbus, 1));
 235     memory_region_init_io(dma_dummy, NULL, &dma_dummy_ops,
 236                           NULL, "dummy_dma", 0x1000);
 237     memory_region_add_subregion(address_space, 0x8000d000, dma_dummy);
 238
 239     memory_region_init_rom(dp8393x_prom, NULL, "dp8393x-jazz.prom",
 240                            SONIC_PROM_SIZE, &error_fatal);
 241     memory_region_add_subregion(address_space, 0x8000b000, dp8393x_prom);
 242
 243     /* ISA bus: IO space at 0x90000000, mem space at 0x91000000 */
 244     memory_region_init(isa_io, NULL, "isa-io", 0x00010000);
 245     memory_region_init(isa_mem, NULL, "isa-mem", 0x01000000);
 246     memory_region_add_subregion(address_space, 0x90000000, isa_io);
 247     memory_region_add_subregion(address_space, 0x91000000, isa_mem);
 248     isa_bus = isa_bus_new(NULL, isa_mem, isa_io, &error_abort);
 249
 250     /* ISA devices */
 251     i8259 = i8259_init(isa_bus, env->irq[4]);
 252     isa_bus_register_input_irqs(isa_bus, i8259);
 253     i8257_dma_init(isa_bus, 0);
 254     pit = i8254_pit_init(isa_bus, 0x40, 0, NULL);
 255     pcspk_init(isa_new(TYPE_PC_SPEAKER), isa_bus, pit);
 256
 257     /* Video card */
 258     switch (jazz_model) {
 259     case JAZZ_MAGNUM:
 260         dev = qdev_new("sysbus-g364");
 261         sysbus = SYS_BUS_DEVICE(dev);
 262         sysbus_realize_and_unref(sysbus, &error_fatal);
 263         sysbus_mmio_map(sysbus, 0, 0x60080000);
 264         sysbus_mmio_map(sysbus, 1, 0x40000000);
 265         sysbus_connect_irq(sysbus, 0, qdev_get_gpio_in(rc4030, 3));
 266         {
 267             /* Simple ROM, so user doesn't have to provide one */
 268             MemoryRegion *rom_mr = g_new(MemoryRegion, 1);
 269             memory_region_init_rom(rom_mr, NULL, "g364fb.rom", 0x80000,
 270                                    &error_fatal);
 271             uint8_t *rom = memory_region_get_ram_ptr(rom_mr);
 272             memory_region_add_subregion(address_space, 0x60000000, rom_mr);
 273             rom[0] = 0x10; /* Mips G364 */
 274         }
 275         break;
 276     case JAZZ_PICA61:
 277         dev = qdev_new(TYPE_VGA_MMIO);
 278         qdev_prop_set_uint8(dev, "it_shift", 0);
 279         sysbus = SYS_BUS_DEVICE(dev);
 280         sysbus_realize_and_unref(sysbus, &error_fatal);
 281         sysbus_mmio_map(sysbus, 0, 0x60000000);
 282         sysbus_mmio_map(sysbus, 1, 0x400a0000);
 283         sysbus_mmio_map(sysbus, 2, VBE_DISPI_LFB_PHYSICAL_ADDRESS);
 284         break;
 285     default:
 286         break;
 287     }
 288
 289     /* Network controller */
 290     for (n = 0; n < nb_nics; n++) {
 291         nd = &nd_table[n];
 292         if (!nd->model) {
 293             nd->model = g_strdup("dp83932");
 294         }
 295         if (strcmp(nd->model, "dp83932") == 0) {
 296             int checksum, i;
 297             uint8_t *prom;
 298
 299             qemu_check_nic_model(nd, "dp83932");
 300
 301             dev = qdev_new("dp8393x");
 302             qdev_set_nic_properties(dev, nd);
 303             qdev_prop_set_uint8(dev, "it_shift", 2);
 304             qdev_prop_set_bit(dev, "big_endian", big_endian > 0);
 305             object_property_set_link(OBJECT(dev), "dma_mr",
 306                                      OBJECT(rc4030_dma_mr), &error_abort);
 307             sysbus = SYS_BUS_DEVICE(dev);
 308             sysbus_realize_and_unref(sysbus, &error_fatal);
 309             sysbus_mmio_map(sysbus, 0, 0x80001000);
 310             sysbus_connect_irq(sysbus, 0, qdev_get_gpio_in(rc4030, 4));
 311
 312             /* Add MAC address with valid checksum to PROM */
 313             prom = memory_region_get_ram_ptr(dp8393x_prom);
 314             checksum = 0;
 315             for (i = 0; i < 6; i++) {
 316                 prom[i] = nd->macaddr.a[i];
 317                 checksum += prom[i];
 318                 if (checksum > 0xff) {
 319                     checksum = (checksum + 1) & 0xff;
 320                 }
 321             }
 322             prom[7] = 0xff - checksum;
 323             break;
 324         } else if (is_help_option(nd->model)) {
 325             error_report("Supported NICs: dp83932");
 326             exit(1);
 327         } else {
 328             error_report("Unsupported NIC: %s", nd->model);
 329             exit(1);
 330         }
 331     }
 332
 333     /* SCSI adapter */
 334     dev = qdev_new(TYPE_SYSBUS_ESP);
 335     sysbus_esp = SYSBUS_ESP(dev);
 336     esp = &sysbus_esp->esp;
 337     esp->dma_memory_read = rc4030_dma_read;
 338     esp->dma_memory_write = rc4030_dma_write;
 339     esp->dma_opaque = dmas[0];
 340     sysbus_esp->it_shift = 0;
 341     /* XXX for now until rc4030 has been changed to use DMA enable signal */
 342     esp->dma_enabled = 1;
 343
 344     sysbus = SYS_BUS_DEVICE(dev);
 345     sysbus_realize_and_unref(sysbus, &error_fatal);
 346     sysbus_connect_irq(sysbus, 0, qdev_get_gpio_in(rc4030, 5));
 347     sysbus_mmio_map(sysbus, 0, 0x80002000);
 348
 349     scsi_bus_legacy_handle_cmdline(&esp->bus);
 350
 351     /* Floppy */
 352     for (n = 0; n < MAX_FD; n++) {
 353         fds[n] = drive_get(IF_FLOPPY, 0, n);
 354     }
 355     /* FIXME: we should enable DMA with a custom IsaDma device */
 356     fdctrl_init_sysbus(qdev_get_gpio_in(rc4030, 1), 0x80003000, fds);
 357
 358     /* Real time clock */
 359     mc146818_rtc_init(isa_bus, 1980, NULL);
 360     memory_region_init_io(rtc, NULL, &rtc_ops, NULL, "rtc", 0x1000);
 361     memory_region_add_subregion(address_space, 0x80004000, rtc);
 362
 363     /* Keyboard (i8042) */
 364     i8042 = I8042_MMIO(qdev_new(TYPE_I8042_MMIO));
 365     qdev_prop_set_uint64(DEVICE(i8042), "mask", 1);
 366     qdev_prop_set_uint32(DEVICE(i8042), "size", 0x1000);
 367     sysbus_realize_and_unref(SYS_BUS_DEVICE(i8042), &error_fatal);
 368
 369     qdev_connect_gpio_out(DEVICE(i8042), I8042_KBD_IRQ,
 370                           qdev_get_gpio_in(rc4030, 6));
 371     qdev_connect_gpio_out(DEVICE(i8042), I8042_MOUSE_IRQ,
 372                           qdev_get_gpio_in(rc4030, 7));
 373
 374     memory_region_add_subregion(address_space, 0x80005000,
 375                                 sysbus_mmio_get_region(SYS_BUS_DEVICE(i8042),
 376                                                        0));
 377
 378     /* Serial ports */
 379     serial_mm_init(address_space, 0x80006000, 0,
 380                    qdev_get_gpio_in(rc4030, 8), 8000000 / 16,
 381                    serial_hd(0), DEVICE_NATIVE_ENDIAN);
 382     serial_mm_init(address_space, 0x80007000, 0,
 383                    qdev_get_gpio_in(rc4030, 9), 8000000 / 16,
 384                    serial_hd(1), DEVICE_NATIVE_ENDIAN);
 385
 386     /* Parallel port */
 387     if (parallel_hds[0])
 388         parallel_mm_init(address_space, 0x80008000, 0,
 389                          qdev_get_gpio_in(rc4030, 0), parallel_hds[0]);
 390
 391     /* FIXME: missing Jazz sound at 0x8000c000, rc4030[2] */
 392
 393     /* NVRAM */
 394     dev = qdev_new("ds1225y");
 395     sysbus = SYS_BUS_DEVICE(dev);
 396     sysbus_realize_and_unref(sysbus, &error_fatal);
 397     sysbus_mmio_map(sysbus, 0, 0x80009000);
 398
 399     /* LED indicator */
 400     sysbus_create_simple("jazz-led", 0x8000f000, NULL);
 401
 402     g_free(dmas);
 403 }
 404
 405 static
 406 void mips_magnum_init(MachineState *machine)
 407 {
 408     mips_jazz_init(machine, JAZZ_MAGNUM);
 409 }
 410
 411 static
 412 void mips_pica61_init(MachineState *machine)
 413 {
 414     mips_jazz_init(machine, JAZZ_PICA61);
 415 }
 416
 417 static void mips_magnum_class_init(ObjectClass *oc, void *data)
 418 {
 419     MachineClass *mc = MACHINE_CLASS(oc);
 420
 421     mc->desc = "MIPS Magnum";
 422     mc->init = mips_magnum_init;
 423     mc->block_default_type = IF_SCSI;
 424     mc->default_cpu_type = MIPS_CPU_TYPE_NAME("R4000");
 425     mc->default_ram_id = "mips_jazz.ram";
 426 }
 427
 428 static const TypeInfo mips_magnum_type = {
 429     .name = MACHINE_TYPE_NAME("magnum"),
 430     .parent = TYPE_MACHINE,
 431     .class_init = mips_magnum_class_init,
 432 };
 433
 434 static void mips_pica61_class_init(ObjectClass *oc, void *data)
 435 {
 436     MachineClass *mc = MACHINE_CLASS(oc);
 437
 438     mc->desc = "Acer Pica 61";
 439     mc->init = mips_pica61_init;
 440     mc->block_default_type = IF_SCSI;
 441     mc->default_cpu_type = MIPS_CPU_TYPE_NAME("R4000");
 442     mc->default_ram_id = "mips_jazz.ram";
 443 }
 444
 445 static const TypeInfo mips_pica61_type = {
 446     .name = MACHINE_TYPE_NAME("pica61"),
 447     .parent = TYPE_MACHINE,
 448     .class_init = mips_pica61_class_init,
 449 };
 450
 451 static void mips_jazz_machine_init(void)
 452 {
 453     type_register_static(&mips_magnum_type);
 454     type_register_static(&mips_pica61_type);
 455 }
 456
 457 type_init(mips_jazz_machine_init)