hw/pci-bridge/pci_expander_bridge.c

   1 /*
   2  * PCI Expander Bridge Device Emulation
   3  *
   4  * Copyright (C) 2015 Red Hat Inc
   5  *
   6  * Authors:
   7  *   Marcel Apfelbaum <marcel@redhat.com>
   8  *
   9  * This work is licensed under the terms of the GNU GPL, version 2 or later.
  10  * See the COPYING file in the top-level directory.
  11  */
  12
  13 #include "qemu/osdep.h"
  14 #include "qapi/error.h"
  15 #include "hw/pci/pci.h"
  16 #include "hw/pci/pci_bus.h"
  17 #include "hw/pci/pci_host.h"
  18 #include "hw/pci/pcie_port.h"
  19 #include "hw/qdev-properties.h"
  20 #include "hw/pci/pci_bridge.h"
  21 #include "hw/pci-bridge/pci_expander_bridge.h"
  22 #include "hw/cxl/cxl.h"
  23 #include "qemu/range.h"
  24 #include "qemu/error-report.h"
  25 #include "qemu/module.h"
  26 #include "sysemu/numa.h"
  27 #include "hw/boards.h"
  28 #include "qom/object.h"
  29
  30 enum BusType { PCI, PCIE, CXL };
  31
  32 #define TYPE_PXB_BUS "pxb-bus"
  33 typedef struct PXBBus PXBBus;
  34 DECLARE_INSTANCE_CHECKER(PXBBus, PXB_BUS,
  35                          TYPE_PXB_BUS)
  36
  37 #define TYPE_PXB_PCIE_BUS "pxb-pcie-bus"
  38 DECLARE_INSTANCE_CHECKER(PXBBus, PXB_PCIE_BUS,
  39                          TYPE_PXB_PCIE_BUS)
  40
  41 #define TYPE_PXB_CXL_BUS "pxb-cxl-bus"
  42 DECLARE_INSTANCE_CHECKER(PXBBus, PXB_CXL_BUS,
  43                          TYPE_PXB_CXL_BUS)
  44
  45 struct PXBBus {
  46     /*< private >*/
  47     PCIBus parent_obj;
  48     /*< public >*/
  49
  50     char bus_path[8];
  51 };
  52
  53 #define TYPE_PXB_DEVICE "pxb"
  54 DECLARE_INSTANCE_CHECKER(PXBDev, PXB_DEV,
  55                          TYPE_PXB_DEVICE)
  56
  57 #define TYPE_PXB_PCIE_DEVICE "pxb-pcie"
  58 DECLARE_INSTANCE_CHECKER(PXBDev, PXB_PCIE_DEV,
  59                          TYPE_PXB_PCIE_DEVICE)
  60
  61 static PXBDev *convert_to_pxb(PCIDevice *dev)
  62 {
  63     /* A CXL PXB's parent bus is PCIe, so the normal check won't work */
  64     if (object_dynamic_cast(OBJECT(dev), TYPE_PXB_CXL_DEVICE)) {
  65         return PXB_CXL_DEV(dev);
  66     }
  67
  68     return pci_bus_is_express(pci_get_bus(dev))
  69         ? PXB_PCIE_DEV(dev) : PXB_DEV(dev);
  70 }
  71
  72 static GList *pxb_dev_list;
  73
  74 #define TYPE_PXB_HOST "pxb-host"
  75
  76 CXLComponentState *cxl_get_hb_cstate(PCIHostState *hb)
  77 {
  78     CXLHost *host = PXB_CXL_HOST(hb);
  79
  80     return &host->cxl_cstate;
  81 }
  82
  83 bool cxl_get_hb_passthrough(PCIHostState *hb)
  84 {
  85     CXLHost *host = PXB_CXL_HOST(hb);
  86
  87     return host->passthrough;
  88 }
  89
  90 static int pxb_bus_num(PCIBus *bus)
  91 {
  92     PXBDev *pxb = convert_to_pxb(bus->parent_dev);
  93
  94     return pxb->bus_nr;
  95 }
  96
  97 static uint16_t pxb_bus_numa_node(PCIBus *bus)
  98 {
  99     PXBDev *pxb = convert_to_pxb(bus->parent_dev);
 100
 101     return pxb->numa_node;
 102 }
 103
 104 static void pxb_bus_class_init(ObjectClass *class, void *data)
 105 {
 106     PCIBusClass *pbc = PCI_BUS_CLASS(class);
 107
 108     pbc->bus_num = pxb_bus_num;
 109     pbc->numa_node = pxb_bus_numa_node;
 110 }
 111
 112 static const TypeInfo pxb_bus_info = {
 113     .name          = TYPE_PXB_BUS,
 114     .parent        = TYPE_PCI_BUS,
 115     .instance_size = sizeof(PXBBus),
 116     .class_init    = pxb_bus_class_init,
 117 };
 118
 119 static const TypeInfo pxb_pcie_bus_info = {
 120     .name          = TYPE_PXB_PCIE_BUS,
 121     .parent        = TYPE_PCIE_BUS,
 122     .instance_size = sizeof(PXBBus),
 123     .class_init    = pxb_bus_class_init,
 124 };
 125
 126 static const TypeInfo pxb_cxl_bus_info = {
 127     .name          = TYPE_PXB_CXL_BUS,
 128     .parent        = TYPE_CXL_BUS,
 129     .instance_size = sizeof(PXBBus),
 130     .class_init    = pxb_bus_class_init,
 131 };
 132
 133 static const char *pxb_host_root_bus_path(PCIHostState *host_bridge,
 134                                           PCIBus *rootbus)
 135 {
 136     PXBBus *bus = pci_bus_is_cxl(rootbus) ?
 137                       PXB_CXL_BUS(rootbus) :
 138                       pci_bus_is_express(rootbus) ? PXB_PCIE_BUS(rootbus) :
 139                                                     PXB_BUS(rootbus);
 140
 141     snprintf(bus->bus_path, 8, "0000:%02x", pxb_bus_num(rootbus));
 142     return bus->bus_path;
 143 }
 144
 145 static char *pxb_host_ofw_unit_address(const SysBusDevice *dev)
 146 {
 147     const PCIHostState *pxb_host;
 148     const PCIBus *pxb_bus;
 149     const PXBDev *pxb_dev;
 150     int position;
 151     const DeviceState *pxb_dev_base;
 152     const PCIHostState *main_host;
 153     const SysBusDevice *main_host_sbd;
 154
 155     pxb_host = PCI_HOST_BRIDGE(dev);
 156     pxb_bus = pxb_host->bus;
 157     pxb_dev = convert_to_pxb(pxb_bus->parent_dev);
 158     position = g_list_index(pxb_dev_list, pxb_dev);
 159     assert(position >= 0);
 160
 161     pxb_dev_base = DEVICE(pxb_dev);
 162     main_host = PCI_HOST_BRIDGE(pxb_dev_base->parent_bus->parent);
 163     main_host_sbd = SYS_BUS_DEVICE(main_host);
 164
 165     if (main_host_sbd->num_mmio > 0) {
 166         return g_strdup_printf(HWADDR_FMT_plx ",%x",
 167                                main_host_sbd->mmio[0].addr, position + 1);
 168     }
 169     if (main_host_sbd->num_pio > 0) {
 170         return g_strdup_printf("i%04x,%x",
 171                                main_host_sbd->pio[0], position + 1);
 172     }
 173     return NULL;
 174 }
 175
 176 static void pxb_host_class_init(ObjectClass *class, void *data)
 177 {
 178     DeviceClass *dc = DEVICE_CLASS(class);
 179     SysBusDeviceClass *sbc = SYS_BUS_DEVICE_CLASS(class);
 180     PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_CLASS(class);
 181
 182     dc->fw_name = "pci";
 183     /* Reason: Internal part of the pxb/pxb-pcie device, not usable by itself */
 184     dc->user_creatable = false;
 185     sbc->explicit_ofw_unit_address = pxb_host_ofw_unit_address;
 186     hc->root_bus_path = pxb_host_root_bus_path;
 187 }
 188
 189 static const TypeInfo pxb_host_info = {
 190     .name          = TYPE_PXB_HOST,
 191     .parent        = TYPE_PCI_HOST_BRIDGE,
 192     .class_init    = pxb_host_class_init,
 193 };
 194
 195 static void pxb_cxl_realize(DeviceState *dev, Error **errp)
 196 {
 197     SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
 198     CXLHost *cxl = PXB_CXL_HOST(dev);
 199     CXLComponentState *cxl_cstate = &cxl->cxl_cstate;
 200     struct MemoryRegion *mr = &cxl_cstate->crb.component_registers;
 201
 202     cxl_component_register_block_init(OBJECT(dev), cxl_cstate,
 203                                       TYPE_PXB_CXL_HOST);
 204     sysbus_init_mmio(sbd, mr);
 205 }
 206
 207 /*
 208  * Host bridge realization has no means of knowning state associated
 209  * with a particular machine. As such, it is nececssary to delay
 210  * final setup of the host bridge register space until later in the
 211  * machine bring up.
 212  */
 213 void pxb_cxl_hook_up_registers(CXLState *cxl_state, PCIBus *bus, Error **errp)
 214 {
 215     PXBDev *pxb =  PXB_CXL_DEV(pci_bridge_get_device(bus));
 216     CXLHost *cxl = pxb->cxl.cxl_host_bridge;
 217     CXLComponentState *cxl_cstate = &cxl->cxl_cstate;
 218     struct MemoryRegion *mr = &cxl_cstate->crb.component_registers;
 219     hwaddr offset;
 220
 221     offset = memory_region_size(mr) * cxl_state->next_mr_idx;
 222     if (offset > memory_region_size(&cxl_state->host_mr)) {
 223         error_setg(errp, "Insufficient space for pxb cxl host register space");
 224         return;
 225     }
 226
 227     memory_region_add_subregion(&cxl_state->host_mr, offset, mr);
 228     cxl_state->next_mr_idx++;
 229 }
 230
 231 static void pxb_cxl_host_class_init(ObjectClass *class, void *data)
 232 {
 233     DeviceClass *dc = DEVICE_CLASS(class);
 234     PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_CLASS(class);
 235
 236     hc->root_bus_path = pxb_host_root_bus_path;
 237     dc->fw_name = "cxl";
 238     dc->realize = pxb_cxl_realize;
 239     /* Reason: Internal part of the pxb/pxb-pcie device, not usable by itself */
 240     dc->user_creatable = false;
 241 }
 242
 243 /*
 244  * This is a device to handle the MMIO for a CXL host bridge. It does nothing
 245  * else.
 246  */
 247 static const TypeInfo cxl_host_info = {
 248     .name          = TYPE_PXB_CXL_HOST,
 249     .parent        = TYPE_PCI_HOST_BRIDGE,
 250     .instance_size = sizeof(CXLHost),
 251     .class_init    = pxb_cxl_host_class_init,
 252 };
 253
 254 /*
 255  * Registers the PXB bus as a child of pci host root bus.
 256  */
 257 static void pxb_register_bus(PCIDevice *dev, PCIBus *pxb_bus, Error **errp)
 258 {
 259     PCIBus *bus = pci_get_bus(dev);
 260     int pxb_bus_num = pci_bus_num(pxb_bus);
 261
 262     if (bus->parent_dev) {
 263         error_setg(errp, "PXB devices can be attached only to root bus");
 264         return;
 265     }
 266
 267     QLIST_FOREACH(bus, &bus->child, sibling) {
 268         if (pci_bus_num(bus) == pxb_bus_num) {
 269             error_setg(errp, "Bus %d is already in use", pxb_bus_num);
 270             return;
 271         }
 272     }
 273     QLIST_INSERT_HEAD(&pci_get_bus(dev)->child, pxb_bus, sibling);
 274 }
 275
 276 static int pxb_map_irq_fn(PCIDevice *pci_dev, int pin)
 277 {
 278     PCIDevice *pxb = pci_get_bus(pci_dev)->parent_dev;
 279
 280     /*
 281      * First carry out normal swizzle to handle
 282      * multple root ports on a pxb instance.
 283      */
 284     pin = pci_swizzle_map_irq_fn(pci_dev, pin);
 285
 286     /*
 287      * The bios does not index the pxb slot number when
 288      * it computes the IRQ because it resides on bus 0
 289      * and not on the current bus.
 290      * However QEMU routes the irq through bus 0 and adds
 291      * the pxb slot to the IRQ computation of the PXB
 292      * device.
 293      *
 294      * Synchronize between bios and QEMU by canceling
 295      * pxb's effect.
 296      */
 297     return pin - PCI_SLOT(pxb->devfn);
 298 }
 299
 300 static void pxb_cxl_dev_reset(DeviceState *dev)
 301 {
 302     CXLHost *cxl = PXB_CXL_DEV(dev)->cxl.cxl_host_bridge;
 303     CXLComponentState *cxl_cstate = &cxl->cxl_cstate;
 304     PCIHostState *hb = PCI_HOST_BRIDGE(cxl);
 305     uint32_t *reg_state = cxl_cstate->crb.cache_mem_registers;
 306     uint32_t *write_msk = cxl_cstate->crb.cache_mem_regs_write_mask;
 307     int dsp_count = 0;
 308
 309     cxl_component_register_init_common(reg_state, write_msk, CXL2_ROOT_PORT);
 310     /*
 311      * The CXL specification allows for host bridges with no HDM decoders
 312      * if they only have a single root port.
 313      */
 314     if (!PXB_DEV(dev)->hdm_for_passthrough) {
 315         dsp_count = pcie_count_ds_ports(hb->bus);
 316     }
 317     /* Initial reset will have 0 dsp so wait until > 0 */
 318     if (dsp_count == 1) {
 319         cxl->passthrough = true;
 320         /* Set Capability ID in header to NONE */
 321         ARRAY_FIELD_DP32(reg_state, CXL_HDM_CAPABILITY_HEADER, ID, 0);
 322     } else {
 323         ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_CAPABILITY, TARGET_COUNT,
 324                          8);
 325     }
 326 }
 327
 328 static gint pxb_compare(gconstpointer a, gconstpointer b)
 329 {
 330     const PXBDev *pxb_a = a, *pxb_b = b;
 331
 332     return pxb_a->bus_nr < pxb_b->bus_nr ? -1 :
 333            pxb_a->bus_nr > pxb_b->bus_nr ?  1 :
 334            0;
 335 }
 336
 337 static void pxb_dev_realize_common(PCIDevice *dev, enum BusType type,
 338                                    Error **errp)
 339 {
 340     PXBDev *pxb = convert_to_pxb(dev);
 341     DeviceState *ds, *bds = NULL;
 342     PCIBus *bus;
 343     const char *dev_name = NULL;
 344     Error *local_err = NULL;
 345     MachineState *ms = MACHINE(qdev_get_machine());
 346
 347     if (ms->numa_state == NULL) {
 348         error_setg(errp, "NUMA is not supported by this machine-type");
 349         return;
 350     }
 351
 352     if (pxb->numa_node != NUMA_NODE_UNASSIGNED &&
 353         pxb->numa_node >= ms->numa_state->num_nodes) {
 354         error_setg(errp, "Illegal numa node %d", pxb->numa_node);
 355         return;
 356     }
 357
 358     if (dev->qdev.id && *dev->qdev.id) {
 359         dev_name = dev->qdev.id;
 360     }
 361
 362     ds = qdev_new(type == CXL ? TYPE_PXB_CXL_HOST : TYPE_PXB_HOST);
 363     if (type == PCIE) {
 364         bus = pci_root_bus_new(ds, dev_name, NULL, NULL, 0, TYPE_PXB_PCIE_BUS);
 365     } else if (type == CXL) {
 366         bus = pci_root_bus_new(ds, dev_name, NULL, NULL, 0, TYPE_PXB_CXL_BUS);
 367         bus->flags |= PCI_BUS_CXL;
 368         PXB_CXL_DEV(dev)->cxl.cxl_host_bridge = PXB_CXL_HOST(ds);
 369     } else {
 370         bus = pci_root_bus_new(ds, "pxb-internal", NULL, NULL, 0, TYPE_PXB_BUS);
 371         bds = qdev_new("pci-bridge");
 372         bds->id = g_strdup(dev_name);
 373         qdev_prop_set_uint8(bds, PCI_BRIDGE_DEV_PROP_CHASSIS_NR, pxb->bus_nr);
 374         qdev_prop_set_bit(bds, PCI_BRIDGE_DEV_PROP_SHPC, false);
 375     }
 376
 377     bus->parent_dev = dev;
 378     bus->address_space_mem = pci_get_bus(dev)->address_space_mem;
 379     bus->address_space_io = pci_get_bus(dev)->address_space_io;
 380     bus->map_irq = pxb_map_irq_fn;
 381
 382     PCI_HOST_BRIDGE(ds)->bus = bus;
 383     PCI_HOST_BRIDGE(ds)->bypass_iommu = pxb->bypass_iommu;
 384
 385     pxb_register_bus(dev, bus, &local_err);
 386     if (local_err) {
 387         error_propagate(errp, local_err);
 388         goto err_register_bus;
 389     }
 390
 391     sysbus_realize_and_unref(SYS_BUS_DEVICE(ds), &error_fatal);
 392     if (bds) {
 393         qdev_realize_and_unref(bds, &bus->qbus, &error_fatal);
 394     }
 395
 396     pci_word_test_and_set_mask(dev->config + PCI_STATUS,
 397                                PCI_STATUS_66MHZ | PCI_STATUS_FAST_BACK);
 398     pci_config_set_class(dev->config, PCI_CLASS_BRIDGE_HOST);
 399
 400     pxb_dev_list = g_list_insert_sorted(pxb_dev_list, pxb, pxb_compare);
 401     return;
 402
 403 err_register_bus:
 404     object_unref(OBJECT(bds));
 405     object_unparent(OBJECT(bus));
 406     object_unref(OBJECT(ds));
 407 }
 408
 409 static void pxb_dev_realize(PCIDevice *dev, Error **errp)
 410 {
 411     if (pci_bus_is_express(pci_get_bus(dev))) {
 412         error_setg(errp, "pxb devices cannot reside on a PCIe bus");
 413         return;
 414     }
 415
 416     pxb_dev_realize_common(dev, PCI, errp);
 417 }
 418
 419 static void pxb_dev_exitfn(PCIDevice *pci_dev)
 420 {
 421     PXBDev *pxb = convert_to_pxb(pci_dev);
 422
 423     pxb_dev_list = g_list_remove(pxb_dev_list, pxb);
 424 }
 425
 426 static Property pxb_dev_properties[] = {
 427     /* Note: 0 is not a legal PXB bus number. */
 428     DEFINE_PROP_UINT8("bus_nr", PXBDev, bus_nr, 0),
 429     DEFINE_PROP_UINT16("numa_node", PXBDev, numa_node, NUMA_NODE_UNASSIGNED),
 430     DEFINE_PROP_BOOL("bypass_iommu", PXBDev, bypass_iommu, false),
 431     DEFINE_PROP_END_OF_LIST(),
 432 };
 433
 434 static void pxb_dev_class_init(ObjectClass *klass, void *data)
 435 {
 436     DeviceClass *dc = DEVICE_CLASS(klass);
 437     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 438
 439     k->realize = pxb_dev_realize;
 440     k->exit = pxb_dev_exitfn;
 441     k->vendor_id = PCI_VENDOR_ID_REDHAT;
 442     k->device_id = PCI_DEVICE_ID_REDHAT_PXB;
 443     k->class_id = PCI_CLASS_BRIDGE_HOST;
 444
 445     dc->desc = "PCI Expander Bridge";
 446     device_class_set_props(dc, pxb_dev_properties);
 447     dc->hotpluggable = false;
 448     set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
 449 }
 450
 451 static const TypeInfo pxb_dev_info = {
 452     .name          = TYPE_PXB_DEVICE,
 453     .parent        = TYPE_PCI_DEVICE,
 454     .instance_size = sizeof(PXBDev),
 455     .class_init    = pxb_dev_class_init,
 456     .interfaces = (InterfaceInfo[]) {
 457         { INTERFACE_CONVENTIONAL_PCI_DEVICE },
 458         { },
 459     },
 460 };
 461
 462 static void pxb_pcie_dev_realize(PCIDevice *dev, Error **errp)
 463 {
 464     if (!pci_bus_is_express(pci_get_bus(dev))) {
 465         error_setg(errp, "pxb-pcie devices cannot reside on a PCI bus");
 466         return;
 467     }
 468
 469     pxb_dev_realize_common(dev, PCIE, errp);
 470 }
 471
 472 static void pxb_pcie_dev_class_init(ObjectClass *klass, void *data)
 473 {
 474     DeviceClass *dc = DEVICE_CLASS(klass);
 475     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 476
 477     k->realize = pxb_pcie_dev_realize;
 478     k->exit = pxb_dev_exitfn;
 479     k->vendor_id = PCI_VENDOR_ID_REDHAT;
 480     k->device_id = PCI_DEVICE_ID_REDHAT_PXB_PCIE;
 481     k->class_id = PCI_CLASS_BRIDGE_HOST;
 482
 483     dc->desc = "PCI Express Expander Bridge";
 484     device_class_set_props(dc, pxb_dev_properties);
 485     dc->hotpluggable = false;
 486     set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
 487 }
 488
 489 static const TypeInfo pxb_pcie_dev_info = {
 490     .name          = TYPE_PXB_PCIE_DEVICE,
 491     .parent        = TYPE_PCI_DEVICE,
 492     .instance_size = sizeof(PXBDev),
 493     .class_init    = pxb_pcie_dev_class_init,
 494     .interfaces = (InterfaceInfo[]) {
 495         { INTERFACE_CONVENTIONAL_PCI_DEVICE },
 496         { },
 497     },
 498 };
 499
 500 static void pxb_cxl_dev_realize(PCIDevice *dev, Error **errp)
 501 {
 502     /* A CXL PXB's parent bus is still PCIe */
 503     if (!pci_bus_is_express(pci_get_bus(dev))) {
 504         error_setg(errp, "pxb-cxl devices cannot reside on a PCI bus");
 505         return;
 506     }
 507
 508     pxb_dev_realize_common(dev, CXL, errp);
 509     pxb_cxl_dev_reset(DEVICE(dev));
 510 }
 511
 512 static Property pxb_cxl_dev_properties[] = {
 513     /* Note: 0 is not a legal PXB bus number. */
 514     DEFINE_PROP_UINT8("bus_nr", PXBDev, bus_nr, 0),
 515     DEFINE_PROP_UINT16("numa_node", PXBDev, numa_node, NUMA_NODE_UNASSIGNED),
 516     DEFINE_PROP_BOOL("bypass_iommu", PXBDev, bypass_iommu, false),
 517     DEFINE_PROP_BOOL("hdm_for_passthrough", PXBDev, hdm_for_passthrough, false),
 518     DEFINE_PROP_END_OF_LIST(),
 519 };
 520
 521 static void pxb_cxl_dev_class_init(ObjectClass *klass, void *data)
 522 {
 523     DeviceClass *dc   = DEVICE_CLASS(klass);
 524     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 525
 526     k->realize             = pxb_cxl_dev_realize;
 527     k->exit                = pxb_dev_exitfn;
 528     /*
 529      * XXX: These types of bridges don't actually show up in the hierarchy so
 530      * vendor, device, class, etc. ids are intentionally left out.
 531      */
 532
 533     dc->desc = "CXL Host Bridge";
 534     device_class_set_props(dc, pxb_cxl_dev_properties);
 535     set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
 536
 537     /* Host bridges aren't hotpluggable. FIXME: spec reference */
 538     dc->hotpluggable = false;
 539     dc->reset = pxb_cxl_dev_reset;
 540 }
 541
 542 static const TypeInfo pxb_cxl_dev_info = {
 543     .name          = TYPE_PXB_CXL_DEVICE,
 544     .parent        = TYPE_PCI_DEVICE,
 545     .instance_size = sizeof(PXBDev),
 546     .class_init    = pxb_cxl_dev_class_init,
 547     .interfaces =
 548         (InterfaceInfo[]){
 549             { INTERFACE_CONVENTIONAL_PCI_DEVICE },
 550             {},
 551         },
 552 };
 553
 554 static void pxb_register_types(void)
 555 {
 556     type_register_static(&pxb_bus_info);
 557     type_register_static(&pxb_pcie_bus_info);
 558     type_register_static(&pxb_cxl_bus_info);
 559     type_register_static(&pxb_host_info);
 560     type_register_static(&cxl_host_info);
 561     type_register_static(&pxb_dev_info);
 562     type_register_static(&pxb_pcie_dev_info);
 563     type_register_static(&pxb_cxl_dev_info);
 564 }
 565
 566 type_init(pxb_register_types)