hw/ppc/spapr_hcall.c

   1 #include "qemu/osdep.h"
   2 #include "qemu/cutils.h"
   3 #include "qapi/error.h"
   4 #include "sysemu/hw_accel.h"
   5 #include "sysemu/runstate.h"
   6 #include "qemu/log.h"
   7 #include "qemu/main-loop.h"
   8 #include "qemu/module.h"
   9 #include "qemu/error-report.h"
  10 #include "exec/exec-all.h"
  11 #include "exec/tb-flush.h"
  12 #include "helper_regs.h"
  13 #include "hw/ppc/ppc.h"
  14 #include "hw/ppc/spapr.h"
  15 #include "hw/ppc/spapr_cpu_core.h"
  16 #include "mmu-hash64.h"
  17 #include "cpu-models.h"
  18 #include "trace.h"
  19 #include "kvm_ppc.h"
  20 #include "hw/ppc/fdt.h"
  21 #include "hw/ppc/spapr_ovec.h"
  22 #include "hw/ppc/spapr_numa.h"
  23 #include "mmu-book3s-v3.h"
  24 #include "hw/mem/memory-device.h"
  25
  26 bool is_ram_address(SpaprMachineState *spapr, hwaddr addr)
  27 {
  28     MachineState *machine = MACHINE(spapr);
  29     DeviceMemoryState *dms = machine->device_memory;
  30
  31     if (addr < machine->ram_size) {
  32         return true;
  33     }
  34     if ((addr >= dms->base)
  35         && ((addr - dms->base) < memory_region_size(&dms->mr))) {
  36         return true;
  37     }
  38
  39     return false;
  40 }
  41
  42 /* Convert a return code from the KVM ioctl()s implementing resize HPT
  43  * into a PAPR hypercall return code */
  44 static target_ulong resize_hpt_convert_rc(int ret)
  45 {
  46     if (ret >= 100000) {
  47         return H_LONG_BUSY_ORDER_100_SEC;
  48     } else if (ret >= 10000) {
  49         return H_LONG_BUSY_ORDER_10_SEC;
  50     } else if (ret >= 1000) {
  51         return H_LONG_BUSY_ORDER_1_SEC;
  52     } else if (ret >= 100) {
  53         return H_LONG_BUSY_ORDER_100_MSEC;
  54     } else if (ret >= 10) {
  55         return H_LONG_BUSY_ORDER_10_MSEC;
  56     } else if (ret > 0) {
  57         return H_LONG_BUSY_ORDER_1_MSEC;
  58     }
  59
  60     switch (ret) {
  61     case 0:
  62         return H_SUCCESS;
  63     case -EPERM:
  64         return H_AUTHORITY;
  65     case -EINVAL:
  66         return H_PARAMETER;
  67     case -ENXIO:
  68         return H_CLOSED;
  69     case -ENOSPC:
  70         return H_PTEG_FULL;
  71     case -EBUSY:
  72         return H_BUSY;
  73     case -ENOMEM:
  74         return H_NO_MEM;
  75     default:
  76         return H_HARDWARE;
  77     }
  78 }
  79
  80 static target_ulong h_resize_hpt_prepare(PowerPCCPU *cpu,
  81                                          SpaprMachineState *spapr,
  82                                          target_ulong opcode,
  83                                          target_ulong *args)
  84 {
  85     target_ulong flags = args[0];
  86     int shift = args[1];
  87     uint64_t current_ram_size;
  88     int rc;
  89
  90     if (spapr->resize_hpt == SPAPR_RESIZE_HPT_DISABLED) {
  91         return H_AUTHORITY;
  92     }
  93
  94     if (!spapr->htab_shift) {
  95         /* Radix guest, no HPT */
  96         return H_NOT_AVAILABLE;
  97     }
  98
  99     trace_spapr_h_resize_hpt_prepare(flags, shift);
 100
 101     if (flags != 0) {
 102         return H_PARAMETER;
 103     }
 104
 105     if (shift && ((shift < 18) || (shift > 46))) {
 106         return H_PARAMETER;
 107     }
 108
 109     current_ram_size = MACHINE(spapr)->ram_size + get_plugged_memory_size();
 110
 111     /* We only allow the guest to allocate an HPT one order above what
 112      * we'd normally give them (to stop a small guest claiming a huge
 113      * chunk of resources in the HPT */
 114     if (shift > (spapr_hpt_shift_for_ramsize(current_ram_size) + 1)) {
 115         return H_RESOURCE;
 116     }
 117
 118     rc = kvmppc_resize_hpt_prepare(cpu, flags, shift);
 119     if (rc != -ENOSYS) {
 120         return resize_hpt_convert_rc(rc);
 121     }
 122
 123     if (kvm_enabled()) {
 124         return H_HARDWARE;
 125     }
 126
 127     return softmmu_resize_hpt_prepare(cpu, spapr, shift);
 128 }
 129
 130 static void do_push_sregs_to_kvm_pr(CPUState *cs, run_on_cpu_data data)
 131 {
 132     int ret;
 133
 134     cpu_synchronize_state(cs);
 135
 136     ret = kvmppc_put_books_sregs(POWERPC_CPU(cs));
 137     if (ret < 0) {
 138         error_report("failed to push sregs to KVM: %s", strerror(-ret));
 139         exit(1);
 140     }
 141 }
 142
 143 void push_sregs_to_kvm_pr(SpaprMachineState *spapr)
 144 {
 145     CPUState *cs;
 146
 147     /*
 148      * This is a hack for the benefit of KVM PR - it abuses the SDR1
 149      * slot in kvm_sregs to communicate the userspace address of the
 150      * HPT
 151      */
 152     if (!kvm_enabled() || !spapr->htab) {
 153         return;
 154     }
 155
 156     CPU_FOREACH(cs) {
 157         run_on_cpu(cs, do_push_sregs_to_kvm_pr, RUN_ON_CPU_NULL);
 158     }
 159 }
 160
 161 static target_ulong h_resize_hpt_commit(PowerPCCPU *cpu,
 162                                         SpaprMachineState *spapr,
 163                                         target_ulong opcode,
 164                                         target_ulong *args)
 165 {
 166     target_ulong flags = args[0];
 167     target_ulong shift = args[1];
 168     int rc;
 169
 170     if (spapr->resize_hpt == SPAPR_RESIZE_HPT_DISABLED) {
 171         return H_AUTHORITY;
 172     }
 173
 174     if (!spapr->htab_shift) {
 175         /* Radix guest, no HPT */
 176         return H_NOT_AVAILABLE;
 177     }
 178
 179     trace_spapr_h_resize_hpt_commit(flags, shift);
 180
 181     rc = kvmppc_resize_hpt_commit(cpu, flags, shift);
 182     if (rc != -ENOSYS) {
 183         rc = resize_hpt_convert_rc(rc);
 184         if (rc == H_SUCCESS) {
 185             /* Need to set the new htab_shift in the machine state */
 186             spapr->htab_shift = shift;
 187         }
 188         return rc;
 189     }
 190
 191     if (kvm_enabled()) {
 192         return H_HARDWARE;
 193     }
 194
 195     return softmmu_resize_hpt_commit(cpu, spapr, flags, shift);
 196 }
 197
 198
 199
 200 static target_ulong h_set_sprg0(PowerPCCPU *cpu, SpaprMachineState *spapr,
 201                                 target_ulong opcode, target_ulong *args)
 202 {
 203     cpu_synchronize_state(CPU(cpu));
 204     cpu->env.spr[SPR_SPRG0] = args[0];
 205
 206     return H_SUCCESS;
 207 }
 208
 209 static target_ulong h_set_dabr(PowerPCCPU *cpu, SpaprMachineState *spapr,
 210                                target_ulong opcode, target_ulong *args)
 211 {
 212     if (!ppc_has_spr(cpu, SPR_DABR)) {
 213         return H_HARDWARE;              /* DABR register not available */
 214     }
 215     cpu_synchronize_state(CPU(cpu));
 216
 217     if (ppc_has_spr(cpu, SPR_DABRX)) {
 218         cpu->env.spr[SPR_DABRX] = 0x3;  /* Use Problem and Privileged state */
 219     } else if (!(args[0] & 0x4)) {      /* Breakpoint Translation set? */
 220         return H_RESERVED_DABR;
 221     }
 222
 223     cpu->env.spr[SPR_DABR] = args[0];
 224     return H_SUCCESS;
 225 }
 226
 227 static target_ulong h_set_xdabr(PowerPCCPU *cpu, SpaprMachineState *spapr,
 228                                 target_ulong opcode, target_ulong *args)
 229 {
 230     target_ulong dabrx = args[1];
 231
 232     if (!ppc_has_spr(cpu, SPR_DABR) || !ppc_has_spr(cpu, SPR_DABRX)) {
 233         return H_HARDWARE;
 234     }
 235
 236     if ((dabrx & ~0xfULL) != 0 || (dabrx & H_DABRX_HYPERVISOR) != 0
 237         || (dabrx & (H_DABRX_KERNEL | H_DABRX_USER)) == 0) {
 238         return H_PARAMETER;
 239     }
 240
 241     cpu_synchronize_state(CPU(cpu));
 242     cpu->env.spr[SPR_DABRX] = dabrx;
 243     cpu->env.spr[SPR_DABR] = args[0];
 244
 245     return H_SUCCESS;
 246 }
 247
 248 static target_ulong h_page_init(PowerPCCPU *cpu, SpaprMachineState *spapr,
 249                                 target_ulong opcode, target_ulong *args)
 250 {
 251     target_ulong flags = args[0];
 252     hwaddr dst = args[1];
 253     hwaddr src = args[2];
 254     hwaddr len = TARGET_PAGE_SIZE;
 255     uint8_t *pdst, *psrc;
 256     target_long ret = H_SUCCESS;
 257
 258     if (flags & ~(H_ICACHE_SYNCHRONIZE | H_ICACHE_INVALIDATE
 259                   | H_COPY_PAGE | H_ZERO_PAGE)) {
 260         qemu_log_mask(LOG_UNIMP, "h_page_init: Bad flags (" TARGET_FMT_lx "\n",
 261                       flags);
 262         return H_PARAMETER;
 263     }
 264
 265     /* Map-in destination */
 266     if (!is_ram_address(spapr, dst) || (dst & ~TARGET_PAGE_MASK) != 0) {
 267         return H_PARAMETER;
 268     }
 269     pdst = cpu_physical_memory_map(dst, &len, true);
 270     if (!pdst || len != TARGET_PAGE_SIZE) {
 271         return H_PARAMETER;
 272     }
 273
 274     if (flags & H_COPY_PAGE) {
 275         /* Map-in source, copy to destination, and unmap source again */
 276         if (!is_ram_address(spapr, src) || (src & ~TARGET_PAGE_MASK) != 0) {
 277             ret = H_PARAMETER;
 278             goto unmap_out;
 279         }
 280         psrc = cpu_physical_memory_map(src, &len, false);
 281         if (!psrc || len != TARGET_PAGE_SIZE) {
 282             ret = H_PARAMETER;
 283             goto unmap_out;
 284         }
 285         memcpy(pdst, psrc, len);
 286         cpu_physical_memory_unmap(psrc, len, 0, len);
 287     } else if (flags & H_ZERO_PAGE) {
 288         memset(pdst, 0, len);          /* Just clear the destination page */
 289     }
 290
 291     if (kvm_enabled() && (flags & H_ICACHE_SYNCHRONIZE) != 0) {
 292         kvmppc_dcbst_range(cpu, pdst, len);
 293     }
 294     if (flags & (H_ICACHE_SYNCHRONIZE | H_ICACHE_INVALIDATE)) {
 295         if (kvm_enabled()) {
 296             kvmppc_icbi_range(cpu, pdst, len);
 297         } else {
 298             tb_flush(CPU(cpu));
 299         }
 300     }
 301
 302 unmap_out:
 303     cpu_physical_memory_unmap(pdst, TARGET_PAGE_SIZE, 1, len);
 304     return ret;
 305 }
 306
 307 #define FLAGS_REGISTER_VPA         0x0000200000000000ULL
 308 #define FLAGS_REGISTER_DTL         0x0000400000000000ULL
 309 #define FLAGS_REGISTER_SLBSHADOW   0x0000600000000000ULL
 310 #define FLAGS_DEREGISTER_VPA       0x0000a00000000000ULL
 311 #define FLAGS_DEREGISTER_DTL       0x0000c00000000000ULL
 312 #define FLAGS_DEREGISTER_SLBSHADOW 0x0000e00000000000ULL
 313
 314 static target_ulong register_vpa(PowerPCCPU *cpu, target_ulong vpa)
 315 {
 316     CPUState *cs = CPU(cpu);
 317     CPUPPCState *env = &cpu->env;
 318     SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu);
 319     uint16_t size;
 320     uint8_t tmp;
 321
 322     if (vpa == 0) {
 323         hcall_dprintf("Can't cope with registering a VPA at logical 0\n");
 324         return H_HARDWARE;
 325     }
 326
 327     if (vpa % env->dcache_line_size) {
 328         return H_PARAMETER;
 329     }
 330     /* FIXME: bounds check the address */
 331
 332     size = lduw_be_phys(cs->as, vpa + 0x4);
 333
 334     if (size < VPA_MIN_SIZE) {
 335         return H_PARAMETER;
 336     }
 337
 338     /* VPA is not allowed to cross a page boundary */
 339     if ((vpa / 4096) != ((vpa + size - 1) / 4096)) {
 340         return H_PARAMETER;
 341     }
 342
 343     spapr_cpu->vpa_addr = vpa;
 344
 345     tmp = ldub_phys(cs->as, spapr_cpu->vpa_addr + VPA_SHARED_PROC_OFFSET);
 346     tmp |= VPA_SHARED_PROC_VAL;
 347     stb_phys(cs->as, spapr_cpu->vpa_addr + VPA_SHARED_PROC_OFFSET, tmp);
 348
 349     return H_SUCCESS;
 350 }
 351
 352 static target_ulong deregister_vpa(PowerPCCPU *cpu, target_ulong vpa)
 353 {
 354     SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu);
 355
 356     if (spapr_cpu->slb_shadow_addr) {
 357         return H_RESOURCE;
 358     }
 359
 360     if (spapr_cpu->dtl_addr) {
 361         return H_RESOURCE;
 362     }
 363
 364     spapr_cpu->vpa_addr = 0;
 365     return H_SUCCESS;
 366 }
 367
 368 static target_ulong register_slb_shadow(PowerPCCPU *cpu, target_ulong addr)
 369 {
 370     SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu);
 371     uint32_t size;
 372
 373     if (addr == 0) {
 374         hcall_dprintf("Can't cope with SLB shadow at logical 0\n");
 375         return H_HARDWARE;
 376     }
 377
 378     size = ldl_be_phys(CPU(cpu)->as, addr + 0x4);
 379     if (size < 0x8) {
 380         return H_PARAMETER;
 381     }
 382
 383     if ((addr / 4096) != ((addr + size - 1) / 4096)) {
 384         return H_PARAMETER;
 385     }
 386
 387     if (!spapr_cpu->vpa_addr) {
 388         return H_RESOURCE;
 389     }
 390
 391     spapr_cpu->slb_shadow_addr = addr;
 392     spapr_cpu->slb_shadow_size = size;
 393
 394     return H_SUCCESS;
 395 }
 396
 397 static target_ulong deregister_slb_shadow(PowerPCCPU *cpu, target_ulong addr)
 398 {
 399     SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu);
 400
 401     spapr_cpu->slb_shadow_addr = 0;
 402     spapr_cpu->slb_shadow_size = 0;
 403     return H_SUCCESS;
 404 }
 405
 406 static target_ulong register_dtl(PowerPCCPU *cpu, target_ulong addr)
 407 {
 408     SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu);
 409     uint32_t size;
 410
 411     if (addr == 0) {
 412         hcall_dprintf("Can't cope with DTL at logical 0\n");
 413         return H_HARDWARE;
 414     }
 415
 416     size = ldl_be_phys(CPU(cpu)->as, addr + 0x4);
 417
 418     if (size < 48) {
 419         return H_PARAMETER;
 420     }
 421
 422     if (!spapr_cpu->vpa_addr) {
 423         return H_RESOURCE;
 424     }
 425
 426     spapr_cpu->dtl_addr = addr;
 427     spapr_cpu->dtl_size = size;
 428
 429     return H_SUCCESS;
 430 }
 431
 432 static target_ulong deregister_dtl(PowerPCCPU *cpu, target_ulong addr)
 433 {
 434     SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu);
 435
 436     spapr_cpu->dtl_addr = 0;
 437     spapr_cpu->dtl_size = 0;
 438
 439     return H_SUCCESS;
 440 }
 441
 442 static target_ulong h_register_vpa(PowerPCCPU *cpu, SpaprMachineState *spapr,
 443                                    target_ulong opcode, target_ulong *args)
 444 {
 445     target_ulong flags = args[0];
 446     target_ulong procno = args[1];
 447     target_ulong vpa = args[2];
 448     target_ulong ret = H_PARAMETER;
 449     PowerPCCPU *tcpu;
 450
 451     tcpu = spapr_find_cpu(procno);
 452     if (!tcpu) {
 453         return H_PARAMETER;
 454     }
 455
 456     switch (flags) {
 457     case FLAGS_REGISTER_VPA:
 458         ret = register_vpa(tcpu, vpa);
 459         break;
 460
 461     case FLAGS_DEREGISTER_VPA:
 462         ret = deregister_vpa(tcpu, vpa);
 463         break;
 464
 465     case FLAGS_REGISTER_SLBSHADOW:
 466         ret = register_slb_shadow(tcpu, vpa);
 467         break;
 468
 469     case FLAGS_DEREGISTER_SLBSHADOW:
 470         ret = deregister_slb_shadow(tcpu, vpa);
 471         break;
 472
 473     case FLAGS_REGISTER_DTL:
 474         ret = register_dtl(tcpu, vpa);
 475         break;
 476
 477     case FLAGS_DEREGISTER_DTL:
 478         ret = deregister_dtl(tcpu, vpa);
 479         break;
 480     }
 481
 482     return ret;
 483 }
 484
 485 static target_ulong h_cede(PowerPCCPU *cpu, SpaprMachineState *spapr,
 486                            target_ulong opcode, target_ulong *args)
 487 {
 488     CPUPPCState *env = &cpu->env;
 489     CPUState *cs = CPU(cpu);
 490     SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu);
 491
 492     env->msr |= (1ULL << MSR_EE);
 493     hreg_compute_hflags(env);
 494     ppc_maybe_interrupt(env);
 495
 496     if (spapr_cpu->prod) {
 497         spapr_cpu->prod = false;
 498         return H_SUCCESS;
 499     }
 500
 501     if (!cpu_has_work(cs)) {
 502         cs->halted = 1;
 503         cs->exception_index = EXCP_HLT;
 504         cs->exit_request = 1;
 505         ppc_maybe_interrupt(env);
 506     }
 507
 508     return H_SUCCESS;
 509 }
 510
 511 /*
 512  * Confer to self, aka join. Cede could use the same pattern as well, if
 513  * EXCP_HLT can be changed to ECXP_HALTED.
 514  */
 515 static target_ulong h_confer_self(PowerPCCPU *cpu)
 516 {
 517     CPUState *cs = CPU(cpu);
 518     SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu);
 519
 520     if (spapr_cpu->prod) {
 521         spapr_cpu->prod = false;
 522         return H_SUCCESS;
 523     }
 524     cs->halted = 1;
 525     cs->exception_index = EXCP_HALTED;
 526     cs->exit_request = 1;
 527     ppc_maybe_interrupt(&cpu->env);
 528
 529     return H_SUCCESS;
 530 }
 531
 532 static target_ulong h_join(PowerPCCPU *cpu, SpaprMachineState *spapr,
 533                            target_ulong opcode, target_ulong *args)
 534 {
 535     CPUPPCState *env = &cpu->env;
 536     CPUState *cs;
 537     bool last_unjoined = true;
 538
 539     if (env->msr & (1ULL << MSR_EE)) {
 540         return H_BAD_MODE;
 541     }
 542
 543     /*
 544      * Must not join the last CPU running. Interestingly, no such restriction
 545      * for H_CONFER-to-self, but that is probably not intended to be used
 546      * when H_JOIN is available.
 547      */
 548     CPU_FOREACH(cs) {
 549         PowerPCCPU *c = POWERPC_CPU(cs);
 550         CPUPPCState *e = &c->env;
 551         if (c == cpu) {
 552             continue;
 553         }
 554
 555         /* Don't have a way to indicate joined, so use halted && MSR[EE]=0 */
 556         if (!cs->halted || (e->msr & (1ULL << MSR_EE))) {
 557             last_unjoined = false;
 558             break;
 559         }
 560     }
 561     if (last_unjoined) {
 562         return H_CONTINUE;
 563     }
 564
 565     return h_confer_self(cpu);
 566 }
 567
 568 static target_ulong h_confer(PowerPCCPU *cpu, SpaprMachineState *spapr,
 569                            target_ulong opcode, target_ulong *args)
 570 {
 571     target_long target = args[0];
 572     uint32_t dispatch = args[1];
 573     CPUState *cs = CPU(cpu);
 574     SpaprCpuState *spapr_cpu;
 575
 576     /*
 577      * -1 means confer to all other CPUs without dispatch counter check,
 578      *  otherwise it's a targeted confer.
 579      */
 580     if (target != -1) {
 581         PowerPCCPU *target_cpu = spapr_find_cpu(target);
 582         uint32_t target_dispatch;
 583
 584         if (!target_cpu) {
 585             return H_PARAMETER;
 586         }
 587
 588         /*
 589          * target == self is a special case, we wait until prodded, without
 590          * dispatch counter check.
 591          */
 592         if (cpu == target_cpu) {
 593             return h_confer_self(cpu);
 594         }
 595
 596         spapr_cpu = spapr_cpu_state(target_cpu);
 597         if (!spapr_cpu->vpa_addr || ((dispatch & 1) == 0)) {
 598             return H_SUCCESS;
 599         }
 600
 601         target_dispatch = ldl_be_phys(cs->as,
 602                                   spapr_cpu->vpa_addr + VPA_DISPATCH_COUNTER);
 603         if (target_dispatch != dispatch) {
 604             return H_SUCCESS;
 605         }
 606
 607         /*
 608          * The targeted confer does not do anything special beyond yielding
 609          * the current vCPU, but even this should be better than nothing.
 610          * At least for single-threaded tcg, it gives the target a chance to
 611          * run before we run again. Multi-threaded tcg does not really do
 612          * anything with EXCP_YIELD yet.
 613          */
 614     }
 615
 616     cs->exception_index = EXCP_YIELD;
 617     cs->exit_request = 1;
 618     cpu_loop_exit(cs);
 619
 620     return H_SUCCESS;
 621 }
 622
 623 static target_ulong h_prod(PowerPCCPU *cpu, SpaprMachineState *spapr,
 624                            target_ulong opcode, target_ulong *args)
 625 {
 626     target_long target = args[0];
 627     PowerPCCPU *tcpu;
 628     CPUState *cs;
 629     SpaprCpuState *spapr_cpu;
 630
 631     tcpu = spapr_find_cpu(target);
 632     cs = CPU(tcpu);
 633     if (!cs) {
 634         return H_PARAMETER;
 635     }
 636
 637     spapr_cpu = spapr_cpu_state(tcpu);
 638     spapr_cpu->prod = true;
 639     cs->halted = 0;
 640     ppc_maybe_interrupt(&cpu->env);
 641     qemu_cpu_kick(cs);
 642
 643     return H_SUCCESS;
 644 }
 645
 646 static target_ulong h_rtas(PowerPCCPU *cpu, SpaprMachineState *spapr,
 647                            target_ulong opcode, target_ulong *args)
 648 {
 649     target_ulong rtas_r3 = args[0];
 650     uint32_t token = rtas_ld(rtas_r3, 0);
 651     uint32_t nargs = rtas_ld(rtas_r3, 1);
 652     uint32_t nret = rtas_ld(rtas_r3, 2);
 653
 654     return spapr_rtas_call(cpu, spapr, token, nargs, rtas_r3 + 12,
 655                            nret, rtas_r3 + 12 + 4*nargs);
 656 }
 657
 658 static target_ulong h_logical_load(PowerPCCPU *cpu, SpaprMachineState *spapr,
 659                                    target_ulong opcode, target_ulong *args)
 660 {
 661     CPUState *cs = CPU(cpu);
 662     target_ulong size = args[0];
 663     target_ulong addr = args[1];
 664
 665     switch (size) {
 666     case 1:
 667         args[0] = ldub_phys(cs->as, addr);
 668         return H_SUCCESS;
 669     case 2:
 670         args[0] = lduw_phys(cs->as, addr);
 671         return H_SUCCESS;
 672     case 4:
 673         args[0] = ldl_phys(cs->as, addr);
 674         return H_SUCCESS;
 675     case 8:
 676         args[0] = ldq_phys(cs->as, addr);
 677         return H_SUCCESS;
 678     }
 679     return H_PARAMETER;
 680 }
 681
 682 static target_ulong h_logical_store(PowerPCCPU *cpu, SpaprMachineState *spapr,
 683                                     target_ulong opcode, target_ulong *args)
 684 {
 685     CPUState *cs = CPU(cpu);
 686
 687     target_ulong size = args[0];
 688     target_ulong addr = args[1];
 689     target_ulong val  = args[2];
 690
 691     switch (size) {
 692     case 1:
 693         stb_phys(cs->as, addr, val);
 694         return H_SUCCESS;
 695     case 2:
 696         stw_phys(cs->as, addr, val);
 697         return H_SUCCESS;
 698     case 4:
 699         stl_phys(cs->as, addr, val);
 700         return H_SUCCESS;
 701     case 8:
 702         stq_phys(cs->as, addr, val);
 703         return H_SUCCESS;
 704     }
 705     return H_PARAMETER;
 706 }
 707
 708 static target_ulong h_logical_memop(PowerPCCPU *cpu, SpaprMachineState *spapr,
 709                                     target_ulong opcode, target_ulong *args)
 710 {
 711     CPUState *cs = CPU(cpu);
 712
 713     target_ulong dst   = args[0]; /* Destination address */
 714     target_ulong src   = args[1]; /* Source address */
 715     target_ulong esize = args[2]; /* Element size (0=1,1=2,2=4,3=8) */
 716     target_ulong count = args[3]; /* Element count */
 717     target_ulong op    = args[4]; /* 0 = copy, 1 = invert */
 718     uint64_t tmp;
 719     unsigned int mask = (1 << esize) - 1;
 720     int step = 1 << esize;
 721
 722     if (count > 0x80000000) {
 723         return H_PARAMETER;
 724     }
 725
 726     if ((dst & mask) || (src & mask) || (op > 1)) {
 727         return H_PARAMETER;
 728     }
 729
 730     if (dst >= src && dst < (src + (count << esize))) {
 731             dst = dst + ((count - 1) << esize);
 732             src = src + ((count - 1) << esize);
 733             step = -step;
 734     }
 735
 736     while (count--) {
 737         switch (esize) {
 738         case 0:
 739             tmp = ldub_phys(cs->as, src);
 740             break;
 741         case 1:
 742             tmp = lduw_phys(cs->as, src);
 743             break;
 744         case 2:
 745             tmp = ldl_phys(cs->as, src);
 746             break;
 747         case 3:
 748             tmp = ldq_phys(cs->as, src);
 749             break;
 750         default:
 751             return H_PARAMETER;
 752         }
 753         if (op == 1) {
 754             tmp = ~tmp;
 755         }
 756         switch (esize) {
 757         case 0:
 758             stb_phys(cs->as, dst, tmp);
 759             break;
 760         case 1:
 761             stw_phys(cs->as, dst, tmp);
 762             break;
 763         case 2:
 764             stl_phys(cs->as, dst, tmp);
 765             break;
 766         case 3:
 767             stq_phys(cs->as, dst, tmp);
 768             break;
 769         }
 770         dst = dst + step;
 771         src = src + step;
 772     }
 773
 774     return H_SUCCESS;
 775 }
 776
 777 static target_ulong h_logical_icbi(PowerPCCPU *cpu, SpaprMachineState *spapr,
 778                                    target_ulong opcode, target_ulong *args)
 779 {
 780     /* Nothing to do on emulation, KVM will trap this in the kernel */
 781     return H_SUCCESS;
 782 }
 783
 784 static target_ulong h_logical_dcbf(PowerPCCPU *cpu, SpaprMachineState *spapr,
 785                                    target_ulong opcode, target_ulong *args)
 786 {
 787     /* Nothing to do on emulation, KVM will trap this in the kernel */
 788     return H_SUCCESS;
 789 }
 790
 791 static target_ulong h_set_mode_resource_le(PowerPCCPU *cpu,
 792                                            SpaprMachineState *spapr,
 793                                            target_ulong mflags,
 794                                            target_ulong value1,
 795                                            target_ulong value2)
 796 {
 797     if (value1) {
 798         return H_P3;
 799     }
 800     if (value2) {
 801         return H_P4;
 802     }
 803
 804     switch (mflags) {
 805     case H_SET_MODE_ENDIAN_BIG:
 806         spapr_set_all_lpcrs(0, LPCR_ILE);
 807         spapr_pci_switch_vga(spapr, true);
 808         return H_SUCCESS;
 809
 810     case H_SET_MODE_ENDIAN_LITTLE:
 811         spapr_set_all_lpcrs(LPCR_ILE, LPCR_ILE);
 812         spapr_pci_switch_vga(spapr, false);
 813         return H_SUCCESS;
 814     }
 815
 816     return H_UNSUPPORTED_FLAG;
 817 }
 818
 819 static target_ulong h_set_mode_resource_addr_trans_mode(PowerPCCPU *cpu,
 820                                                         target_ulong mflags,
 821                                                         target_ulong value1,
 822                                                         target_ulong value2)
 823 {
 824     PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
 825
 826     if (!(pcc->insns_flags2 & PPC2_ISA207S)) {
 827         return H_P2;
 828     }
 829     if (value1) {
 830         return H_P3;
 831     }
 832     if (value2) {
 833         return H_P4;
 834     }
 835
 836     if (mflags == 1) {
 837         /* AIL=1 is reserved in POWER8/POWER9/POWER10 */
 838         return H_UNSUPPORTED_FLAG;
 839     }
 840
 841     if (mflags == 2 && (pcc->insns_flags2 & PPC2_ISA310)) {
 842         /* AIL=2 is reserved in POWER10 (ISA v3.1) */
 843         return H_UNSUPPORTED_FLAG;
 844     }
 845
 846     spapr_set_all_lpcrs(mflags << LPCR_AIL_SHIFT, LPCR_AIL);
 847
 848     return H_SUCCESS;
 849 }
 850
 851 static target_ulong h_set_mode(PowerPCCPU *cpu, SpaprMachineState *spapr,
 852                                target_ulong opcode, target_ulong *args)
 853 {
 854     target_ulong resource = args[1];
 855     target_ulong ret = H_P2;
 856
 857     switch (resource) {
 858     case H_SET_MODE_RESOURCE_LE:
 859         ret = h_set_mode_resource_le(cpu, spapr, args[0], args[2], args[3]);
 860         break;
 861     case H_SET_MODE_RESOURCE_ADDR_TRANS_MODE:
 862         ret = h_set_mode_resource_addr_trans_mode(cpu, args[0],
 863                                                   args[2], args[3]);
 864         break;
 865     }
 866
 867     return ret;
 868 }
 869
 870 static target_ulong h_clean_slb(PowerPCCPU *cpu, SpaprMachineState *spapr,
 871                                 target_ulong opcode, target_ulong *args)
 872 {
 873     qemu_log_mask(LOG_UNIMP, "Unimplemented SPAPR hcall 0x"TARGET_FMT_lx"%s\n",
 874                   opcode, " (H_CLEAN_SLB)");
 875     return H_FUNCTION;
 876 }
 877
 878 static target_ulong h_invalidate_pid(PowerPCCPU *cpu, SpaprMachineState *spapr,
 879                                      target_ulong opcode, target_ulong *args)
 880 {
 881     qemu_log_mask(LOG_UNIMP, "Unimplemented SPAPR hcall 0x"TARGET_FMT_lx"%s\n",
 882                   opcode, " (H_INVALIDATE_PID)");
 883     return H_FUNCTION;
 884 }
 885
 886 static void spapr_check_setup_free_hpt(SpaprMachineState *spapr,
 887                                        uint64_t patbe_old, uint64_t patbe_new)
 888 {
 889     /*
 890      * We have 4 Options:
 891      * HASH->HASH || RADIX->RADIX || NOTHING->RADIX : Do Nothing
 892      * HASH->RADIX                                  : Free HPT
 893      * RADIX->HASH                                  : Allocate HPT
 894      * NOTHING->HASH                                : Allocate HPT
 895      * Note: NOTHING implies the case where we said the guest could choose
 896      *       later and so assumed radix and now it's called H_REG_PROC_TBL
 897      */
 898
 899     if ((patbe_old & PATE1_GR) == (patbe_new & PATE1_GR)) {
 900         /* We assume RADIX, so this catches all the "Do Nothing" cases */
 901     } else if (!(patbe_old & PATE1_GR)) {
 902         /* HASH->RADIX : Free HPT */
 903         spapr_free_hpt(spapr);
 904     } else if (!(patbe_new & PATE1_GR)) {
 905         /* RADIX->HASH || NOTHING->HASH : Allocate HPT */
 906         spapr_setup_hpt(spapr);
 907     }
 908     return;
 909 }
 910
 911 #define FLAGS_MASK              0x01FULL
 912 #define FLAG_MODIFY             0x10
 913 #define FLAG_REGISTER           0x08
 914 #define FLAG_RADIX              0x04
 915 #define FLAG_HASH_PROC_TBL      0x02
 916 #define FLAG_GTSE               0x01
 917
 918 static target_ulong h_register_process_table(PowerPCCPU *cpu,
 919                                              SpaprMachineState *spapr,
 920                                              target_ulong opcode,
 921                                              target_ulong *args)
 922 {
 923     target_ulong flags = args[0];
 924     target_ulong proc_tbl = args[1];
 925     target_ulong page_size = args[2];
 926     target_ulong table_size = args[3];
 927     target_ulong update_lpcr = 0;
 928     target_ulong table_byte_size;
 929     uint64_t cproc;
 930
 931     if (flags & ~FLAGS_MASK) { /* Check no reserved bits are set */
 932         return H_PARAMETER;
 933     }
 934     if (flags & FLAG_MODIFY) {
 935         if (flags & FLAG_REGISTER) {
 936             /* Check process table alignment */
 937             table_byte_size = 1ULL << (table_size + 12);
 938             if (proc_tbl & (table_byte_size - 1)) {
 939                 qemu_log_mask(LOG_GUEST_ERROR,
 940                     "%s: process table not properly aligned: proc_tbl 0x"
 941                     TARGET_FMT_lx" proc_tbl_size 0x"TARGET_FMT_lx"\n",
 942                     __func__, proc_tbl, table_byte_size);
 943             }
 944             if (flags & FLAG_RADIX) { /* Register new RADIX process table */
 945                 if (proc_tbl & 0xfff || proc_tbl >> 60) {
 946                     return H_P2;
 947                 } else if (page_size) {
 948                     return H_P3;
 949                 } else if (table_size > 24) {
 950                     return H_P4;
 951                 }
 952                 cproc = PATE1_GR | proc_tbl | table_size;
 953             } else { /* Register new HPT process table */
 954                 if (flags & FLAG_HASH_PROC_TBL) { /* Hash with Segment Tables */
 955                     /* TODO - Not Supported */
 956                     /* Technically caused by flag bits => H_PARAMETER */
 957                     return H_PARAMETER;
 958                 } else { /* Hash with SLB */
 959                     if (proc_tbl >> 38) {
 960                         return H_P2;
 961                     } else if (page_size & ~0x7) {
 962                         return H_P3;
 963                     } else if (table_size > 24) {
 964                         return H_P4;
 965                     }
 966                 }
 967                 cproc = (proc_tbl << 25) | page_size << 5 | table_size;
 968             }
 969
 970         } else { /* Deregister current process table */
 971             /*
 972              * Set to benign value: (current GR) | 0. This allows
 973              * deregistration in KVM to succeed even if the radix bit
 974              * in flags doesn't match the radix bit in the old PATE.
 975              */
 976             cproc = spapr->patb_entry & PATE1_GR;
 977         }
 978     } else { /* Maintain current registration */
 979         if (!(flags & FLAG_RADIX) != !(spapr->patb_entry & PATE1_GR)) {
 980             /* Technically caused by flag bits => H_PARAMETER */
 981             return H_PARAMETER; /* Existing Process Table Mismatch */
 982         }
 983         cproc = spapr->patb_entry;
 984     }
 985
 986     /* Check if we need to setup OR free the hpt */
 987     spapr_check_setup_free_hpt(spapr, spapr->patb_entry, cproc);
 988
 989     spapr->patb_entry = cproc; /* Save new process table */
 990
 991     /* Update the UPRT, HR and GTSE bits in the LPCR for all cpus */
 992     if (flags & FLAG_RADIX)     /* Radix must use process tables, also set HR */
 993         update_lpcr |= (LPCR_UPRT | LPCR_HR);
 994     else if (flags & FLAG_HASH_PROC_TBL) /* Hash with process tables */
 995         update_lpcr |= LPCR_UPRT;
 996     if (flags & FLAG_GTSE)      /* Guest translation shootdown enable */
 997         update_lpcr |= LPCR_GTSE;
 998
 999     spapr_set_all_lpcrs(update_lpcr, LPCR_UPRT | LPCR_HR | LPCR_GTSE);
1000
1001     if (kvm_enabled()) {
1002         return kvmppc_configure_v3_mmu(cpu, flags & FLAG_RADIX,
1003                                        flags & FLAG_GTSE, cproc);
1004     }
1005     return H_SUCCESS;
1006 }
1007
1008 #define H_SIGNAL_SYS_RESET_ALL         -1
1009 #define H_SIGNAL_SYS_RESET_ALLBUTSELF  -2
1010
1011 static target_ulong h_signal_sys_reset(PowerPCCPU *cpu,
1012                                        SpaprMachineState *spapr,
1013                                        target_ulong opcode, target_ulong *args)
1014 {
1015     target_long target = args[0];
1016     CPUState *cs;
1017
1018     if (target < 0) {
1019         /* Broadcast */
1020         if (target < H_SIGNAL_SYS_RESET_ALLBUTSELF) {
1021             return H_PARAMETER;
1022         }
1023
1024         CPU_FOREACH(cs) {
1025             PowerPCCPU *c = POWERPC_CPU(cs);
1026
1027             if (target == H_SIGNAL_SYS_RESET_ALLBUTSELF) {
1028                 if (c == cpu) {
1029                     continue;
1030                 }
1031             }
1032             run_on_cpu(cs, spapr_do_system_reset_on_cpu, RUN_ON_CPU_NULL);
1033         }
1034         return H_SUCCESS;
1035
1036     } else {
1037         /* Unicast */
1038         cs = CPU(spapr_find_cpu(target));
1039         if (cs) {
1040             run_on_cpu(cs, spapr_do_system_reset_on_cpu, RUN_ON_CPU_NULL);
1041             return H_SUCCESS;
1042         }
1043         return H_PARAMETER;
1044     }
1045 }
1046
1047 /* Returns either a logical PVR or zero if none was found */
1048 static uint32_t cas_check_pvr(PowerPCCPU *cpu, uint32_t max_compat,
1049                               target_ulong *addr, bool *raw_mode_supported)
1050 {
1051     bool explicit_match = false; /* Matched the CPU's real PVR */
1052     uint32_t best_compat = 0;
1053     int i;
1054
1055     /*
1056      * We scan the supplied table of PVRs looking for two things
1057      *   1. Is our real CPU PVR in the list?
1058      *   2. What's the "best" listed logical PVR
1059      */
1060     for (i = 0; i < 512; ++i) {
1061         uint32_t pvr, pvr_mask;
1062
1063         pvr_mask = ldl_be_phys(&address_space_memory, *addr);
1064         pvr = ldl_be_phys(&address_space_memory, *addr + 4);
1065         *addr += 8;
1066
1067         if (~pvr_mask & pvr) {
1068             break; /* Terminator record */
1069         }
1070
1071         if ((cpu->env.spr[SPR_PVR] & pvr_mask) == (pvr & pvr_mask)) {
1072             explicit_match = true;
1073         } else {
1074             if (ppc_check_compat(cpu, pvr, best_compat, max_compat)) {
1075                 best_compat = pvr;
1076             }
1077         }
1078     }
1079
1080     *raw_mode_supported = explicit_match;
1081
1082     /* Parsing finished */
1083     trace_spapr_cas_pvr(cpu->compat_pvr, explicit_match, best_compat);
1084
1085     return best_compat;
1086 }
1087
1088 static
1089 target_ulong do_client_architecture_support(PowerPCCPU *cpu,
1090                                             SpaprMachineState *spapr,
1091                                             target_ulong vec,
1092                                             target_ulong fdt_bufsize)
1093 {
1094     target_ulong ov_table; /* Working address in data buffer */
1095     uint32_t cas_pvr;
1096     SpaprOptionVector *ov1_guest, *ov5_guest;
1097     bool guest_radix;
1098     bool raw_mode_supported = false;
1099     bool guest_xive;
1100     CPUState *cs;
1101     void *fdt;
1102     uint32_t max_compat = spapr->max_compat_pvr;
1103
1104     /* CAS is supposed to be called early when only the boot vCPU is active. */
1105     CPU_FOREACH(cs) {
1106         if (cs == CPU(cpu)) {
1107             continue;
1108         }
1109         if (!cs->halted) {
1110             warn_report("guest has multiple active vCPUs at CAS, which is not allowed");
1111             return H_MULTI_THREADS_ACTIVE;
1112         }
1113     }
1114
1115     cas_pvr = cas_check_pvr(cpu, max_compat, &vec, &raw_mode_supported);
1116     if (!cas_pvr && (!raw_mode_supported || max_compat)) {
1117         /*
1118          * We couldn't find a suitable compatibility mode, and either
1119          * the guest doesn't support "raw" mode for this CPU, or "raw"
1120          * mode is disabled because a maximum compat mode is set.
1121          */
1122         error_report("Couldn't negotiate a suitable PVR during CAS");
1123         return H_HARDWARE;
1124     }
1125
1126     /* Update CPUs */
1127     if (cpu->compat_pvr != cas_pvr) {
1128         Error *local_err = NULL;
1129
1130         if (ppc_set_compat_all(cas_pvr, &local_err) < 0) {
1131             /* We fail to set compat mode (likely because running with KVM PR),
1132              * but maybe we can fallback to raw mode if the guest supports it.
1133              */
1134             if (!raw_mode_supported) {
1135                 error_report_err(local_err);
1136                 return H_HARDWARE;
1137             }
1138             error_free(local_err);
1139         }
1140     }
1141
1142     /* For the future use: here @ov_table points to the first option vector */
1143     ov_table = vec;
1144
1145     ov1_guest = spapr_ovec_parse_vector(ov_table, 1);
1146     if (!ov1_guest) {
1147         warn_report("guest didn't provide option vector 1");
1148         return H_PARAMETER;
1149     }
1150     ov5_guest = spapr_ovec_parse_vector(ov_table, 5);
1151     if (!ov5_guest) {
1152         spapr_ovec_cleanup(ov1_guest);
1153         warn_report("guest didn't provide option vector 5");
1154         return H_PARAMETER;
1155     }
1156     if (spapr_ovec_test(ov5_guest, OV5_MMU_BOTH)) {
1157         error_report("guest requested hash and radix MMU, which is invalid.");
1158         exit(EXIT_FAILURE);
1159     }
1160     if (spapr_ovec_test(ov5_guest, OV5_XIVE_BOTH)) {
1161         error_report("guest requested an invalid interrupt mode");
1162         exit(EXIT_FAILURE);
1163     }
1164
1165     guest_radix = spapr_ovec_test(ov5_guest, OV5_MMU_RADIX_300);
1166
1167     guest_xive = spapr_ovec_test(ov5_guest, OV5_XIVE_EXPLOIT);
1168
1169     /*
1170      * HPT resizing is a bit of a special case, because when enabled
1171      * we assume an HPT guest will support it until it says it
1172      * doesn't, instead of assuming it won't support it until it says
1173      * it does.  Strictly speaking that approach could break for
1174      * guests which don't make a CAS call, but those are so old we
1175      * don't care about them.  Without that assumption we'd have to
1176      * make at least a temporary allocation of an HPT sized for max
1177      * memory, which could be impossibly difficult under KVM HV if
1178      * maxram is large.
1179      */
1180     if (!guest_radix && !spapr_ovec_test(ov5_guest, OV5_HPT_RESIZE)) {
1181         int maxshift = spapr_hpt_shift_for_ramsize(MACHINE(spapr)->maxram_size);
1182
1183         if (spapr->resize_hpt == SPAPR_RESIZE_HPT_REQUIRED) {
1184             error_report(
1185                 "h_client_architecture_support: Guest doesn't support HPT resizing, but resize-hpt=required");
1186             exit(1);
1187         }
1188
1189         if (spapr->htab_shift < maxshift) {
1190             /* Guest doesn't know about HPT resizing, so we
1191              * pre-emptively resize for the maximum permitted RAM.  At
1192              * the point this is called, nothing should have been
1193              * entered into the existing HPT */
1194             spapr_reallocate_hpt(spapr, maxshift, &error_fatal);
1195             push_sregs_to_kvm_pr(spapr);
1196         }
1197     }
1198
1199     /* NOTE: there are actually a number of ov5 bits where input from the
1200      * guest is always zero, and the platform/QEMU enables them independently
1201      * of guest input. To model these properly we'd want some sort of mask,
1202      * but since they only currently apply to memory migration as defined
1203      * by LoPAPR 1.1, 14.5.4.8, which QEMU doesn't implement, we don't need
1204      * to worry about this for now.
1205      */
1206
1207     /* full range of negotiated ov5 capabilities */
1208     spapr_ovec_intersect(spapr->ov5_cas, spapr->ov5, ov5_guest);
1209     spapr_ovec_cleanup(ov5_guest);
1210
1211     spapr_check_mmu_mode(guest_radix);
1212
1213     spapr->cas_pre_isa3_guest = !spapr_ovec_test(ov1_guest, OV1_PPC_3_00);
1214     spapr_ovec_cleanup(ov1_guest);
1215
1216     /*
1217      * Check for NUMA affinity conditions now that we know which NUMA
1218      * affinity the guest will use.
1219      */
1220     spapr_numa_associativity_check(spapr);
1221
1222     /*
1223      * Ensure the guest asks for an interrupt mode we support;
1224      * otherwise terminate the boot.
1225      */
1226     if (guest_xive) {
1227         if (!spapr->irq->xive) {
1228             error_report(
1229 "Guest requested unavailable interrupt mode (XIVE), try the ic-mode=xive or ic-mode=dual machine property");
1230             exit(EXIT_FAILURE);
1231         }
1232     } else {
1233         if (!spapr->irq->xics) {
1234             error_report(
1235 "Guest requested unavailable interrupt mode (XICS), either don't set the ic-mode machine property or try ic-mode=xics or ic-mode=dual");
1236             exit(EXIT_FAILURE);
1237         }
1238     }
1239
1240     spapr_irq_update_active_intc(spapr);
1241
1242     /*
1243      * Process all pending hot-plug/unplug requests now. An updated full
1244      * rendered FDT will be returned to the guest.
1245      */
1246     spapr_drc_reset_all(spapr);
1247     spapr_clear_pending_hotplug_events(spapr);
1248
1249     /*
1250      * If spapr_machine_reset() did not set up a HPT but one is necessary
1251      * (because the guest isn't going to use radix) then set it up here.
1252      */
1253     if ((spapr->patb_entry & PATE1_GR) && !guest_radix) {
1254         /* legacy hash or new hash: */
1255         spapr_setup_hpt(spapr);
1256     }
1257
1258     fdt = spapr_build_fdt(spapr, spapr->vof != NULL, fdt_bufsize);
1259     g_free(spapr->fdt_blob);
1260     spapr->fdt_size = fdt_totalsize(fdt);
1261     spapr->fdt_initial_size = spapr->fdt_size;
1262     spapr->fdt_blob = fdt;
1263
1264     /*
1265      * Set the machine->fdt pointer again since we just freed
1266      * it above (by freeing spapr->fdt_blob). We set this
1267      * pointer to enable support for the 'dumpdtb' QMP/HMP
1268      * command.
1269      */
1270     MACHINE(spapr)->fdt = fdt;
1271
1272     return H_SUCCESS;
1273 }
1274
1275 static target_ulong h_client_architecture_support(PowerPCCPU *cpu,
1276                                                   SpaprMachineState *spapr,
1277                                                   target_ulong opcode,
1278                                                   target_ulong *args)
1279 {
1280     target_ulong vec = ppc64_phys_to_real(args[0]);
1281     target_ulong fdt_buf = args[1];
1282     target_ulong fdt_bufsize = args[2];
1283     target_ulong ret;
1284     SpaprDeviceTreeUpdateHeader hdr = { .version_id = 1 };
1285
1286     if (fdt_bufsize < sizeof(hdr)) {
1287         error_report("SLOF provided insufficient CAS buffer "
1288                      TARGET_FMT_lu " (min: %zu)", fdt_bufsize, sizeof(hdr));
1289         exit(EXIT_FAILURE);
1290     }
1291
1292     fdt_bufsize -= sizeof(hdr);
1293
1294     ret = do_client_architecture_support(cpu, spapr, vec, fdt_bufsize);
1295     if (ret == H_SUCCESS) {
1296         _FDT((fdt_pack(spapr->fdt_blob)));
1297         spapr->fdt_size = fdt_totalsize(spapr->fdt_blob);
1298         spapr->fdt_initial_size = spapr->fdt_size;
1299
1300         cpu_physical_memory_write(fdt_buf, &hdr, sizeof(hdr));
1301         cpu_physical_memory_write(fdt_buf + sizeof(hdr), spapr->fdt_blob,
1302                                   spapr->fdt_size);
1303         trace_spapr_cas_continue(spapr->fdt_size + sizeof(hdr));
1304     }
1305
1306     return ret;
1307 }
1308
1309 target_ulong spapr_vof_client_architecture_support(MachineState *ms,
1310                                                    CPUState *cs,
1311                                                    target_ulong ovec_addr)
1312 {
1313     SpaprMachineState *spapr = SPAPR_MACHINE(ms);
1314
1315     target_ulong ret = do_client_architecture_support(POWERPC_CPU(cs), spapr,
1316                                                       ovec_addr, FDT_MAX_SIZE);
1317
1318     /*
1319      * This adds stdout and generates phandles for boottime and CAS FDTs.
1320      * It is alright to update the FDT here as do_client_architecture_support()
1321      * does not pack it.
1322      */
1323     spapr_vof_client_dt_finalize(spapr, spapr->fdt_blob);
1324
1325     return ret;
1326 }
1327
1328 static target_ulong h_get_cpu_characteristics(PowerPCCPU *cpu,
1329                                               SpaprMachineState *spapr,
1330                                               target_ulong opcode,
1331                                               target_ulong *args)
1332 {
1333     uint64_t characteristics = H_CPU_CHAR_HON_BRANCH_HINTS &
1334                                ~H_CPU_CHAR_THR_RECONF_TRIG;
1335     uint64_t behaviour = H_CPU_BEHAV_FAVOUR_SECURITY;
1336     uint8_t safe_cache = spapr_get_cap(spapr, SPAPR_CAP_CFPC);
1337     uint8_t safe_bounds_check = spapr_get_cap(spapr, SPAPR_CAP_SBBC);
1338     uint8_t safe_indirect_branch = spapr_get_cap(spapr, SPAPR_CAP_IBS);
1339     uint8_t count_cache_flush_assist = spapr_get_cap(spapr,
1340                                                      SPAPR_CAP_CCF_ASSIST);
1341
1342     switch (safe_cache) {
1343     case SPAPR_CAP_WORKAROUND:
1344         characteristics |= H_CPU_CHAR_L1D_FLUSH_ORI30;
1345         characteristics |= H_CPU_CHAR_L1D_FLUSH_TRIG2;
1346         characteristics |= H_CPU_CHAR_L1D_THREAD_PRIV;
1347         behaviour |= H_CPU_BEHAV_L1D_FLUSH_PR;
1348         break;
1349     case SPAPR_CAP_FIXED:
1350         behaviour |= H_CPU_BEHAV_NO_L1D_FLUSH_ENTRY;
1351         behaviour |= H_CPU_BEHAV_NO_L1D_FLUSH_UACCESS;
1352         break;
1353     default: /* broken */
1354         assert(safe_cache == SPAPR_CAP_BROKEN);
1355         behaviour |= H_CPU_BEHAV_L1D_FLUSH_PR;
1356         break;
1357     }
1358
1359     switch (safe_bounds_check) {
1360     case SPAPR_CAP_WORKAROUND:
1361         characteristics |= H_CPU_CHAR_SPEC_BAR_ORI31;
1362         behaviour |= H_CPU_BEHAV_BNDS_CHK_SPEC_BAR;
1363         break;
1364     case SPAPR_CAP_FIXED:
1365         break;
1366     default: /* broken */
1367         assert(safe_bounds_check == SPAPR_CAP_BROKEN);
1368         behaviour |= H_CPU_BEHAV_BNDS_CHK_SPEC_BAR;
1369         break;
1370     }
1371
1372     switch (safe_indirect_branch) {
1373     case SPAPR_CAP_FIXED_NA:
1374         break;
1375     case SPAPR_CAP_FIXED_CCD:
1376         characteristics |= H_CPU_CHAR_CACHE_COUNT_DIS;
1377         break;
1378     case SPAPR_CAP_FIXED_IBS:
1379         characteristics |= H_CPU_CHAR_BCCTRL_SERIALISED;
1380         break;
1381     case SPAPR_CAP_WORKAROUND:
1382         behaviour |= H_CPU_BEHAV_FLUSH_COUNT_CACHE;
1383         if (count_cache_flush_assist) {
1384             characteristics |= H_CPU_CHAR_BCCTR_FLUSH_ASSIST;
1385         }
1386         break;
1387     default: /* broken */
1388         assert(safe_indirect_branch == SPAPR_CAP_BROKEN);
1389         break;
1390     }
1391
1392     args[0] = characteristics;
1393     args[1] = behaviour;
1394     return H_SUCCESS;
1395 }
1396
1397 static target_ulong h_update_dt(PowerPCCPU *cpu, SpaprMachineState *spapr,
1398                                 target_ulong opcode, target_ulong *args)
1399 {
1400     target_ulong dt = ppc64_phys_to_real(args[0]);
1401     struct fdt_header hdr = { 0 };
1402     unsigned cb;
1403     SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr);
1404     void *fdt;
1405
1406     cpu_physical_memory_read(dt, &hdr, sizeof(hdr));
1407     cb = fdt32_to_cpu(hdr.totalsize);
1408
1409     if (!smc->update_dt_enabled) {
1410         return H_SUCCESS;
1411     }
1412
1413     /* Check that the fdt did not grow out of proportion */
1414     if (cb > spapr->fdt_initial_size * 2) {
1415         trace_spapr_update_dt_failed_size(spapr->fdt_initial_size, cb,
1416                                           fdt32_to_cpu(hdr.magic));
1417         return H_PARAMETER;
1418     }
1419
1420     fdt = g_malloc0(cb);
1421     cpu_physical_memory_read(dt, fdt, cb);
1422
1423     /* Check the fdt consistency */
1424     if (fdt_check_full(fdt, cb)) {
1425         trace_spapr_update_dt_failed_check(spapr->fdt_initial_size, cb,
1426                                            fdt32_to_cpu(hdr.magic));
1427         return H_PARAMETER;
1428     }
1429
1430     g_free(spapr->fdt_blob);
1431     spapr->fdt_size = cb;
1432     spapr->fdt_blob = fdt;
1433     trace_spapr_update_dt(cb);
1434
1435     return H_SUCCESS;
1436 }
1437
1438 static spapr_hcall_fn papr_hypercall_table[(MAX_HCALL_OPCODE / 4) + 1];
1439 static spapr_hcall_fn kvmppc_hypercall_table[KVMPPC_HCALL_MAX - KVMPPC_HCALL_BASE + 1];
1440 static spapr_hcall_fn svm_hypercall_table[(SVM_HCALL_MAX - SVM_HCALL_BASE) / 4 + 1];
1441
1442 void spapr_register_hypercall(target_ulong opcode, spapr_hcall_fn fn)
1443 {
1444     spapr_hcall_fn *slot;
1445
1446     if (opcode <= MAX_HCALL_OPCODE) {
1447         assert((opcode & 0x3) == 0);
1448
1449         slot = &papr_hypercall_table[opcode / 4];
1450     } else if (opcode >= SVM_HCALL_BASE && opcode <= SVM_HCALL_MAX) {
1451         /* we only have SVM-related hcall numbers assigned in multiples of 4 */
1452         assert((opcode & 0x3) == 0);
1453
1454         slot = &svm_hypercall_table[(opcode - SVM_HCALL_BASE) / 4];
1455     } else {
1456         assert((opcode >= KVMPPC_HCALL_BASE) && (opcode <= KVMPPC_HCALL_MAX));
1457
1458         slot = &kvmppc_hypercall_table[opcode - KVMPPC_HCALL_BASE];
1459     }
1460
1461     assert(!(*slot));
1462     *slot = fn;
1463 }
1464
1465 target_ulong spapr_hypercall(PowerPCCPU *cpu, target_ulong opcode,
1466                              target_ulong *args)
1467 {
1468     SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine());
1469
1470     if ((opcode <= MAX_HCALL_OPCODE)
1471         && ((opcode & 0x3) == 0)) {
1472         spapr_hcall_fn fn = papr_hypercall_table[opcode / 4];
1473
1474         if (fn) {
1475             return fn(cpu, spapr, opcode, args);
1476         }
1477     } else if ((opcode >= SVM_HCALL_BASE) &&
1478                (opcode <= SVM_HCALL_MAX)) {
1479         spapr_hcall_fn fn = svm_hypercall_table[(opcode - SVM_HCALL_BASE) / 4];
1480
1481         if (fn) {
1482             return fn(cpu, spapr, opcode, args);
1483         }
1484     } else if ((opcode >= KVMPPC_HCALL_BASE) &&
1485                (opcode <= KVMPPC_HCALL_MAX)) {
1486         spapr_hcall_fn fn = kvmppc_hypercall_table[opcode - KVMPPC_HCALL_BASE];
1487
1488         if (fn) {
1489             return fn(cpu, spapr, opcode, args);
1490         }
1491     }
1492
1493     qemu_log_mask(LOG_UNIMP, "Unimplemented SPAPR hcall 0x" TARGET_FMT_lx "\n",
1494                   opcode);
1495     return H_FUNCTION;
1496 }
1497
1498 #ifdef CONFIG_TCG
1499 #define PRTS_MASK      0x1f
1500
1501 static target_ulong h_set_ptbl(PowerPCCPU *cpu,
1502                                SpaprMachineState *spapr,
1503                                target_ulong opcode,
1504                                target_ulong *args)
1505 {
1506     target_ulong ptcr = args[0];
1507
1508     if (!spapr_get_cap(spapr, SPAPR_CAP_NESTED_KVM_HV)) {
1509         return H_FUNCTION;
1510     }
1511
1512     if ((ptcr & PRTS_MASK) + 12 - 4 > 12) {
1513         return H_PARAMETER;
1514     }
1515
1516     spapr->nested_ptcr = ptcr; /* Save new partition table */
1517
1518     return H_SUCCESS;
1519 }
1520
1521 static target_ulong h_tlb_invalidate(PowerPCCPU *cpu,
1522                                      SpaprMachineState *spapr,
1523                                      target_ulong opcode,
1524                                      target_ulong *args)
1525 {
1526     /*
1527      * The spapr virtual hypervisor nested HV implementation retains no L2
1528      * translation state except for TLB. And the TLB is always invalidated
1529      * across L1<->L2 transitions, so nothing is required here.
1530      */
1531
1532     return H_SUCCESS;
1533 }
1534
1535 static target_ulong h_copy_tofrom_guest(PowerPCCPU *cpu,
1536                                         SpaprMachineState *spapr,
1537                                         target_ulong opcode,
1538                                         target_ulong *args)
1539 {
1540     /*
1541      * This HCALL is not required, L1 KVM will take a slow path and walk the
1542      * page tables manually to do the data copy.
1543      */
1544     return H_FUNCTION;
1545 }
1546
1547 /*
1548  * When this handler returns, the environment is switched to the L2 guest
1549  * and TCG begins running that. spapr_exit_nested() performs the switch from
1550  * L2 back to L1 and returns from the H_ENTER_NESTED hcall.
1551  */
1552 static target_ulong h_enter_nested(PowerPCCPU *cpu,
1553                                    SpaprMachineState *spapr,
1554                                    target_ulong opcode,
1555                                    target_ulong *args)
1556 {
1557     PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
1558     CPUState *cs = CPU(cpu);
1559     CPUPPCState *env = &cpu->env;
1560     SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu);
1561     target_ulong hv_ptr = args[0];
1562     target_ulong regs_ptr = args[1];
1563     target_ulong hdec, now = cpu_ppc_load_tbl(env);
1564     target_ulong lpcr, lpcr_mask;
1565     struct kvmppc_hv_guest_state *hvstate;
1566     struct kvmppc_hv_guest_state hv_state;
1567     struct kvmppc_pt_regs *regs;
1568     hwaddr len;
1569     uint64_t cr;
1570     int i;
1571
1572     if (spapr->nested_ptcr == 0) {
1573         return H_NOT_AVAILABLE;
1574     }
1575
1576     len = sizeof(*hvstate);
1577     hvstate = address_space_map(CPU(cpu)->as, hv_ptr, &len, false,
1578                                 MEMTXATTRS_UNSPECIFIED);
1579     if (len != sizeof(*hvstate)) {
1580         address_space_unmap(CPU(cpu)->as, hvstate, len, 0, false);
1581         return H_PARAMETER;
1582     }
1583
1584     memcpy(&hv_state, hvstate, len);
1585
1586     address_space_unmap(CPU(cpu)->as, hvstate, len, len, false);
1587
1588     /*
1589      * We accept versions 1 and 2. Version 2 fields are unused because TCG
1590      * does not implement DAWR*.
1591      */
1592     if (hv_state.version > HV_GUEST_STATE_VERSION) {
1593         return H_PARAMETER;
1594     }
1595
1596     spapr_cpu->nested_host_state = g_try_new(CPUPPCState, 1);
1597     if (!spapr_cpu->nested_host_state) {
1598         return H_NO_MEM;
1599     }
1600
1601     memcpy(spapr_cpu->nested_host_state, env, sizeof(CPUPPCState));
1602
1603     len = sizeof(*regs);
1604     regs = address_space_map(CPU(cpu)->as, regs_ptr, &len, false,
1605                                 MEMTXATTRS_UNSPECIFIED);
1606     if (!regs || len != sizeof(*regs)) {
1607         address_space_unmap(CPU(cpu)->as, regs, len, 0, false);
1608         g_free(spapr_cpu->nested_host_state);
1609         return H_P2;
1610     }
1611
1612     len = sizeof(env->gpr);
1613     assert(len == sizeof(regs->gpr));
1614     memcpy(env->gpr, regs->gpr, len);
1615
1616     env->lr = regs->link;
1617     env->ctr = regs->ctr;
1618     cpu_write_xer(env, regs->xer);
1619
1620     cr = regs->ccr;
1621     for (i = 7; i >= 0; i--) {
1622         env->crf[i] = cr & 15;
1623         cr >>= 4;
1624     }
1625
1626     env->msr = regs->msr;
1627     env->nip = regs->nip;
1628
1629     address_space_unmap(CPU(cpu)->as, regs, len, len, false);
1630
1631     env->cfar = hv_state.cfar;
1632
1633     assert(env->spr[SPR_LPIDR] == 0);
1634     env->spr[SPR_LPIDR] = hv_state.lpid;
1635
1636     lpcr_mask = LPCR_DPFD | LPCR_ILE | LPCR_AIL | LPCR_LD | LPCR_MER;
1637     lpcr = (env->spr[SPR_LPCR] & ~lpcr_mask) | (hv_state.lpcr & lpcr_mask);
1638     lpcr |= LPCR_HR | LPCR_UPRT | LPCR_GTSE | LPCR_HVICE | LPCR_HDICE;
1639     lpcr &= ~LPCR_LPES0;
1640     env->spr[SPR_LPCR] = lpcr & pcc->lpcr_mask;
1641
1642     env->spr[SPR_PCR] = hv_state.pcr;
1643     /* hv_state.amor is not used */
1644     env->spr[SPR_DPDES] = hv_state.dpdes;
1645     env->spr[SPR_HFSCR] = hv_state.hfscr;
1646     hdec = hv_state.hdec_expiry - now;
1647     spapr_cpu->nested_tb_offset = hv_state.tb_offset;
1648     /* TCG does not implement DAWR*, CIABR, PURR, SPURR, IC, VTB, HEIR SPRs*/
1649     env->spr[SPR_SRR0] = hv_state.srr0;
1650     env->spr[SPR_SRR1] = hv_state.srr1;
1651     env->spr[SPR_SPRG0] = hv_state.sprg[0];
1652     env->spr[SPR_SPRG1] = hv_state.sprg[1];
1653     env->spr[SPR_SPRG2] = hv_state.sprg[2];
1654     env->spr[SPR_SPRG3] = hv_state.sprg[3];
1655     env->spr[SPR_BOOKS_PID] = hv_state.pidr;
1656     env->spr[SPR_PPR] = hv_state.ppr;
1657
1658     cpu_ppc_hdecr_init(env);
1659     cpu_ppc_store_hdecr(env, hdec);
1660
1661     /*
1662      * The hv_state.vcpu_token is not needed. It is used by the KVM
1663      * implementation to remember which L2 vCPU last ran on which physical
1664      * CPU so as to invalidate process scope translations if it is moved
1665      * between physical CPUs. For now TLBs are always flushed on L1<->L2
1666      * transitions so this is not a problem.
1667      *
1668      * Could validate that the same vcpu_token does not attempt to run on
1669      * different L1 vCPUs at the same time, but that would be a L1 KVM bug
1670      * and it's not obviously worth a new data structure to do it.
1671      */
1672
1673     env->tb_env->tb_offset += spapr_cpu->nested_tb_offset;
1674     spapr_cpu->in_nested = true;
1675
1676     hreg_compute_hflags(env);
1677     ppc_maybe_interrupt(env);
1678     tlb_flush(cs);
1679     env->reserve_addr = -1; /* Reset the reservation */
1680
1681     /*
1682      * The spapr hcall helper sets env->gpr[3] to the return value, but at
1683      * this point the L1 is not returning from the hcall but rather we
1684      * start running the L2, so r3 must not be clobbered, so return env->gpr[3]
1685      * to leave it unchanged.
1686      */
1687     return env->gpr[3];
1688 }
1689
1690 void spapr_exit_nested(PowerPCCPU *cpu, int excp)
1691 {
1692     CPUState *cs = CPU(cpu);
1693     CPUPPCState *env = &cpu->env;
1694     SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu);
1695     target_ulong r3_return = env->excp_vectors[excp]; /* hcall return value */
1696     target_ulong hv_ptr = spapr_cpu->nested_host_state->gpr[4];
1697     target_ulong regs_ptr = spapr_cpu->nested_host_state->gpr[5];
1698     struct kvmppc_hv_guest_state *hvstate;
1699     struct kvmppc_pt_regs *regs;
1700     hwaddr len;
1701     uint64_t cr;
1702     int i;
1703
1704     assert(spapr_cpu->in_nested);
1705
1706     cpu_ppc_hdecr_exit(env);
1707
1708     len = sizeof(*hvstate);
1709     hvstate = address_space_map(CPU(cpu)->as, hv_ptr, &len, true,
1710                                 MEMTXATTRS_UNSPECIFIED);
1711     if (len != sizeof(*hvstate)) {
1712         address_space_unmap(CPU(cpu)->as, hvstate, len, 0, true);
1713         r3_return = H_PARAMETER;
1714         goto out_restore_l1;
1715     }
1716
1717     hvstate->cfar = env->cfar;
1718     hvstate->lpcr = env->spr[SPR_LPCR];
1719     hvstate->pcr = env->spr[SPR_PCR];
1720     hvstate->dpdes = env->spr[SPR_DPDES];
1721     hvstate->hfscr = env->spr[SPR_HFSCR];
1722
1723     if (excp == POWERPC_EXCP_HDSI) {
1724         hvstate->hdar = env->spr[SPR_HDAR];
1725         hvstate->hdsisr = env->spr[SPR_HDSISR];
1726         hvstate->asdr = env->spr[SPR_ASDR];
1727     } else if (excp == POWERPC_EXCP_HISI) {
1728         hvstate->asdr = env->spr[SPR_ASDR];
1729     }
1730
1731     /* HEIR should be implemented for HV mode and saved here. */
1732     hvstate->srr0 = env->spr[SPR_SRR0];
1733     hvstate->srr1 = env->spr[SPR_SRR1];
1734     hvstate->sprg[0] = env->spr[SPR_SPRG0];
1735     hvstate->sprg[1] = env->spr[SPR_SPRG1];
1736     hvstate->sprg[2] = env->spr[SPR_SPRG2];
1737     hvstate->sprg[3] = env->spr[SPR_SPRG3];
1738     hvstate->pidr = env->spr[SPR_BOOKS_PID];
1739     hvstate->ppr = env->spr[SPR_PPR];
1740
1741     /* Is it okay to specify write length larger than actual data written? */
1742     address_space_unmap(CPU(cpu)->as, hvstate, len, len, true);
1743
1744     len = sizeof(*regs);
1745     regs = address_space_map(CPU(cpu)->as, regs_ptr, &len, true,
1746                                 MEMTXATTRS_UNSPECIFIED);
1747     if (!regs || len != sizeof(*regs)) {
1748         address_space_unmap(CPU(cpu)->as, regs, len, 0, true);
1749         r3_return = H_P2;
1750         goto out_restore_l1;
1751     }
1752
1753     len = sizeof(env->gpr);
1754     assert(len == sizeof(regs->gpr));
1755     memcpy(regs->gpr, env->gpr, len);
1756
1757     regs->link = env->lr;
1758     regs->ctr = env->ctr;
1759     regs->xer = cpu_read_xer(env);
1760
1761     cr = 0;
1762     for (i = 0; i < 8; i++) {
1763         cr |= (env->crf[i] & 15) << (4 * (7 - i));
1764     }
1765     regs->ccr = cr;
1766
1767     if (excp == POWERPC_EXCP_MCHECK ||
1768         excp == POWERPC_EXCP_RESET ||
1769         excp == POWERPC_EXCP_SYSCALL) {
1770         regs->nip = env->spr[SPR_SRR0];
1771         regs->msr = env->spr[SPR_SRR1] & env->msr_mask;
1772     } else {
1773         regs->nip = env->spr[SPR_HSRR0];
1774         regs->msr = env->spr[SPR_HSRR1] & env->msr_mask;
1775     }
1776
1777     /* Is it okay to specify write length larger than actual data written? */
1778     address_space_unmap(CPU(cpu)->as, regs, len, len, true);
1779
1780 out_restore_l1:
1781     memcpy(env->gpr, spapr_cpu->nested_host_state->gpr, sizeof(env->gpr));
1782     env->lr = spapr_cpu->nested_host_state->lr;
1783     env->ctr = spapr_cpu->nested_host_state->ctr;
1784     memcpy(env->crf, spapr_cpu->nested_host_state->crf, sizeof(env->crf));
1785     env->cfar = spapr_cpu->nested_host_state->cfar;
1786     env->xer = spapr_cpu->nested_host_state->xer;
1787     env->so = spapr_cpu->nested_host_state->so;
1788     env->ov = spapr_cpu->nested_host_state->ov;
1789     env->ov32 = spapr_cpu->nested_host_state->ov32;
1790     env->ca32 = spapr_cpu->nested_host_state->ca32;
1791     env->msr = spapr_cpu->nested_host_state->msr;
1792     env->nip = spapr_cpu->nested_host_state->nip;
1793
1794     assert(env->spr[SPR_LPIDR] != 0);
1795     env->spr[SPR_LPCR] = spapr_cpu->nested_host_state->spr[SPR_LPCR];
1796     env->spr[SPR_LPIDR] = spapr_cpu->nested_host_state->spr[SPR_LPIDR];
1797     env->spr[SPR_PCR] = spapr_cpu->nested_host_state->spr[SPR_PCR];
1798     env->spr[SPR_DPDES] = 0;
1799     env->spr[SPR_HFSCR] = spapr_cpu->nested_host_state->spr[SPR_HFSCR];
1800     env->spr[SPR_SRR0] = spapr_cpu->nested_host_state->spr[SPR_SRR0];
1801     env->spr[SPR_SRR1] = spapr_cpu->nested_host_state->spr[SPR_SRR1];
1802     env->spr[SPR_SPRG0] = spapr_cpu->nested_host_state->spr[SPR_SPRG0];
1803     env->spr[SPR_SPRG1] = spapr_cpu->nested_host_state->spr[SPR_SPRG1];
1804     env->spr[SPR_SPRG2] = spapr_cpu->nested_host_state->spr[SPR_SPRG2];
1805     env->spr[SPR_SPRG3] = spapr_cpu->nested_host_state->spr[SPR_SPRG3];
1806     env->spr[SPR_BOOKS_PID] = spapr_cpu->nested_host_state->spr[SPR_BOOKS_PID];
1807     env->spr[SPR_PPR] = spapr_cpu->nested_host_state->spr[SPR_PPR];
1808
1809     /*
1810      * Return the interrupt vector address from H_ENTER_NESTED to the L1
1811      * (or error code).
1812      */
1813     env->gpr[3] = r3_return;
1814
1815     env->tb_env->tb_offset -= spapr_cpu->nested_tb_offset;
1816     spapr_cpu->in_nested = false;
1817
1818     hreg_compute_hflags(env);
1819     ppc_maybe_interrupt(env);
1820     tlb_flush(cs);
1821     env->reserve_addr = -1; /* Reset the reservation */
1822
1823     g_free(spapr_cpu->nested_host_state);
1824     spapr_cpu->nested_host_state = NULL;
1825 }
1826
1827 static void hypercall_register_nested(void)
1828 {
1829     spapr_register_hypercall(KVMPPC_H_SET_PARTITION_TABLE, h_set_ptbl);
1830     spapr_register_hypercall(KVMPPC_H_ENTER_NESTED, h_enter_nested);
1831     spapr_register_hypercall(KVMPPC_H_TLB_INVALIDATE, h_tlb_invalidate);
1832     spapr_register_hypercall(KVMPPC_H_COPY_TOFROM_GUEST, h_copy_tofrom_guest);
1833 }
1834
1835 static void hypercall_register_softmmu(void)
1836 {
1837     /* DO NOTHING */
1838 }
1839 #else
1840 void spapr_exit_nested(PowerPCCPU *cpu, int excp)
1841 {
1842     g_assert_not_reached();
1843 }
1844
1845 static target_ulong h_softmmu(PowerPCCPU *cpu, SpaprMachineState *spapr,
1846                             target_ulong opcode, target_ulong *args)
1847 {
1848     g_assert_not_reached();
1849 }
1850
1851 static void hypercall_register_nested(void)
1852 {
1853     /* DO NOTHING */
1854 }
1855
1856 static void hypercall_register_softmmu(void)
1857 {
1858     /* hcall-pft */
1859     spapr_register_hypercall(H_ENTER, h_softmmu);
1860     spapr_register_hypercall(H_REMOVE, h_softmmu);
1861     spapr_register_hypercall(H_PROTECT, h_softmmu);
1862     spapr_register_hypercall(H_READ, h_softmmu);
1863
1864     /* hcall-bulk */
1865     spapr_register_hypercall(H_BULK_REMOVE, h_softmmu);
1866 }
1867 #endif
1868
1869 static void hypercall_register_types(void)
1870 {
1871     hypercall_register_softmmu();
1872
1873     /* hcall-hpt-resize */
1874     spapr_register_hypercall(H_RESIZE_HPT_PREPARE, h_resize_hpt_prepare);
1875     spapr_register_hypercall(H_RESIZE_HPT_COMMIT, h_resize_hpt_commit);
1876
1877     /* hcall-splpar */
1878     spapr_register_hypercall(H_REGISTER_VPA, h_register_vpa);
1879     spapr_register_hypercall(H_CEDE, h_cede);
1880     spapr_register_hypercall(H_CONFER, h_confer);
1881     spapr_register_hypercall(H_PROD, h_prod);
1882
1883     /* hcall-join */
1884     spapr_register_hypercall(H_JOIN, h_join);
1885
1886     spapr_register_hypercall(H_SIGNAL_SYS_RESET, h_signal_sys_reset);
1887
1888     /* processor register resource access h-calls */
1889     spapr_register_hypercall(H_SET_SPRG0, h_set_sprg0);
1890     spapr_register_hypercall(H_SET_DABR, h_set_dabr);
1891     spapr_register_hypercall(H_SET_XDABR, h_set_xdabr);
1892     spapr_register_hypercall(H_PAGE_INIT, h_page_init);
1893     spapr_register_hypercall(H_SET_MODE, h_set_mode);
1894
1895     /* In Memory Table MMU h-calls */
1896     spapr_register_hypercall(H_CLEAN_SLB, h_clean_slb);
1897     spapr_register_hypercall(H_INVALIDATE_PID, h_invalidate_pid);
1898     spapr_register_hypercall(H_REGISTER_PROC_TBL, h_register_process_table);
1899
1900     /* hcall-get-cpu-characteristics */
1901     spapr_register_hypercall(H_GET_CPU_CHARACTERISTICS,
1902                              h_get_cpu_characteristics);
1903
1904     /* "debugger" hcalls (also used by SLOF). Note: We do -not- differenciate
1905      * here between the "CI" and the "CACHE" variants, they will use whatever
1906      * mapping attributes qemu is using. When using KVM, the kernel will
1907      * enforce the attributes more strongly
1908      */
1909     spapr_register_hypercall(H_LOGICAL_CI_LOAD, h_logical_load);
1910     spapr_register_hypercall(H_LOGICAL_CI_STORE, h_logical_store);
1911     spapr_register_hypercall(H_LOGICAL_CACHE_LOAD, h_logical_load);
1912     spapr_register_hypercall(H_LOGICAL_CACHE_STORE, h_logical_store);
1913     spapr_register_hypercall(H_LOGICAL_ICBI, h_logical_icbi);
1914     spapr_register_hypercall(H_LOGICAL_DCBF, h_logical_dcbf);
1915     spapr_register_hypercall(KVMPPC_H_LOGICAL_MEMOP, h_logical_memop);
1916
1917     /* qemu/KVM-PPC specific hcalls */
1918     spapr_register_hypercall(KVMPPC_H_RTAS, h_rtas);
1919
1920     /* ibm,client-architecture-support support */
1921     spapr_register_hypercall(KVMPPC_H_CAS, h_client_architecture_support);
1922
1923     spapr_register_hypercall(KVMPPC_H_UPDATE_DT, h_update_dt);
1924
1925     hypercall_register_nested();
1926 }
1927
1928 type_init(hypercall_register_types)