hw/rtc/pl031.c

   1 /*
   2  * ARM AMBA PrimeCell PL031 RTC
   3  *
   4  * Copyright (c) 2007 CodeSourcery
   5  *
   6  * This file is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  *
  10  * Contributions after 2012-01-13 are licensed under the terms of the
  11  * GNU GPL, version 2 or (at your option) any later version.
  12  */
  13
  14 #include "qemu/osdep.h"
  15 #include "hw/rtc/pl031.h"
  16 #include "migration/vmstate.h"
  17 #include "hw/irq.h"
  18 #include "hw/qdev-properties.h"
  19 #include "hw/sysbus.h"
  20 #include "qemu/timer.h"
  21 #include "sysemu/sysemu.h"
  22 #include "sysemu/rtc.h"
  23 #include "qemu/cutils.h"
  24 #include "qemu/log.h"
  25 #include "qemu/module.h"
  26 #include "trace.h"
  27 #include "qapi/qapi-events-misc.h"
  28
  29 #define RTC_DR      0x00    /* Data read register */
  30 #define RTC_MR      0x04    /* Match register */
  31 #define RTC_LR      0x08    /* Data load register */
  32 #define RTC_CR      0x0c    /* Control register */
  33 #define RTC_IMSC    0x10    /* Interrupt mask and set register */
  34 #define RTC_RIS     0x14    /* Raw interrupt status register */
  35 #define RTC_MIS     0x18    /* Masked interrupt status register */
  36 #define RTC_ICR     0x1c    /* Interrupt clear register */
  37
  38 static const unsigned char pl031_id[] = {
  39     0x31, 0x10, 0x14, 0x00,         /* Device ID        */
  40     0x0d, 0xf0, 0x05, 0xb1          /* Cell ID      */
  41 };
  42
  43 static void pl031_update(PL031State *s)
  44 {
  45     uint32_t flags = s->is & s->im;
  46
  47     trace_pl031_irq_state(flags);
  48     qemu_set_irq(s->irq, flags);
  49 }
  50
  51 static void pl031_interrupt(void * opaque)
  52 {
  53     PL031State *s = (PL031State *)opaque;
  54
  55     s->is = 1;
  56     trace_pl031_alarm_raised();
  57     pl031_update(s);
  58 }
  59
  60 static uint32_t pl031_get_count(PL031State *s)
  61 {
  62     int64_t now = qemu_clock_get_ns(rtc_clock);
  63     return s->tick_offset + now / NANOSECONDS_PER_SECOND;
  64 }
  65
  66 static void pl031_set_alarm(PL031State *s)
  67 {
  68     uint32_t ticks;
  69
  70     /* The timer wraps around.  This subtraction also wraps in the same way,
  71        and gives correct results when alarm < now_ticks.  */
  72     ticks = s->mr - pl031_get_count(s);
  73     trace_pl031_set_alarm(ticks);
  74     if (ticks == 0) {
  75         timer_del(s->timer);
  76         pl031_interrupt(s);
  77     } else {
  78         int64_t now = qemu_clock_get_ns(rtc_clock);
  79         timer_mod(s->timer, now + (int64_t)ticks * NANOSECONDS_PER_SECOND);
  80     }
  81 }
  82
  83 static uint64_t pl031_read(void *opaque, hwaddr offset,
  84                            unsigned size)
  85 {
  86     PL031State *s = (PL031State *)opaque;
  87     uint64_t r;
  88
  89     switch (offset) {
  90     case RTC_DR:
  91         r = pl031_get_count(s);
  92         break;
  93     case RTC_MR:
  94         r = s->mr;
  95         break;
  96     case RTC_IMSC:
  97         r = s->im;
  98         break;
  99     case RTC_RIS:
 100         r = s->is;
 101         break;
 102     case RTC_LR:
 103         r = s->lr;
 104         break;
 105     case RTC_CR:
 106         /* RTC is permanently enabled.  */
 107         r = 1;
 108         break;
 109     case RTC_MIS:
 110         r = s->is & s->im;
 111         break;
 112     case 0xfe0 ... 0xfff:
 113         r = pl031_id[(offset - 0xfe0) >> 2];
 114         break;
 115     case RTC_ICR:
 116         qemu_log_mask(LOG_GUEST_ERROR,
 117                       "pl031: read of write-only register at offset 0x%x\n",
 118                       (int)offset);
 119         r = 0;
 120         break;
 121     default:
 122         qemu_log_mask(LOG_GUEST_ERROR,
 123                       "pl031_read: Bad offset 0x%x\n", (int)offset);
 124         r = 0;
 125         break;
 126     }
 127
 128     trace_pl031_read(offset, r);
 129     return r;
 130 }
 131
 132 static void pl031_write(void * opaque, hwaddr offset,
 133                         uint64_t value, unsigned size)
 134 {
 135     PL031State *s = (PL031State *)opaque;
 136
 137     trace_pl031_write(offset, value);
 138
 139     switch (offset) {
 140     case RTC_LR: {
 141         g_autofree const char *qom_path = object_get_canonical_path(opaque);
 142         struct tm tm;
 143
 144         s->tick_offset += value - pl031_get_count(s);
 145
 146         qemu_get_timedate(&tm, s->tick_offset);
 147         qapi_event_send_rtc_change(qemu_timedate_diff(&tm), qom_path);
 148
 149         pl031_set_alarm(s);
 150         break;
 151     }
 152     case RTC_MR:
 153         s->mr = value;
 154         pl031_set_alarm(s);
 155         break;
 156     case RTC_IMSC:
 157         s->im = value & 1;
 158         pl031_update(s);
 159         break;
 160     case RTC_ICR:
 161         s->is &= ~value;
 162         pl031_update(s);
 163         break;
 164     case RTC_CR:
 165         /* Written value is ignored.  */
 166         break;
 167
 168     case RTC_DR:
 169     case RTC_MIS:
 170     case RTC_RIS:
 171         qemu_log_mask(LOG_GUEST_ERROR,
 172                       "pl031: write to read-only register at offset 0x%x\n",
 173                       (int)offset);
 174         break;
 175
 176     default:
 177         qemu_log_mask(LOG_GUEST_ERROR,
 178                       "pl031_write: Bad offset 0x%x\n", (int)offset);
 179         break;
 180     }
 181 }
 182
 183 static const MemoryRegionOps pl031_ops = {
 184     .read = pl031_read,
 185     .write = pl031_write,
 186     .endianness = DEVICE_NATIVE_ENDIAN,
 187 };
 188
 189 static void pl031_init(Object *obj)
 190 {
 191     PL031State *s = PL031(obj);
 192     SysBusDevice *dev = SYS_BUS_DEVICE(obj);
 193     struct tm tm;
 194
 195     memory_region_init_io(&s->iomem, obj, &pl031_ops, s, "pl031", 0x1000);
 196     sysbus_init_mmio(dev, &s->iomem);
 197
 198     sysbus_init_irq(dev, &s->irq);
 199     qemu_get_timedate(&tm, 0);
 200     s->tick_offset = mktimegm(&tm) -
 201         qemu_clock_get_ns(rtc_clock) / NANOSECONDS_PER_SECOND;
 202
 203     s->timer = timer_new_ns(rtc_clock, pl031_interrupt, s);
 204 }
 205
 206 static void pl031_finalize(Object *obj)
 207 {
 208     PL031State *s = PL031(obj);
 209
 210     timer_free(s->timer);
 211 }
 212
 213 static int pl031_pre_save(void *opaque)
 214 {
 215     PL031State *s = opaque;
 216
 217     /*
 218      * The PL031 device model code uses the tick_offset field, which is
 219      * the offset between what the guest RTC should read and what the
 220      * QEMU rtc_clock reads:
 221      *  guest_rtc = rtc_clock + tick_offset
 222      * and so
 223      *  tick_offset = guest_rtc - rtc_clock
 224      *
 225      * We want to migrate this offset, which sounds straightforward.
 226      * Unfortunately older versions of QEMU migrated a conversion of this
 227      * offset into an offset from the vm_clock. (This was in turn an
 228      * attempt to be compatible with even older QEMU versions, but it
 229      * has incorrect behaviour if the rtc_clock is not the same as the
 230      * vm_clock.) So we put the actual tick_offset into a migration
 231      * subsection, and the backwards-compatible time-relative-to-vm_clock
 232      * in the main migration state.
 233      *
 234      * Calculate base time relative to QEMU_CLOCK_VIRTUAL:
 235      */
 236     int64_t delta = qemu_clock_get_ns(rtc_clock) - qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
 237     s->tick_offset_vmstate = s->tick_offset + delta / NANOSECONDS_PER_SECOND;
 238
 239     return 0;
 240 }
 241
 242 static int pl031_pre_load(void *opaque)
 243 {
 244     PL031State *s = opaque;
 245
 246     s->tick_offset_migrated = false;
 247     return 0;
 248 }
 249
 250 static int pl031_post_load(void *opaque, int version_id)
 251 {
 252     PL031State *s = opaque;
 253
 254     /*
 255      * If we got the tick_offset subsection, then we can just use
 256      * the value in that. Otherwise the source is an older QEMU and
 257      * has given us the offset from the vm_clock; convert it back to
 258      * an offset from the rtc_clock. This will cause time to incorrectly
 259      * go backwards compared to the host RTC, but this is unavoidable.
 260      */
 261
 262     if (!s->tick_offset_migrated) {
 263         int64_t delta = qemu_clock_get_ns(rtc_clock) -
 264             qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
 265         s->tick_offset = s->tick_offset_vmstate -
 266             delta / NANOSECONDS_PER_SECOND;
 267     }
 268     pl031_set_alarm(s);
 269     return 0;
 270 }
 271
 272 static int pl031_tick_offset_post_load(void *opaque, int version_id)
 273 {
 274     PL031State *s = opaque;
 275
 276     s->tick_offset_migrated = true;
 277     return 0;
 278 }
 279
 280 static bool pl031_tick_offset_needed(void *opaque)
 281 {
 282     PL031State *s = opaque;
 283
 284     return s->migrate_tick_offset;
 285 }
 286
 287 static const VMStateDescription vmstate_pl031_tick_offset = {
 288     .name = "pl031/tick-offset",
 289     .version_id = 1,
 290     .minimum_version_id = 1,
 291     .needed = pl031_tick_offset_needed,
 292     .post_load = pl031_tick_offset_post_load,
 293     .fields = (VMStateField[]) {
 294         VMSTATE_UINT32(tick_offset, PL031State),
 295         VMSTATE_END_OF_LIST()
 296     }
 297 };
 298
 299 static const VMStateDescription vmstate_pl031 = {
 300     .name = "pl031",
 301     .version_id = 1,
 302     .minimum_version_id = 1,
 303     .pre_save = pl031_pre_save,
 304     .pre_load = pl031_pre_load,
 305     .post_load = pl031_post_load,
 306     .fields = (VMStateField[]) {
 307         VMSTATE_UINT32(tick_offset_vmstate, PL031State),
 308         VMSTATE_UINT32(mr, PL031State),
 309         VMSTATE_UINT32(lr, PL031State),
 310         VMSTATE_UINT32(cr, PL031State),
 311         VMSTATE_UINT32(im, PL031State),
 312         VMSTATE_UINT32(is, PL031State),
 313         VMSTATE_END_OF_LIST()
 314     },
 315     .subsections = (const VMStateDescription*[]) {
 316         &vmstate_pl031_tick_offset,
 317         NULL
 318     }
 319 };
 320
 321 static Property pl031_properties[] = {
 322     /*
 323      * True to correctly migrate the tick offset of the RTC. False to
 324      * obtain backward migration compatibility with older QEMU versions,
 325      * at the expense of the guest RTC going backwards compared with the
 326      * host RTC when the VM is saved/restored if using -rtc host.
 327      * (Even if set to 'true' older QEMU can migrate forward to newer QEMU;
 328      * 'false' also permits newer QEMU to migrate to older QEMU.)
 329      */
 330     DEFINE_PROP_BOOL("migrate-tick-offset",
 331                      PL031State, migrate_tick_offset, true),
 332     DEFINE_PROP_END_OF_LIST()
 333 };
 334
 335 static void pl031_class_init(ObjectClass *klass, void *data)
 336 {
 337     DeviceClass *dc = DEVICE_CLASS(klass);
 338
 339     dc->vmsd = &vmstate_pl031;
 340     device_class_set_props(dc, pl031_properties);
 341 }
 342
 343 static const TypeInfo pl031_info = {
 344     .name          = TYPE_PL031,
 345     .parent        = TYPE_SYS_BUS_DEVICE,
 346     .instance_size = sizeof(PL031State),
 347     .instance_init = pl031_init,
 348     .instance_finalize = pl031_finalize,
 349     .class_init    = pl031_class_init,
 350 };
 351
 352 static void pl031_register_types(void)
 353 {
 354     type_register_static(&pl031_info);
 355 }
 356
 357 type_init(pl031_register_types)