target/i386/tcg/decode-new.h

   1 /*
   2  * Decode table flags, mostly based on Intel SDM.
   3  *
   4  *  Copyright (c) 2022 Red Hat, Inc.
   5  *
   6  * Author: Paolo Bonzini <pbonzini@redhat.com>
   7  *
   8  * This library is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU Lesser General Public
  10  * License as published by the Free Software Foundation; either
  11  * version 2.1 of the License, or (at your option) any later version.
  12  *
  13  * This library is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  16  * Lesser General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU Lesser General Public
  19  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  20  */
  21
  22 typedef enum X86OpType {
  23     X86_TYPE_None,
  24
  25     X86_TYPE_A, /* Implicit */
  26     X86_TYPE_B, /* VEX.vvvv selects a GPR */
  27     X86_TYPE_C, /* REG in the modrm byte selects a control register */
  28     X86_TYPE_D, /* REG in the modrm byte selects a debug register */
  29     X86_TYPE_E, /* ALU modrm operand */
  30     X86_TYPE_F, /* EFLAGS/RFLAGS */
  31     X86_TYPE_G, /* REG in the modrm byte selects a GPR */
  32     X86_TYPE_H, /* For AVX, VEX.vvvv selects an XMM/YMM register */
  33     X86_TYPE_I, /* Immediate */
  34     X86_TYPE_J, /* Relative offset for a jump */
  35     X86_TYPE_L, /* The upper 4 bits of the immediate select a 128-bit register */
  36     X86_TYPE_M, /* modrm byte selects a memory operand */
  37     X86_TYPE_N, /* R/M in the modrm byte selects an MMX register */
  38     X86_TYPE_O, /* Absolute address encoded in the instruction */
  39     X86_TYPE_P, /* reg in the modrm byte selects an MMX register */
  40     X86_TYPE_Q, /* MMX modrm operand */
  41     X86_TYPE_R, /* R/M in the modrm byte selects a register */
  42     X86_TYPE_S, /* reg selects a segment register */
  43     X86_TYPE_U, /* R/M in the modrm byte selects an XMM/YMM register */
  44     X86_TYPE_V, /* reg in the modrm byte selects an XMM/YMM register */
  45     X86_TYPE_W, /* XMM/YMM modrm operand */
  46     X86_TYPE_X, /* string source */
  47     X86_TYPE_Y, /* string destination */
  48
  49     /* Custom */
  50     X86_TYPE_WM, /* modrm byte selects an XMM/YMM memory operand */
  51     X86_TYPE_2op, /* 2-operand RMW instruction */
  52     X86_TYPE_LoBits, /* encoded in bits 0-2 of the operand + REX.B */
  53     X86_TYPE_0, /* Hard-coded GPRs (RAX..RDI) */
  54     X86_TYPE_1,
  55     X86_TYPE_2,
  56     X86_TYPE_3,
  57     X86_TYPE_4,
  58     X86_TYPE_5,
  59     X86_TYPE_6,
  60     X86_TYPE_7,
  61     X86_TYPE_ES, /* Hard-coded segment registers */
  62     X86_TYPE_CS,
  63     X86_TYPE_SS,
  64     X86_TYPE_DS,
  65     X86_TYPE_FS,
  66     X86_TYPE_GS,
  67 } X86OpType;
  68
  69 typedef enum X86OpSize {
  70     X86_SIZE_None,
  71
  72     X86_SIZE_a,  /* BOUND operand */
  73     X86_SIZE_b,  /* byte */
  74     X86_SIZE_d,  /* 32-bit */
  75     X86_SIZE_dq, /* SSE/AVX 128-bit */
  76     X86_SIZE_p,  /* Far pointer */
  77     X86_SIZE_pd, /* SSE/AVX packed double precision */
  78     X86_SIZE_pi, /* MMX */
  79     X86_SIZE_ps, /* SSE/AVX packed single precision */
  80     X86_SIZE_q,  /* 64-bit */
  81     X86_SIZE_qq, /* AVX 256-bit */
  82     X86_SIZE_s,  /* Descriptor */
  83     X86_SIZE_sd, /* SSE/AVX scalar double precision */
  84     X86_SIZE_ss, /* SSE/AVX scalar single precision */
  85     X86_SIZE_si, /* 32-bit GPR */
  86     X86_SIZE_v,  /* 16/32/64-bit, based on operand size */
  87     X86_SIZE_w,  /* 16-bit */
  88     X86_SIZE_x,  /* 128/256-bit, based on operand size */
  89     X86_SIZE_y,  /* 32/64-bit, based on operand size */
  90     X86_SIZE_z,  /* 16-bit for 16-bit operand size, else 32-bit */
  91
  92     /* Custom */
  93     X86_SIZE_d64,
  94     X86_SIZE_f64,
  95     X86_SIZE_ph, /* SSE/AVX packed half precision */
  96 } X86OpSize;
  97
  98 typedef enum X86CPUIDFeature {
  99     X86_FEAT_None,
 100     X86_FEAT_3DNOW,
 101     X86_FEAT_ADX,
 102     X86_FEAT_AES,
 103     X86_FEAT_AVX,
 104     X86_FEAT_AVX2,
 105     X86_FEAT_BMI1,
 106     X86_FEAT_BMI2,
 107     X86_FEAT_F16C,
 108     X86_FEAT_FMA,
 109     X86_FEAT_MOVBE,
 110     X86_FEAT_PCLMULQDQ,
 111     X86_FEAT_SSE,
 112     X86_FEAT_SSE2,
 113     X86_FEAT_SSE3,
 114     X86_FEAT_SSSE3,
 115     X86_FEAT_SSE41,
 116     X86_FEAT_SSE42,
 117     X86_FEAT_SSE4A,
 118 } X86CPUIDFeature;
 119
 120 /* Execution flags */
 121
 122 typedef enum X86OpUnit {
 123     X86_OP_SKIP,    /* not valid or managed by emission function */
 124     X86_OP_SEG,     /* segment selector */
 125     X86_OP_CR,      /* control register */
 126     X86_OP_DR,      /* debug register */
 127     X86_OP_INT,     /* loaded into/stored from s->T0/T1 */
 128     X86_OP_IMM,     /* immediate */
 129     X86_OP_SSE,     /* address in either s->ptrX or s->A0 depending on has_ea */
 130     X86_OP_MMX,     /* address in either s->ptrX or s->A0 depending on has_ea */
 131 } X86OpUnit;
 132
 133 typedef enum X86InsnSpecial {
 134     X86_SPECIAL_None,
 135
 136     /* Always locked if it has a memory operand (XCHG) */
 137     X86_SPECIAL_Locked,
 138
 139     /* Fault outside protected mode */
 140     X86_SPECIAL_ProtMode,
 141
 142     /*
 143      * Register operand 0/2 is zero extended to 32 bits.  Rd/Mb or Rd/Mw
 144      * in the manual.
 145      */
 146     X86_SPECIAL_ZExtOp0,
 147     X86_SPECIAL_ZExtOp2,
 148
 149     /*
 150      * Register operand 2 is extended to full width, while a memory operand
 151      * is doubled in size if VEX.L=1.
 152      */
 153     X86_SPECIAL_AVXExtMov,
 154
 155     /*
 156      * MMX instruction exists with no prefix; if there is no prefix, V/H/W/U operands
 157      * become P/P/Q/N, and size "x" becomes "q".
 158      */
 159     X86_SPECIAL_MMX,
 160
 161     /* Illegal or exclusive to 64-bit mode */
 162     X86_SPECIAL_i64,
 163     X86_SPECIAL_o64,
 164 } X86InsnSpecial;
 165
 166 /*
 167  * Special cases for instructions that operate on XMM/YMM registers.  Intel
 168  * retconned all of them to have VEX exception classes other than 0 and 13, so
 169  * all these only matter for instructions that have a VEX exception class.
 170  * Based on tables in the "AVX and SSE Instruction Exception Specification"
 171  * section of the manual.
 172  */
 173 typedef enum X86VEXSpecial {
 174     /* Legacy SSE instructions that allow unaligned operands */
 175     X86_VEX_SSEUnaligned,
 176
 177     /*
 178      * Used for instructions that distinguish the XMM operand type with an
 179      * instruction prefix; legacy SSE encodings will allow unaligned operands
 180      * for scalar operands only (identified by a REP prefix).  In this case,
 181      * the decoding table uses "x" for the vector operands instead of specifying
 182      * pd/ps/sd/ss individually.
 183      */
 184     X86_VEX_REPScalar,
 185
 186     /*
 187      * VEX instructions that only support 256-bit operands with AVX2 (Table 2-17
 188      * column 3).  Columns 2 and 4 (instructions limited to 256- and 127-bit
 189      * operands respectively) are implicit in the presence of dq and qq
 190      * operands, and thus handled by decode_op_size.
 191      */
 192     X86_VEX_AVX2_256,
 193 } X86VEXSpecial;
 194
 195
 196 typedef struct X86OpEntry  X86OpEntry;
 197 typedef struct X86DecodedInsn X86DecodedInsn;
 198
 199 /* Decode function for multibyte opcodes.  */
 200 typedef void (*X86DecodeFunc)(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b);
 201
 202 /* Code generation function.  */
 203 typedef void (*X86GenFunc)(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode);
 204
 205 struct X86OpEntry {
 206     /* Based on the is_decode flags.  */
 207     union {
 208         X86GenFunc gen;
 209         X86DecodeFunc decode;
 210     };
 211     /* op0 is always written, op1 and op2 are always read.  */
 212     X86OpType    op0:8;
 213     X86OpSize    s0:8;
 214     X86OpType    op1:8;
 215     X86OpSize    s1:8;
 216     X86OpType    op2:8;
 217     X86OpSize    s2:8;
 218     /* Must be I and b respectively if present.  */
 219     X86OpType    op3:8;
 220     X86OpSize    s3:8;
 221
 222     X86InsnSpecial special:8;
 223     X86CPUIDFeature cpuid:8;
 224     unsigned     vex_class:8;
 225     X86VEXSpecial vex_special:8;
 226     uint16_t     valid_prefix:16;
 227     bool         is_decode:1;
 228 };
 229
 230 typedef struct X86DecodedOp {
 231     int8_t n;
 232     MemOp ot;     /* For b/c/d/p/s/q/v/w/y/z */
 233     X86OpUnit unit;
 234     bool has_ea;
 235     int offset;   /* For MMX and SSE */
 236
 237     /*
 238      * This field is used internally by macros OP0_PTR/OP1_PTR/OP2_PTR,
 239      * do not access directly!
 240      */
 241     TCGv_ptr v_ptr;
 242 } X86DecodedOp;
 243
 244 struct X86DecodedInsn {
 245     X86OpEntry e;
 246     X86DecodedOp op[3];
 247     target_ulong immediate;
 248     AddressParts mem;
 249
 250     uint8_t b;
 251 };
 252