2 * x86 FPU, MMX/3DNow!/SSE/SSE2/SSE3/SSSE3/SSE4/PNI helpers (sysemu code)
4 * Copyright (c) 2003 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2.1 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
20 #include "qemu/osdep.h"
24 static qemu_irq ferr_irq
;
26 void x86_register_ferr_irq(qemu_irq irq
)
31 void fpu_check_raise_ferr_irq(CPUX86State
*env
)
33 if (ferr_irq
&& !(env
->hflags2
& HF2_IGNNE_MASK
)) {
34 qemu_irq_raise(ferr_irq
);
39 void cpu_clear_ignne(void)
41 CPUX86State
*env
= &X86_CPU(first_cpu
)->env
;
42 env
->hflags2
&= ~HF2_IGNNE_MASK
;
45 void cpu_set_ignne(void)
47 CPUX86State
*env
= &X86_CPU(first_cpu
)->env
;
48 env
->hflags2
|= HF2_IGNNE_MASK
;
50 * We get here in response to a write to port F0h. The chipset should
51 * deassert FP_IRQ and FERR# instead should stay signaled until FPSW_SE is
52 * cleared, because FERR# and FP_IRQ are two separate pins on real
53 * hardware. However, we don't model FERR# as a qemu_irq, so we just
54 * do directly what the chipset would do, i.e. deassert FP_IRQ.
56 qemu_irq_lower(ferr_irq
);