hw/riscv/sifive_plic.c

   1 /*
   2  * SiFive PLIC (Platform Level Interrupt Controller)
   3  *
   4  * Copyright (c) 2017 SiFive, Inc.
   5  *
   6  * This provides a parameterizable interrupt controller based on SiFive's PLIC.
   7  *
   8  * This program is free software; you can redistribute it and/or modify it
   9  * under the terms and conditions of the GNU General Public License,
  10  * version 2 or later, as published by the Free Software Foundation.
  11  *
  12  * This program is distributed in the hope it will be useful, but WITHOUT
  13  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  15  * more details.
  16  *
  17  * You should have received a copy of the GNU General Public License along with
  18  * this program.  If not, see <http://www.gnu.org/licenses/>.
  19  */
  20
  21 #include "qemu/osdep.h"
  22 #include "qapi/error.h"
  23 #include "qemu/log.h"
  24 #include "qemu/module.h"
  25 #include "qemu/error-report.h"
  26 #include "hw/sysbus.h"
  27 #include "hw/pci/msi.h"
  28 #include "hw/boards.h"
  29 #include "hw/qdev-properties.h"
  30 #include "target/riscv/cpu.h"
  31 #include "sysemu/sysemu.h"
  32 #include "hw/riscv/sifive_plic.h"
  33
  34 #define RISCV_DEBUG_PLIC 0
  35
  36 static PLICMode char_to_mode(char c)
  37 {
  38     switch (c) {
  39     case 'U': return PLICMode_U;
  40     case 'S': return PLICMode_S;
  41     case 'H': return PLICMode_H;
  42     case 'M': return PLICMode_M;
  43     default:
  44         error_report("plic: invalid mode '%c'", c);
  45         exit(1);
  46     }
  47 }
  48
  49 static char mode_to_char(PLICMode m)
  50 {
  51     switch (m) {
  52     case PLICMode_U: return 'U';
  53     case PLICMode_S: return 'S';
  54     case PLICMode_H: return 'H';
  55     case PLICMode_M: return 'M';
  56     default: return '?';
  57     }
  58 }
  59
  60 static void sifive_plic_print_state(SiFivePLICState *plic)
  61 {
  62     int i;
  63     int addrid;
  64
  65     /* pending */
  66     qemu_log("pending       : ");
  67     for (i = plic->bitfield_words - 1; i >= 0; i--) {
  68         qemu_log("%08x", plic->pending[i]);
  69     }
  70     qemu_log("\n");
  71
  72     /* pending */
  73     qemu_log("claimed       : ");
  74     for (i = plic->bitfield_words - 1; i >= 0; i--) {
  75         qemu_log("%08x", plic->claimed[i]);
  76     }
  77     qemu_log("\n");
  78
  79     for (addrid = 0; addrid < plic->num_addrs; addrid++) {
  80         qemu_log("hart%d-%c enable: ",
  81             plic->addr_config[addrid].hartid,
  82             mode_to_char(plic->addr_config[addrid].mode));
  83         for (i = plic->bitfield_words - 1; i >= 0; i--) {
  84             qemu_log("%08x", plic->enable[addrid * plic->bitfield_words + i]);
  85         }
  86         qemu_log("\n");
  87     }
  88 }
  89
  90 static uint32_t atomic_set_masked(uint32_t *a, uint32_t mask, uint32_t value)
  91 {
  92     uint32_t old, new, cmp = atomic_read(a);
  93
  94     do {
  95         old = cmp;
  96         new = (old & ~mask) | (value & mask);
  97         cmp = atomic_cmpxchg(a, old, new);
  98     } while (old != cmp);
  99
 100     return old;
 101 }
 102
 103 static void sifive_plic_set_pending(SiFivePLICState *plic, int irq, bool level)
 104 {
 105     atomic_set_masked(&plic->pending[irq >> 5], 1 << (irq & 31), -!!level);
 106 }
 107
 108 static void sifive_plic_set_claimed(SiFivePLICState *plic, int irq, bool level)
 109 {
 110     atomic_set_masked(&plic->claimed[irq >> 5], 1 << (irq & 31), -!!level);
 111 }
 112
 113 static int sifive_plic_irqs_pending(SiFivePLICState *plic, uint32_t addrid)
 114 {
 115     int i, j;
 116     for (i = 0; i < plic->bitfield_words; i++) {
 117         uint32_t pending_enabled_not_claimed =
 118             (plic->pending[i] & ~plic->claimed[i]) &
 119             plic->enable[addrid * plic->bitfield_words + i];
 120         if (!pending_enabled_not_claimed) {
 121             continue;
 122         }
 123         for (j = 0; j < 32; j++) {
 124             int irq = (i << 5) + j;
 125             uint32_t prio = plic->source_priority[irq];
 126             int enabled = pending_enabled_not_claimed & (1 << j);
 127             if (enabled && prio > plic->target_priority[addrid]) {
 128                 return 1;
 129             }
 130         }
 131     }
 132     return 0;
 133 }
 134
 135 static void sifive_plic_update(SiFivePLICState *plic)
 136 {
 137     int addrid;
 138
 139     /* raise irq on harts where this irq is enabled */
 140     for (addrid = 0; addrid < plic->num_addrs; addrid++) {
 141         uint32_t hartid = plic->addr_config[addrid].hartid;
 142         PLICMode mode = plic->addr_config[addrid].mode;
 143         CPUState *cpu = qemu_get_cpu(hartid);
 144         CPURISCVState *env = cpu ? cpu->env_ptr : NULL;
 145         if (!env) {
 146             continue;
 147         }
 148         int level = sifive_plic_irqs_pending(plic, addrid);
 149         switch (mode) {
 150         case PLICMode_M:
 151             riscv_cpu_update_mip(RISCV_CPU(cpu), MIP_MEIP, BOOL_TO_MASK(level));
 152             break;
 153         case PLICMode_S:
 154             riscv_cpu_update_mip(RISCV_CPU(cpu), MIP_SEIP, BOOL_TO_MASK(level));
 155             break;
 156         default:
 157             break;
 158         }
 159     }
 160
 161     if (RISCV_DEBUG_PLIC) {
 162         sifive_plic_print_state(plic);
 163     }
 164 }
 165
 166 static uint32_t sifive_plic_claim(SiFivePLICState *plic, uint32_t addrid)
 167 {
 168     int i, j;
 169     for (i = 0; i < plic->bitfield_words; i++) {
 170         uint32_t pending_enabled_not_claimed =
 171             (plic->pending[i] & ~plic->claimed[i]) &
 172             plic->enable[addrid * plic->bitfield_words + i];
 173         if (!pending_enabled_not_claimed) {
 174             continue;
 175         }
 176         for (j = 0; j < 32; j++) {
 177             int irq = (i << 5) + j;
 178             uint32_t prio = plic->source_priority[irq];
 179             int enabled = pending_enabled_not_claimed & (1 << j);
 180             if (enabled && prio > plic->target_priority[addrid]) {
 181                 sifive_plic_set_pending(plic, irq, false);
 182                 sifive_plic_set_claimed(plic, irq, true);
 183                 return irq;
 184             }
 185         }
 186     }
 187     return 0;
 188 }
 189
 190 static uint64_t sifive_plic_read(void *opaque, hwaddr addr, unsigned size)
 191 {
 192     SiFivePLICState *plic = opaque;
 193
 194     /* writes must be 4 byte words */
 195     if ((addr & 0x3) != 0) {
 196         goto err;
 197     }
 198
 199     if (addr >= plic->priority_base && /* 4 bytes per source */
 200         addr < plic->priority_base + (plic->num_sources << 2))
 201     {
 202         uint32_t irq = ((addr - plic->priority_base) >> 2) + 1;
 203         if (RISCV_DEBUG_PLIC) {
 204             qemu_log("plic: read priority: irq=%d priority=%d\n",
 205                 irq, plic->source_priority[irq]);
 206         }
 207         return plic->source_priority[irq];
 208     } else if (addr >= plic->pending_base && /* 1 bit per source */
 209                addr < plic->pending_base + (plic->num_sources >> 3))
 210     {
 211         uint32_t word = (addr - plic->pending_base) >> 2;
 212         if (RISCV_DEBUG_PLIC) {
 213             qemu_log("plic: read pending: word=%d value=%d\n",
 214                 word, plic->pending[word]);
 215         }
 216         return plic->pending[word];
 217     } else if (addr >= plic->enable_base && /* 1 bit per source */
 218              addr < plic->enable_base + plic->num_addrs * plic->enable_stride)
 219     {
 220         uint32_t addrid = (addr - plic->enable_base) / plic->enable_stride;
 221         uint32_t wordid = (addr & (plic->enable_stride - 1)) >> 2;
 222         if (wordid < plic->bitfield_words) {
 223             if (RISCV_DEBUG_PLIC) {
 224                 qemu_log("plic: read enable: hart%d-%c word=%d value=%x\n",
 225                     plic->addr_config[addrid].hartid,
 226                     mode_to_char(plic->addr_config[addrid].mode), wordid,
 227                     plic->enable[addrid * plic->bitfield_words + wordid]);
 228             }
 229             return plic->enable[addrid * plic->bitfield_words + wordid];
 230         }
 231     } else if (addr >= plic->context_base && /* 1 bit per source */
 232              addr < plic->context_base + plic->num_addrs * plic->context_stride)
 233     {
 234         uint32_t addrid = (addr - plic->context_base) / plic->context_stride;
 235         uint32_t contextid = (addr & (plic->context_stride - 1));
 236         if (contextid == 0) {
 237             if (RISCV_DEBUG_PLIC) {
 238                 qemu_log("plic: read priority: hart%d-%c priority=%x\n",
 239                     plic->addr_config[addrid].hartid,
 240                     mode_to_char(plic->addr_config[addrid].mode),
 241                     plic->target_priority[addrid]);
 242             }
 243             return plic->target_priority[addrid];
 244         } else if (contextid == 4) {
 245             uint32_t value = sifive_plic_claim(plic, addrid);
 246             if (RISCV_DEBUG_PLIC) {
 247                 qemu_log("plic: read claim: hart%d-%c irq=%x\n",
 248                     plic->addr_config[addrid].hartid,
 249                     mode_to_char(plic->addr_config[addrid].mode),
 250                     value);
 251                 sifive_plic_print_state(plic);
 252             }
 253             return value;
 254         }
 255     }
 256
 257 err:
 258     qemu_log_mask(LOG_GUEST_ERROR,
 259                   "%s: Invalid register read 0x%" HWADDR_PRIx "\n",
 260                   __func__, addr);
 261     return 0;
 262 }
 263
 264 static void sifive_plic_write(void *opaque, hwaddr addr, uint64_t value,
 265         unsigned size)
 266 {
 267     SiFivePLICState *plic = opaque;
 268
 269     /* writes must be 4 byte words */
 270     if ((addr & 0x3) != 0) {
 271         goto err;
 272     }
 273
 274     if (addr >= plic->priority_base && /* 4 bytes per source */
 275         addr < plic->priority_base + (plic->num_sources << 2))
 276     {
 277         uint32_t irq = ((addr - plic->priority_base) >> 2) + 1;
 278         plic->source_priority[irq] = value & 7;
 279         if (RISCV_DEBUG_PLIC) {
 280             qemu_log("plic: write priority: irq=%d priority=%d\n",
 281                 irq, plic->source_priority[irq]);
 282         }
 283         return;
 284     } else if (addr >= plic->pending_base && /* 1 bit per source */
 285                addr < plic->pending_base + (plic->num_sources >> 3))
 286     {
 287         qemu_log_mask(LOG_GUEST_ERROR,
 288                       "%s: invalid pending write: 0x%" HWADDR_PRIx "",
 289                       __func__, addr);
 290         return;
 291     } else if (addr >= plic->enable_base && /* 1 bit per source */
 292         addr < plic->enable_base + plic->num_addrs * plic->enable_stride)
 293     {
 294         uint32_t addrid = (addr - plic->enable_base) / plic->enable_stride;
 295         uint32_t wordid = (addr & (plic->enable_stride - 1)) >> 2;
 296         if (wordid < plic->bitfield_words) {
 297             plic->enable[addrid * plic->bitfield_words + wordid] = value;
 298             if (RISCV_DEBUG_PLIC) {
 299                 qemu_log("plic: write enable: hart%d-%c word=%d value=%x\n",
 300                     plic->addr_config[addrid].hartid,
 301                     mode_to_char(plic->addr_config[addrid].mode), wordid,
 302                     plic->enable[addrid * plic->bitfield_words + wordid]);
 303             }
 304             return;
 305         }
 306     } else if (addr >= plic->context_base && /* 4 bytes per reg */
 307         addr < plic->context_base + plic->num_addrs * plic->context_stride)
 308     {
 309         uint32_t addrid = (addr - plic->context_base) / plic->context_stride;
 310         uint32_t contextid = (addr & (plic->context_stride - 1));
 311         if (contextid == 0) {
 312             if (RISCV_DEBUG_PLIC) {
 313                 qemu_log("plic: write priority: hart%d-%c priority=%x\n",
 314                     plic->addr_config[addrid].hartid,
 315                     mode_to_char(plic->addr_config[addrid].mode),
 316                     plic->target_priority[addrid]);
 317             }
 318             if (value <= plic->num_priorities) {
 319                 plic->target_priority[addrid] = value;
 320                 sifive_plic_update(plic);
 321             }
 322             return;
 323         } else if (contextid == 4) {
 324             if (RISCV_DEBUG_PLIC) {
 325                 qemu_log("plic: write claim: hart%d-%c irq=%x\n",
 326                     plic->addr_config[addrid].hartid,
 327                     mode_to_char(plic->addr_config[addrid].mode),
 328                     (uint32_t)value);
 329             }
 330             if (value < plic->num_sources) {
 331                 sifive_plic_set_claimed(plic, value, false);
 332                 sifive_plic_update(plic);
 333             }
 334             return;
 335         }
 336     }
 337
 338 err:
 339     qemu_log_mask(LOG_GUEST_ERROR,
 340                   "%s: Invalid register write 0x%" HWADDR_PRIx "\n",
 341                   __func__, addr);
 342 }
 343
 344 static const MemoryRegionOps sifive_plic_ops = {
 345     .read = sifive_plic_read,
 346     .write = sifive_plic_write,
 347     .endianness = DEVICE_LITTLE_ENDIAN,
 348     .valid = {
 349         .min_access_size = 4,
 350         .max_access_size = 4
 351     }
 352 };
 353
 354 static Property sifive_plic_properties[] = {
 355     DEFINE_PROP_STRING("hart-config", SiFivePLICState, hart_config),
 356     DEFINE_PROP_UINT32("num-sources", SiFivePLICState, num_sources, 0),
 357     DEFINE_PROP_UINT32("num-priorities", SiFivePLICState, num_priorities, 0),
 358     DEFINE_PROP_UINT32("priority-base", SiFivePLICState, priority_base, 0),
 359     DEFINE_PROP_UINT32("pending-base", SiFivePLICState, pending_base, 0),
 360     DEFINE_PROP_UINT32("enable-base", SiFivePLICState, enable_base, 0),
 361     DEFINE_PROP_UINT32("enable-stride", SiFivePLICState, enable_stride, 0),
 362     DEFINE_PROP_UINT32("context-base", SiFivePLICState, context_base, 0),
 363     DEFINE_PROP_UINT32("context-stride", SiFivePLICState, context_stride, 0),
 364     DEFINE_PROP_UINT32("aperture-size", SiFivePLICState, aperture_size, 0),
 365     DEFINE_PROP_END_OF_LIST(),
 366 };
 367
 368 /*
 369  * parse PLIC hart/mode address offset config
 370  *
 371  * "M"              1 hart with M mode
 372  * "MS,MS"          2 harts, 0-1 with M and S mode
 373  * "M,MS,MS,MS,MS"  5 harts, 0 with M mode, 1-5 with M and S mode
 374  */
 375 static void parse_hart_config(SiFivePLICState *plic)
 376 {
 377     int addrid, hartid, modes;
 378     const char *p;
 379     char c;
 380
 381     /* count and validate hart/mode combinations */
 382     addrid = 0, hartid = 0, modes = 0;
 383     p = plic->hart_config;
 384     while ((c = *p++)) {
 385         if (c == ',') {
 386             addrid += ctpop8(modes);
 387             modes = 0;
 388             hartid++;
 389         } else {
 390             int m = 1 << char_to_mode(c);
 391             if (modes == (modes | m)) {
 392                 error_report("plic: duplicate mode '%c' in config: %s",
 393                              c, plic->hart_config);
 394                 exit(1);
 395             }
 396             modes |= m;
 397         }
 398     }
 399     if (modes) {
 400         addrid += ctpop8(modes);
 401     }
 402     hartid++;
 403
 404     /* store hart/mode combinations */
 405     plic->num_addrs = addrid;
 406     plic->addr_config = g_new(PLICAddr, plic->num_addrs);
 407     addrid = 0, hartid = 0;
 408     p = plic->hart_config;
 409     while ((c = *p++)) {
 410         if (c == ',') {
 411             hartid++;
 412         } else {
 413             plic->addr_config[addrid].addrid = addrid;
 414             plic->addr_config[addrid].hartid = hartid;
 415             plic->addr_config[addrid].mode = char_to_mode(c);
 416             addrid++;
 417         }
 418     }
 419 }
 420
 421 static void sifive_plic_irq_request(void *opaque, int irq, int level)
 422 {
 423     SiFivePLICState *plic = opaque;
 424     if (RISCV_DEBUG_PLIC) {
 425         qemu_log("sifive_plic_irq_request: irq=%d level=%d\n", irq, level);
 426     }
 427     sifive_plic_set_pending(plic, irq, level > 0);
 428     sifive_plic_update(plic);
 429 }
 430
 431 static void sifive_plic_realize(DeviceState *dev, Error **errp)
 432 {
 433     MachineState *ms = MACHINE(qdev_get_machine());
 434     unsigned int smp_cpus = ms->smp.cpus;
 435     SiFivePLICState *plic = SIFIVE_PLIC(dev);
 436     int i;
 437
 438     memory_region_init_io(&plic->mmio, OBJECT(dev), &sifive_plic_ops, plic,
 439                           TYPE_SIFIVE_PLIC, plic->aperture_size);
 440     parse_hart_config(plic);
 441     plic->bitfield_words = (plic->num_sources + 31) >> 5;
 442     plic->source_priority = g_new0(uint32_t, plic->num_sources);
 443     plic->target_priority = g_new(uint32_t, plic->num_addrs);
 444     plic->pending = g_new0(uint32_t, plic->bitfield_words);
 445     plic->claimed = g_new0(uint32_t, plic->bitfield_words);
 446     plic->enable = g_new0(uint32_t, plic->bitfield_words * plic->num_addrs);
 447     sysbus_init_mmio(SYS_BUS_DEVICE(dev), &plic->mmio);
 448     qdev_init_gpio_in(dev, sifive_plic_irq_request, plic->num_sources);
 449
 450     /* We can't allow the supervisor to control SEIP as this would allow the
 451      * supervisor to clear a pending external interrupt which will result in
 452      * lost a interrupt in the case a PLIC is attached. The SEIP bit must be
 453      * hardware controlled when a PLIC is attached.
 454      */
 455     for (i = 0; i < smp_cpus; i++) {
 456         RISCVCPU *cpu = RISCV_CPU(qemu_get_cpu(i));
 457         if (riscv_cpu_claim_interrupts(cpu, MIP_SEIP) < 0) {
 458             error_report("SEIP already claimed");
 459             exit(1);
 460         }
 461     }
 462
 463     msi_nonbroken = true;
 464 }
 465
 466 static void sifive_plic_class_init(ObjectClass *klass, void *data)
 467 {
 468     DeviceClass *dc = DEVICE_CLASS(klass);
 469
 470     device_class_set_props(dc, sifive_plic_properties);
 471     dc->realize = sifive_plic_realize;
 472 }
 473
 474 static const TypeInfo sifive_plic_info = {
 475     .name          = TYPE_SIFIVE_PLIC,
 476     .parent        = TYPE_SYS_BUS_DEVICE,
 477     .instance_size = sizeof(SiFivePLICState),
 478     .class_init    = sifive_plic_class_init,
 479 };
 480
 481 static void sifive_plic_register_types(void)
 482 {
 483     type_register_static(&sifive_plic_info);
 484 }
 485
 486 type_init(sifive_plic_register_types)
 487
 488 /*
 489  * Create PLIC device.
 490  */
 491 DeviceState *sifive_plic_create(hwaddr addr, char *hart_config,
 492     uint32_t num_sources, uint32_t num_priorities,
 493     uint32_t priority_base, uint32_t pending_base,
 494     uint32_t enable_base, uint32_t enable_stride,
 495     uint32_t context_base, uint32_t context_stride,
 496     uint32_t aperture_size)
 497 {
 498     DeviceState *dev = qdev_new(TYPE_SIFIVE_PLIC);
 499     assert(enable_stride == (enable_stride & -enable_stride));
 500     assert(context_stride == (context_stride & -context_stride));
 501     qdev_prop_set_string(dev, "hart-config", hart_config);
 502     qdev_prop_set_uint32(dev, "num-sources", num_sources);
 503     qdev_prop_set_uint32(dev, "num-priorities", num_priorities);
 504     qdev_prop_set_uint32(dev, "priority-base", priority_base);
 505     qdev_prop_set_uint32(dev, "pending-base", pending_base);
 506     qdev_prop_set_uint32(dev, "enable-base", enable_base);
 507     qdev_prop_set_uint32(dev, "enable-stride", enable_stride);
 508     qdev_prop_set_uint32(dev, "context-base", context_base);
 509     qdev_prop_set_uint32(dev, "context-stride", context_stride);
 510     qdev_prop_set_uint32(dev, "aperture-size", aperture_size);
 511     sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
 512     sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr);
 513     return dev;
 514 }