include/hw/riscv/sifive_u.h

   1 /*
   2  * SiFive U series machine interface
   3  *
   4  * Copyright (c) 2017 SiFive, Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms and conditions of the GNU General Public License,
   8  * version 2 or later, as published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13  * more details.
  14  *
  15  * You should have received a copy of the GNU General Public License along with
  16  * this program.  If not, see <http://www.gnu.org/licenses/>.
  17  */
  18
  19 #ifndef HW_SIFIVE_U_H
  20 #define HW_SIFIVE_U_H
  21
  22 #include "hw/net/cadence_gem.h"
  23
  24 #define TYPE_RISCV_U_SOC "riscv.sifive.u.soc"
  25 #define RISCV_U_SOC(obj) \
  26     OBJECT_CHECK(SiFiveUSoCState, (obj), TYPE_RISCV_U_SOC)
  27
  28 typedef struct SiFiveUSoCState {
  29     /*< private >*/
  30     SysBusDevice parent_obj;
  31
  32     /*< public >*/
  33     RISCVHartArrayState cpus;
  34     DeviceState *plic;
  35     CadenceGEMState gem;
  36 } SiFiveUSoCState;
  37
  38 typedef struct SiFiveUState {
  39     /*< private >*/
  40     SysBusDevice parent_obj;
  41
  42     /*< public >*/
  43     SiFiveUSoCState soc;
  44     void *fdt;
  45     int fdt_size;
  46 } SiFiveUState;
  47
  48 enum {
  49     SIFIVE_U_DEBUG,
  50     SIFIVE_U_MROM,
  51     SIFIVE_U_CLINT,
  52     SIFIVE_U_PLIC,
  53     SIFIVE_U_UART0,
  54     SIFIVE_U_UART1,
  55     SIFIVE_U_DRAM,
  56     SIFIVE_U_GEM
  57 };
  58
  59 enum {
  60     SIFIVE_U_UART0_IRQ = 3,
  61     SIFIVE_U_UART1_IRQ = 4,
  62     SIFIVE_U_GEM_IRQ = 0x35
  63 };
  64
  65 enum {
  66     SIFIVE_U_CLOCK_FREQ = 1000000000
  67 };
  68
  69 #define SIFIVE_U_PLIC_HART_CONFIG "MS"
  70 #define SIFIVE_U_PLIC_NUM_SOURCES 127
  71 #define SIFIVE_U_PLIC_NUM_PRIORITIES 7
  72 #define SIFIVE_U_PLIC_PRIORITY_BASE 0x0
  73 #define SIFIVE_U_PLIC_PENDING_BASE 0x1000
  74 #define SIFIVE_U_PLIC_ENABLE_BASE 0x2000
  75 #define SIFIVE_U_PLIC_ENABLE_STRIDE 0x80
  76 #define SIFIVE_U_PLIC_CONTEXT_BASE 0x200000
  77 #define SIFIVE_U_PLIC_CONTEXT_STRIDE 0x1000
  78
  79 #if defined(TARGET_RISCV32)
  80 #define SIFIVE_U_CPU TYPE_RISCV_CPU_SIFIVE_U34
  81 #elif defined(TARGET_RISCV64)
  82 #define SIFIVE_U_CPU TYPE_RISCV_CPU_SIFIVE_U54
  83 #endif
  84
  85 #endif