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sysemu: Split sysemu/runstate.h off sysemu/sysemu.h
[qemu/armbru.git] / hw / i386 / pc.c
blob3ab4bcb3ca1dd3ebfe2eb8887bf47f91fe3ba14a
1 /*
2 * QEMU PC System Emulator
3 *
4 * Copyright (c) 2003-2004 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24
25 #include "qemu/osdep.h"
26 #include "qemu/units.h"
27 #include "hw/i386/pc.h"
28 #include "hw/char/serial.h"
29 #include "hw/char/parallel.h"
30 #include "hw/i386/apic.h"
31 #include "hw/i386/topology.h"
32 #include "hw/i386/fw_cfg.h"
33 #include "sysemu/cpus.h"
34 #include "hw/block/fdc.h"
35 #include "hw/ide.h"
36 #include "hw/pci/pci.h"
37 #include "hw/pci/pci_bus.h"
38 #include "hw/nvram/fw_cfg.h"
39 #include "hw/timer/hpet.h"
40 #include "hw/firmware/smbios.h"
41 #include "hw/loader.h"
42 #include "elf.h"
43 #include "migration/vmstate.h"
44 #include "multiboot.h"
45 #include "hw/timer/mc146818rtc.h"
46 #include "hw/dma/i8257.h"
47 #include "hw/timer/i8254.h"
48 #include "hw/input/i8042.h"
49 #include "hw/irq.h"
50 #include "hw/audio/pcspk.h"
51 #include "hw/pci/msi.h"
52 #include "hw/sysbus.h"
53 #include "sysemu/sysemu.h"
54 #include "sysemu/tcg.h"
55 #include "sysemu/numa.h"
56 #include "sysemu/kvm.h"
57 #include "sysemu/qtest.h"
58 #include "sysemu/reset.h"
59 #include "sysemu/runstate.h"
60 #include "kvm_i386.h"
61 #include "hw/xen/xen.h"
62 #include "hw/xen/start_info.h"
63 #include "ui/qemu-spice.h"
64 #include "exec/memory.h"
65 #include "exec/address-spaces.h"
66 #include "sysemu/arch_init.h"
67 #include "qemu/bitmap.h"
68 #include "qemu/config-file.h"
69 #include "qemu/error-report.h"
70 #include "qemu/option.h"
71 #include "hw/acpi/acpi.h"
72 #include "hw/acpi/cpu_hotplug.h"
73 #include "hw/boards.h"
74 #include "acpi-build.h"
75 #include "hw/mem/pc-dimm.h"
76 #include "qapi/error.h"
77 #include "qapi/qapi-visit-common.h"
78 #include "qapi/visitor.h"
79 #include "qom/cpu.h"
80 #include "hw/nmi.h"
81 #include "hw/usb.h"
82 #include "hw/i386/intel_iommu.h"
83 #include "hw/net/ne2000-isa.h"
84 #include "standard-headers/asm-x86/bootparam.h"
85 #include "hw/virtio/virtio-pmem-pci.h"
86 #include "hw/mem/memory-device.h"
87 #include "sysemu/replay.h"
88 #include "qapi/qmp/qerror.h"
89 #include "config-devices.h"
90
91 /* debug PC/ISA interrupts */
92 //#define DEBUG_IRQ
93
94 #ifdef DEBUG_IRQ
95 #define DPRINTF(fmt, ...) \
96 do { printf("CPUIRQ: " fmt , ## __VA_ARGS__); } while (0)
97 #else
98 #define DPRINTF(fmt, ...)
99 #endif
100
101 #define E820_NR_ENTRIES 16
102
103 struct e820_entry {
104 uint64_t address;
105 uint64_t length;
106 uint32_t type;
107 } QEMU_PACKED __attribute((__aligned__(4)));
108
109 struct e820_table {
110 uint32_t count;
111 struct e820_entry entry[E820_NR_ENTRIES];
112 } QEMU_PACKED __attribute((__aligned__(4)));
113
114 static struct e820_table e820_reserve;
115 static struct e820_entry *e820_table;
116 static unsigned e820_entries;
117 struct hpet_fw_config hpet_cfg = {.count = UINT8_MAX};
118
119 /* Physical Address of PVH entry point read from kernel ELF NOTE */
120 static size_t pvh_start_addr;
121
122 GlobalProperty pc_compat_4_0[] = {};
123 const size_t pc_compat_4_0_len = G_N_ELEMENTS(pc_compat_4_0);
124
125 GlobalProperty pc_compat_3_1[] = {
126 { "intel-iommu", "dma-drain", "off" },
127 { "Opteron_G3" "-" TYPE_X86_CPU, "rdtscp", "off" },
128 { "Opteron_G4" "-" TYPE_X86_CPU, "rdtscp", "off" },
129 { "Opteron_G4" "-" TYPE_X86_CPU, "npt", "off" },
130 { "Opteron_G4" "-" TYPE_X86_CPU, "nrip-save", "off" },
131 { "Opteron_G5" "-" TYPE_X86_CPU, "rdtscp", "off" },
132 { "Opteron_G5" "-" TYPE_X86_CPU, "npt", "off" },
133 { "Opteron_G5" "-" TYPE_X86_CPU, "nrip-save", "off" },
134 { "EPYC" "-" TYPE_X86_CPU, "npt", "off" },
135 { "EPYC" "-" TYPE_X86_CPU, "nrip-save", "off" },
136 { "EPYC-IBPB" "-" TYPE_X86_CPU, "npt", "off" },
137 { "EPYC-IBPB" "-" TYPE_X86_CPU, "nrip-save", "off" },
138 { "Skylake-Client" "-" TYPE_X86_CPU, "mpx", "on" },
139 { "Skylake-Client-IBRS" "-" TYPE_X86_CPU, "mpx", "on" },
140 { "Skylake-Server" "-" TYPE_X86_CPU, "mpx", "on" },
141 { "Skylake-Server-IBRS" "-" TYPE_X86_CPU, "mpx", "on" },
142 { "Cascadelake-Server" "-" TYPE_X86_CPU, "mpx", "on" },
143 { "Icelake-Client" "-" TYPE_X86_CPU, "mpx", "on" },
144 { "Icelake-Server" "-" TYPE_X86_CPU, "mpx", "on" },
145 { "Cascadelake-Server" "-" TYPE_X86_CPU, "stepping", "5" },
146 { TYPE_X86_CPU, "x-intel-pt-auto-level", "off" },
147 };
148 const size_t pc_compat_3_1_len = G_N_ELEMENTS(pc_compat_3_1);
149
150 GlobalProperty pc_compat_3_0[] = {
151 { TYPE_X86_CPU, "x-hv-synic-kvm-only", "on" },
152 { "Skylake-Server" "-" TYPE_X86_CPU, "pku", "off" },
153 { "Skylake-Server-IBRS" "-" TYPE_X86_CPU, "pku", "off" },
154 };
155 const size_t pc_compat_3_0_len = G_N_ELEMENTS(pc_compat_3_0);
156
157 GlobalProperty pc_compat_2_12[] = {
158 { TYPE_X86_CPU, "legacy-cache", "on" },
159 { TYPE_X86_CPU, "topoext", "off" },
160 { "EPYC-" TYPE_X86_CPU, "xlevel", "0x8000000a" },
161 { "EPYC-IBPB-" TYPE_X86_CPU, "xlevel", "0x8000000a" },
162 };
163 const size_t pc_compat_2_12_len = G_N_ELEMENTS(pc_compat_2_12);
164
165 GlobalProperty pc_compat_2_11[] = {
166 { TYPE_X86_CPU, "x-migrate-smi-count", "off" },
167 { "Skylake-Server" "-" TYPE_X86_CPU, "clflushopt", "off" },
168 };
169 const size_t pc_compat_2_11_len = G_N_ELEMENTS(pc_compat_2_11);
170
171 GlobalProperty pc_compat_2_10[] = {
172 { TYPE_X86_CPU, "x-hv-max-vps", "0x40" },
173 { "i440FX-pcihost", "x-pci-hole64-fix", "off" },
174 { "q35-pcihost", "x-pci-hole64-fix", "off" },
175 };
176 const size_t pc_compat_2_10_len = G_N_ELEMENTS(pc_compat_2_10);
177
178 GlobalProperty pc_compat_2_9[] = {
179 { "mch", "extended-tseg-mbytes", "0" },
180 };
181 const size_t pc_compat_2_9_len = G_N_ELEMENTS(pc_compat_2_9);
182
183 GlobalProperty pc_compat_2_8[] = {
184 { TYPE_X86_CPU, "tcg-cpuid", "off" },
185 { "kvmclock", "x-mach-use-reliable-get-clock", "off" },
186 { "ICH9-LPC", "x-smi-broadcast", "off" },
187 { TYPE_X86_CPU, "vmware-cpuid-freq", "off" },
188 { "Haswell-" TYPE_X86_CPU, "stepping", "1" },
189 };
190 const size_t pc_compat_2_8_len = G_N_ELEMENTS(pc_compat_2_8);
191
192 GlobalProperty pc_compat_2_7[] = {
193 { TYPE_X86_CPU, "l3-cache", "off" },
194 { TYPE_X86_CPU, "full-cpuid-auto-level", "off" },
195 { "Opteron_G3" "-" TYPE_X86_CPU, "family", "15" },
196 { "Opteron_G3" "-" TYPE_X86_CPU, "model", "6" },
197 { "Opteron_G3" "-" TYPE_X86_CPU, "stepping", "1" },
198 { "isa-pcspk", "migrate", "off" },
199 };
200 const size_t pc_compat_2_7_len = G_N_ELEMENTS(pc_compat_2_7);
201
202 GlobalProperty pc_compat_2_6[] = {
203 { TYPE_X86_CPU, "cpuid-0xb", "off" },
204 { "vmxnet3", "romfile", "" },
205 { TYPE_X86_CPU, "fill-mtrr-mask", "off" },
206 { "apic-common", "legacy-instance-id", "on", }
207 };
208 const size_t pc_compat_2_6_len = G_N_ELEMENTS(pc_compat_2_6);
209
210 GlobalProperty pc_compat_2_5[] = {};
211 const size_t pc_compat_2_5_len = G_N_ELEMENTS(pc_compat_2_5);
212
213 GlobalProperty pc_compat_2_4[] = {
214 PC_CPU_MODEL_IDS("2.4.0")
215 { "Haswell-" TYPE_X86_CPU, "abm", "off" },
216 { "Haswell-noTSX-" TYPE_X86_CPU, "abm", "off" },
217 { "Broadwell-" TYPE_X86_CPU, "abm", "off" },
218 { "Broadwell-noTSX-" TYPE_X86_CPU, "abm", "off" },
219 { "host" "-" TYPE_X86_CPU, "host-cache-info", "on" },
220 { TYPE_X86_CPU, "check", "off" },
221 { "qemu64" "-" TYPE_X86_CPU, "sse4a", "on" },
222 { "qemu64" "-" TYPE_X86_CPU, "abm", "on" },
223 { "qemu64" "-" TYPE_X86_CPU, "popcnt", "on" },
224 { "qemu32" "-" TYPE_X86_CPU, "popcnt", "on" },
225 { "Opteron_G2" "-" TYPE_X86_CPU, "rdtscp", "on" },
226 { "Opteron_G3" "-" TYPE_X86_CPU, "rdtscp", "on" },
227 { "Opteron_G4" "-" TYPE_X86_CPU, "rdtscp", "on" },
228 { "Opteron_G5" "-" TYPE_X86_CPU, "rdtscp", "on", }
229 };
230 const size_t pc_compat_2_4_len = G_N_ELEMENTS(pc_compat_2_4);
231
232 GlobalProperty pc_compat_2_3[] = {
233 PC_CPU_MODEL_IDS("2.3.0")
234 { TYPE_X86_CPU, "arat", "off" },
235 { "qemu64" "-" TYPE_X86_CPU, "min-level", "4" },
236 { "kvm64" "-" TYPE_X86_CPU, "min-level", "5" },
237 { "pentium3" "-" TYPE_X86_CPU, "min-level", "2" },
238 { "n270" "-" TYPE_X86_CPU, "min-level", "5" },
239 { "Conroe" "-" TYPE_X86_CPU, "min-level", "4" },
240 { "Penryn" "-" TYPE_X86_CPU, "min-level", "4" },
241 { "Nehalem" "-" TYPE_X86_CPU, "min-level", "4" },
242 { "n270" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
243 { "Penryn" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
244 { "Conroe" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
245 { "Nehalem" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
246 { "Westmere" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
247 { "SandyBridge" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
248 { "IvyBridge" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
249 { "Haswell" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
250 { "Haswell-noTSX" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
251 { "Broadwell" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
252 { "Broadwell-noTSX" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
253 { TYPE_X86_CPU, "kvm-no-smi-migration", "on" },
254 };
255 const size_t pc_compat_2_3_len = G_N_ELEMENTS(pc_compat_2_3);
256
257 GlobalProperty pc_compat_2_2[] = {
258 PC_CPU_MODEL_IDS("2.2.0")
259 { "kvm64" "-" TYPE_X86_CPU, "vme", "off" },
260 { "kvm32" "-" TYPE_X86_CPU, "vme", "off" },
261 { "Conroe" "-" TYPE_X86_CPU, "vme", "off" },
262 { "Penryn" "-" TYPE_X86_CPU, "vme", "off" },
263 { "Nehalem" "-" TYPE_X86_CPU, "vme", "off" },
264 { "Westmere" "-" TYPE_X86_CPU, "vme", "off" },
265 { "SandyBridge" "-" TYPE_X86_CPU, "vme", "off" },
266 { "Haswell" "-" TYPE_X86_CPU, "vme", "off" },
267 { "Broadwell" "-" TYPE_X86_CPU, "vme", "off" },
268 { "Opteron_G1" "-" TYPE_X86_CPU, "vme", "off" },
269 { "Opteron_G2" "-" TYPE_X86_CPU, "vme", "off" },
270 { "Opteron_G3" "-" TYPE_X86_CPU, "vme", "off" },
271 { "Opteron_G4" "-" TYPE_X86_CPU, "vme", "off" },
272 { "Opteron_G5" "-" TYPE_X86_CPU, "vme", "off" },
273 { "Haswell" "-" TYPE_X86_CPU, "f16c", "off" },
274 { "Haswell" "-" TYPE_X86_CPU, "rdrand", "off" },
275 { "Broadwell" "-" TYPE_X86_CPU, "f16c", "off" },
276 { "Broadwell" "-" TYPE_X86_CPU, "rdrand", "off" },
277 };
278 const size_t pc_compat_2_2_len = G_N_ELEMENTS(pc_compat_2_2);
279
280 GlobalProperty pc_compat_2_1[] = {
281 PC_CPU_MODEL_IDS("2.1.0")
282 { "coreduo" "-" TYPE_X86_CPU, "vmx", "on" },
283 { "core2duo" "-" TYPE_X86_CPU, "vmx", "on" },
284 };
285 const size_t pc_compat_2_1_len = G_N_ELEMENTS(pc_compat_2_1);
286
287 GlobalProperty pc_compat_2_0[] = {
288 PC_CPU_MODEL_IDS("2.0.0")
289 { "virtio-scsi-pci", "any_layout", "off" },
290 { "PIIX4_PM", "memory-hotplug-support", "off" },
291 { "apic", "version", "0x11" },
292 { "nec-usb-xhci", "superspeed-ports-first", "off" },
293 { "nec-usb-xhci", "force-pcie-endcap", "on" },
294 { "pci-serial", "prog_if", "0" },
295 { "pci-serial-2x", "prog_if", "0" },
296 { "pci-serial-4x", "prog_if", "0" },
297 { "virtio-net-pci", "guest_announce", "off" },
298 { "ICH9-LPC", "memory-hotplug-support", "off" },
299 { "xio3130-downstream", COMPAT_PROP_PCP, "off" },
300 { "ioh3420", COMPAT_PROP_PCP, "off" },
301 };
302 const size_t pc_compat_2_0_len = G_N_ELEMENTS(pc_compat_2_0);
303
304 GlobalProperty pc_compat_1_7[] = {
305 PC_CPU_MODEL_IDS("1.7.0")
306 { TYPE_USB_DEVICE, "msos-desc", "no" },
307 { "PIIX4_PM", "acpi-pci-hotplug-with-bridge-support", "off" },
308 { "hpet", HPET_INTCAP, "4" },
309 };
310 const size_t pc_compat_1_7_len = G_N_ELEMENTS(pc_compat_1_7);
311
312 GlobalProperty pc_compat_1_6[] = {
313 PC_CPU_MODEL_IDS("1.6.0")
314 { "e1000", "mitigation", "off" },
315 { "qemu64-" TYPE_X86_CPU, "model", "2" },
316 { "qemu32-" TYPE_X86_CPU, "model", "3" },
317 { "i440FX-pcihost", "short_root_bus", "1" },
318 { "q35-pcihost", "short_root_bus", "1" },
319 };
320 const size_t pc_compat_1_6_len = G_N_ELEMENTS(pc_compat_1_6);
321
322 GlobalProperty pc_compat_1_5[] = {
323 PC_CPU_MODEL_IDS("1.5.0")
324 { "Conroe-" TYPE_X86_CPU, "model", "2" },
325 { "Conroe-" TYPE_X86_CPU, "min-level", "2" },
326 { "Penryn-" TYPE_X86_CPU, "model", "2" },
327 { "Penryn-" TYPE_X86_CPU, "min-level", "2" },
328 { "Nehalem-" TYPE_X86_CPU, "model", "2" },
329 { "Nehalem-" TYPE_X86_CPU, "min-level", "2" },
330 { "virtio-net-pci", "any_layout", "off" },
331 { TYPE_X86_CPU, "pmu", "on" },
332 { "i440FX-pcihost", "short_root_bus", "0" },
333 { "q35-pcihost", "short_root_bus", "0" },
334 };
335 const size_t pc_compat_1_5_len = G_N_ELEMENTS(pc_compat_1_5);
336
337 GlobalProperty pc_compat_1_4[] = {
338 PC_CPU_MODEL_IDS("1.4.0")
339 { "scsi-hd", "discard_granularity", "0" },
340 { "scsi-cd", "discard_granularity", "0" },
341 { "scsi-disk", "discard_granularity", "0" },
342 { "ide-hd", "discard_granularity", "0" },
343 { "ide-cd", "discard_granularity", "0" },
344 { "ide-drive", "discard_granularity", "0" },
345 { "virtio-blk-pci", "discard_granularity", "0" },
346 /* DEV_NVECTORS_UNSPECIFIED as a uint32_t string: */
347 { "virtio-serial-pci", "vectors", "0xFFFFFFFF" },
348 { "virtio-net-pci", "ctrl_guest_offloads", "off" },
349 { "e1000", "romfile", "pxe-e1000.rom" },
350 { "ne2k_pci", "romfile", "pxe-ne2k_pci.rom" },
351 { "pcnet", "romfile", "pxe-pcnet.rom" },
352 { "rtl8139", "romfile", "pxe-rtl8139.rom" },
353 { "virtio-net-pci", "romfile", "pxe-virtio.rom" },
354 { "486-" TYPE_X86_CPU, "model", "0" },
355 { "n270" "-" TYPE_X86_CPU, "movbe", "off" },
356 { "Westmere" "-" TYPE_X86_CPU, "pclmulqdq", "off" },
357 };
358 const size_t pc_compat_1_4_len = G_N_ELEMENTS(pc_compat_1_4);
359
360 void gsi_handler(void *opaque, int n, int level)
361 {
362 GSIState *s = opaque;
363
364 DPRINTF("pc: %s GSI %d\n", level ? "raising" : "lowering", n);
365 if (n < ISA_NUM_IRQS) {
366 qemu_set_irq(s->i8259_irq[n], level);
367 }
368 qemu_set_irq(s->ioapic_irq[n], level);
369 }
370
371 static void ioport80_write(void *opaque, hwaddr addr, uint64_t data,
372 unsigned size)
373 {
374 }
375
376 static uint64_t ioport80_read(void *opaque, hwaddr addr, unsigned size)
377 {
378 return 0xffffffffffffffffULL;
379 }
380
381 /* MSDOS compatibility mode FPU exception support */
382 static qemu_irq ferr_irq;
383
384 void pc_register_ferr_irq(qemu_irq irq)
385 {
386 ferr_irq = irq;
387 }
388
389 /* XXX: add IGNNE support */
390 void cpu_set_ferr(CPUX86State *s)
391 {
392 qemu_irq_raise(ferr_irq);
393 }
394
395 static void ioportF0_write(void *opaque, hwaddr addr, uint64_t data,
396 unsigned size)
397 {
398 qemu_irq_lower(ferr_irq);
399 }
400
401 static uint64_t ioportF0_read(void *opaque, hwaddr addr, unsigned size)
402 {
403 return 0xffffffffffffffffULL;
404 }
405
406 /* TSC handling */
407 uint64_t cpu_get_tsc(CPUX86State *env)
408 {
409 return cpu_get_ticks();
410 }
411
412 /* IRQ handling */
413 int cpu_get_pic_interrupt(CPUX86State *env)
414 {
415 X86CPU *cpu = env_archcpu(env);
416 int intno;
417
418 if (!kvm_irqchip_in_kernel()) {
419 intno = apic_get_interrupt(cpu->apic_state);
420 if (intno >= 0) {
421 return intno;
422 }
423 /* read the irq from the PIC */
424 if (!apic_accept_pic_intr(cpu->apic_state)) {
425 return -1;
426 }
427 }
428
429 intno = pic_read_irq(isa_pic);
430 return intno;
431 }
432
433 static void pic_irq_request(void *opaque, int irq, int level)
434 {
435 CPUState *cs = first_cpu;
436 X86CPU *cpu = X86_CPU(cs);
437
438 DPRINTF("pic_irqs: %s irq %d\n", level? "raise" : "lower", irq);
439 if (cpu->apic_state && !kvm_irqchip_in_kernel()) {
440 CPU_FOREACH(cs) {
441 cpu = X86_CPU(cs);
442 if (apic_accept_pic_intr(cpu->apic_state)) {
443 apic_deliver_pic_intr(cpu->apic_state, level);
444 }
445 }
446 } else {
447 if (level) {
448 cpu_interrupt(cs, CPU_INTERRUPT_HARD);
449 } else {
450 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
451 }
452 }
453 }
454
455 /* PC cmos mappings */
456
457 #define REG_EQUIPMENT_BYTE 0x14
458
459 int cmos_get_fd_drive_type(FloppyDriveType fd0)
460 {
461 int val;
462
463 switch (fd0) {
464 case FLOPPY_DRIVE_TYPE_144:
465 /* 1.44 Mb 3"5 drive */
466 val = 4;
467 break;
468 case FLOPPY_DRIVE_TYPE_288:
469 /* 2.88 Mb 3"5 drive */
470 val = 5;
471 break;
472 case FLOPPY_DRIVE_TYPE_120:
473 /* 1.2 Mb 5"5 drive */
474 val = 2;
475 break;
476 case FLOPPY_DRIVE_TYPE_NONE:
477 default:
478 val = 0;
479 break;
480 }
481 return val;
482 }
483
484 static void cmos_init_hd(ISADevice *s, int type_ofs, int info_ofs,
485 int16_t cylinders, int8_t heads, int8_t sectors)
486 {
487 rtc_set_memory(s, type_ofs, 47);
488 rtc_set_memory(s, info_ofs, cylinders);
489 rtc_set_memory(s, info_ofs + 1, cylinders >> 8);
490 rtc_set_memory(s, info_ofs + 2, heads);
491 rtc_set_memory(s, info_ofs + 3, 0xff);
492 rtc_set_memory(s, info_ofs + 4, 0xff);
493 rtc_set_memory(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3));
494 rtc_set_memory(s, info_ofs + 6, cylinders);
495 rtc_set_memory(s, info_ofs + 7, cylinders >> 8);
496 rtc_set_memory(s, info_ofs + 8, sectors);
497 }
498
499 /* convert boot_device letter to something recognizable by the bios */
500 static int boot_device2nibble(char boot_device)
501 {
502 switch(boot_device) {
503 case 'a':
504 case 'b':
505 return 0x01; /* floppy boot */
506 case 'c':
507 return 0x02; /* hard drive boot */
508 case 'd':
509 return 0x03; /* CD-ROM boot */
510 case 'n':
511 return 0x04; /* Network boot */
512 }
513 return 0;
514 }
515
516 static void set_boot_dev(ISADevice *s, const char *boot_device, Error **errp)
517 {
518 #define PC_MAX_BOOT_DEVICES 3
519 int nbds, bds[3] = { 0, };
520 int i;
521
522 nbds = strlen(boot_device);
523 if (nbds > PC_MAX_BOOT_DEVICES) {
524 error_setg(errp, "Too many boot devices for PC");
525 return;
526 }
527 for (i = 0; i < nbds; i++) {
528 bds[i] = boot_device2nibble(boot_device[i]);
529 if (bds[i] == 0) {
530 error_setg(errp, "Invalid boot device for PC: '%c'",
531 boot_device[i]);
532 return;
533 }
534 }
535 rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]);
536 rtc_set_memory(s, 0x38, (bds[2] << 4) | (fd_bootchk ? 0x0 : 0x1));
537 }
538
539 static void pc_boot_set(void *opaque, const char *boot_device, Error **errp)
540 {
541 set_boot_dev(opaque, boot_device, errp);
542 }
543
544 static void pc_cmos_init_floppy(ISADevice *rtc_state, ISADevice *floppy)
545 {
546 int val, nb, i;
547 FloppyDriveType fd_type[2] = { FLOPPY_DRIVE_TYPE_NONE,
548 FLOPPY_DRIVE_TYPE_NONE };
549
550 /* floppy type */
551 if (floppy) {
552 for (i = 0; i < 2; i++) {
553 fd_type[i] = isa_fdc_get_drive_type(floppy, i);
554 }
555 }
556 val = (cmos_get_fd_drive_type(fd_type[0]) << 4) |
557 cmos_get_fd_drive_type(fd_type[1]);
558 rtc_set_memory(rtc_state, 0x10, val);
559
560 val = rtc_get_memory(rtc_state, REG_EQUIPMENT_BYTE);
561 nb = 0;
562 if (fd_type[0] != FLOPPY_DRIVE_TYPE_NONE) {
563 nb++;
564 }
565 if (fd_type[1] != FLOPPY_DRIVE_TYPE_NONE) {
566 nb++;
567 }
568 switch (nb) {
569 case 0:
570 break;
571 case 1:
572 val |= 0x01; /* 1 drive, ready for boot */
573 break;
574 case 2:
575 val |= 0x41; /* 2 drives, ready for boot */
576 break;
577 }
578 rtc_set_memory(rtc_state, REG_EQUIPMENT_BYTE, val);
579 }
580
581 typedef struct pc_cmos_init_late_arg {
582 ISADevice *rtc_state;
583 BusState *idebus[2];
584 } pc_cmos_init_late_arg;
585
586 typedef struct check_fdc_state {
587 ISADevice *floppy;
588 bool multiple;
589 } CheckFdcState;
590
591 static int check_fdc(Object *obj, void *opaque)
592 {
593 CheckFdcState *state = opaque;
594 Object *fdc;
595 uint32_t iobase;
596 Error *local_err = NULL;
597
598 fdc = object_dynamic_cast(obj, TYPE_ISA_FDC);
599 if (!fdc) {
600 return 0;
601 }
602
603 iobase = object_property_get_uint(obj, "iobase", &local_err);
604 if (local_err || iobase != 0x3f0) {
605 error_free(local_err);
606 return 0;
607 }
608
609 if (state->floppy) {
610 state->multiple = true;
611 } else {
612 state->floppy = ISA_DEVICE(obj);
613 }
614 return 0;
615 }
616
617 static const char * const fdc_container_path[] = {
618 "/unattached", "/peripheral", "/peripheral-anon"
619 };
620
621 /*
622 * Locate the FDC at IO address 0x3f0, in order to configure the CMOS registers
623 * and ACPI objects.
624 */
625 ISADevice *pc_find_fdc0(void)
626 {
627 int i;
628 Object *container;
629 CheckFdcState state = { 0 };
630
631 for (i = 0; i < ARRAY_SIZE(fdc_container_path); i++) {
632 container = container_get(qdev_get_machine(), fdc_container_path[i]);
633 object_child_foreach(container, check_fdc, &state);
634 }
635
636 if (state.multiple) {
637 warn_report("multiple floppy disk controllers with "
638 "iobase=0x3f0 have been found");
639 error_printf("the one being picked for CMOS setup might not reflect "
640 "your intent");
641 }
642
643 return state.floppy;
644 }
645
646 static void pc_cmos_init_late(void *opaque)
647 {
648 pc_cmos_init_late_arg *arg = opaque;
649 ISADevice *s = arg->rtc_state;
650 int16_t cylinders;
651 int8_t heads, sectors;
652 int val;
653 int i, trans;
654
655 val = 0;
656 if (arg->idebus[0] && ide_get_geometry(arg->idebus[0], 0,
657 &cylinders, &heads, &sectors) >= 0) {
658 cmos_init_hd(s, 0x19, 0x1b, cylinders, heads, sectors);
659 val |= 0xf0;
660 }
661 if (arg->idebus[0] && ide_get_geometry(arg->idebus[0], 1,
662 &cylinders, &heads, &sectors) >= 0) {
663 cmos_init_hd(s, 0x1a, 0x24, cylinders, heads, sectors);
664 val |= 0x0f;
665 }
666 rtc_set_memory(s, 0x12, val);
667
668 val = 0;
669 for (i = 0; i < 4; i++) {
670 /* NOTE: ide_get_geometry() returns the physical
671 geometry. It is always such that: 1 <= sects <= 63, 1
672 <= heads <= 16, 1 <= cylinders <= 16383. The BIOS
673 geometry can be different if a translation is done. */
674 if (arg->idebus[i / 2] &&
675 ide_get_geometry(arg->idebus[i / 2], i % 2,
676 &cylinders, &heads, &sectors) >= 0) {
677 trans = ide_get_bios_chs_trans(arg->idebus[i / 2], i % 2) - 1;
678 assert((trans & ~3) == 0);
679 val |= trans << (i * 2);
680 }
681 }
682 rtc_set_memory(s, 0x39, val);
683
684 pc_cmos_init_floppy(s, pc_find_fdc0());
685
686 qemu_unregister_reset(pc_cmos_init_late, opaque);
687 }
688
689 void pc_cmos_init(PCMachineState *pcms,
690 BusState *idebus0, BusState *idebus1,
691 ISADevice *s)
692 {
693 int val;
694 static pc_cmos_init_late_arg arg;
695
696 /* various important CMOS locations needed by PC/Bochs bios */
697
698 /* memory size */
699 /* base memory (first MiB) */
700 val = MIN(pcms->below_4g_mem_size / KiB, 640);
701 rtc_set_memory(s, 0x15, val);
702 rtc_set_memory(s, 0x16, val >> 8);
703 /* extended memory (next 64MiB) */
704 if (pcms->below_4g_mem_size > 1 * MiB) {
705 val = (pcms->below_4g_mem_size - 1 * MiB) / KiB;
706 } else {
707 val = 0;
708 }
709 if (val > 65535)
710 val = 65535;
711 rtc_set_memory(s, 0x17, val);
712 rtc_set_memory(s, 0x18, val >> 8);
713 rtc_set_memory(s, 0x30, val);
714 rtc_set_memory(s, 0x31, val >> 8);
715 /* memory between 16MiB and 4GiB */
716 if (pcms->below_4g_mem_size > 16 * MiB) {
717 val = (pcms->below_4g_mem_size - 16 * MiB) / (64 * KiB);
718 } else {
719 val = 0;
720 }
721 if (val > 65535)
722 val = 65535;
723 rtc_set_memory(s, 0x34, val);
724 rtc_set_memory(s, 0x35, val >> 8);
725 /* memory above 4GiB */
726 val = pcms->above_4g_mem_size / 65536;
727 rtc_set_memory(s, 0x5b, val);
728 rtc_set_memory(s, 0x5c, val >> 8);
729 rtc_set_memory(s, 0x5d, val >> 16);
730
731 object_property_add_link(OBJECT(pcms), "rtc_state",
732 TYPE_ISA_DEVICE,
733 (Object **)&pcms->rtc,
734 object_property_allow_set_link,
735 OBJ_PROP_LINK_STRONG, &error_abort);
736 object_property_set_link(OBJECT(pcms), OBJECT(s),
737 "rtc_state", &error_abort);
738
739 set_boot_dev(s, MACHINE(pcms)->boot_order, &error_fatal);
740
741 val = 0;
742 val |= 0x02; /* FPU is there */
743 val |= 0x04; /* PS/2 mouse installed */
744 rtc_set_memory(s, REG_EQUIPMENT_BYTE, val);
745
746 /* hard drives and FDC */
747 arg.rtc_state = s;
748 arg.idebus[0] = idebus0;
749 arg.idebus[1] = idebus1;
750 qemu_register_reset(pc_cmos_init_late, &arg);
751 }
752
753 #define TYPE_PORT92 "port92"
754 #define PORT92(obj) OBJECT_CHECK(Port92State, (obj), TYPE_PORT92)
755
756 /* port 92 stuff: could be split off */
757 typedef struct Port92State {
758 ISADevice parent_obj;
759
760 MemoryRegion io;
761 uint8_t outport;
762 qemu_irq a20_out;
763 } Port92State;
764
765 static void port92_write(void *opaque, hwaddr addr, uint64_t val,
766 unsigned size)
767 {
768 Port92State *s = opaque;
769 int oldval = s->outport;
770
771 DPRINTF("port92: write 0x%02" PRIx64 "\n", val);
772 s->outport = val;
773 qemu_set_irq(s->a20_out, (val >> 1) & 1);
774 if ((val & 1) && !(oldval & 1)) {
775 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
776 }
777 }
778
779 static uint64_t port92_read(void *opaque, hwaddr addr,
780 unsigned size)
781 {
782 Port92State *s = opaque;
783 uint32_t ret;
784
785 ret = s->outport;
786 DPRINTF("port92: read 0x%02x\n", ret);
787 return ret;
788 }
789
790 static void port92_init(ISADevice *dev, qemu_irq a20_out)
791 {
792 qdev_connect_gpio_out_named(DEVICE(dev), PORT92_A20_LINE, 0, a20_out);
793 }
794
795 static const VMStateDescription vmstate_port92_isa = {
796 .name = "port92",
797 .version_id = 1,
798 .minimum_version_id = 1,
799 .fields = (VMStateField[]) {
800 VMSTATE_UINT8(outport, Port92State),
801 VMSTATE_END_OF_LIST()
802 }
803 };
804
805 static void port92_reset(DeviceState *d)
806 {
807 Port92State *s = PORT92(d);
808
809 s->outport &= ~1;
810 }
811
812 static const MemoryRegionOps port92_ops = {
813 .read = port92_read,
814 .write = port92_write,
815 .impl = {
816 .min_access_size = 1,
817 .max_access_size = 1,
818 },
819 .endianness = DEVICE_LITTLE_ENDIAN,
820 };
821
822 static void port92_initfn(Object *obj)
823 {
824 Port92State *s = PORT92(obj);
825
826 memory_region_init_io(&s->io, OBJECT(s), &port92_ops, s, "port92", 1);
827
828 s->outport = 0;
829
830 qdev_init_gpio_out_named(DEVICE(obj), &s->a20_out, PORT92_A20_LINE, 1);
831 }
832
833 static void port92_realizefn(DeviceState *dev, Error **errp)
834 {
835 ISADevice *isadev = ISA_DEVICE(dev);
836 Port92State *s = PORT92(dev);
837
838 isa_register_ioport(isadev, &s->io, 0x92);
839 }
840
841 static void port92_class_initfn(ObjectClass *klass, void *data)
842 {
843 DeviceClass *dc = DEVICE_CLASS(klass);
844
845 dc->realize = port92_realizefn;
846 dc->reset = port92_reset;
847 dc->vmsd = &vmstate_port92_isa;
848 /*
849 * Reason: unlike ordinary ISA devices, this one needs additional
850 * wiring: its A20 output line needs to be wired up by
851 * port92_init().
852 */
853 dc->user_creatable = false;
854 }
855
856 static const TypeInfo port92_info = {
857 .name = TYPE_PORT92,
858 .parent = TYPE_ISA_DEVICE,
859 .instance_size = sizeof(Port92State),
860 .instance_init = port92_initfn,
861 .class_init = port92_class_initfn,
862 };
863
864 static void port92_register_types(void)
865 {
866 type_register_static(&port92_info);
867 }
868
869 type_init(port92_register_types)
870
871 static void handle_a20_line_change(void *opaque, int irq, int level)
872 {
873 X86CPU *cpu = opaque;
874
875 /* XXX: send to all CPUs ? */
876 /* XXX: add logic to handle multiple A20 line sources */
877 x86_cpu_set_a20(cpu, level);
878 }
879
880 int e820_add_entry(uint64_t address, uint64_t length, uint32_t type)
881 {
882 int index = le32_to_cpu(e820_reserve.count);
883 struct e820_entry *entry;
884
885 if (type != E820_RAM) {
886 /* old FW_CFG_E820_TABLE entry -- reservations only */
887 if (index >= E820_NR_ENTRIES) {
888 return -EBUSY;
889 }
890 entry = &e820_reserve.entry[index++];
891
892 entry->address = cpu_to_le64(address);
893 entry->length = cpu_to_le64(length);
894 entry->type = cpu_to_le32(type);
895
896 e820_reserve.count = cpu_to_le32(index);
897 }
898
899 /* new "etc/e820" file -- include ram too */
900 e820_table = g_renew(struct e820_entry, e820_table, e820_entries + 1);
901 e820_table[e820_entries].address = cpu_to_le64(address);
902 e820_table[e820_entries].length = cpu_to_le64(length);
903 e820_table[e820_entries].type = cpu_to_le32(type);
904 e820_entries++;
905
906 return e820_entries;
907 }
908
909 int e820_get_num_entries(void)
910 {
911 return e820_entries;
912 }
913
914 bool e820_get_entry(int idx, uint32_t type, uint64_t *address, uint64_t *length)
915 {
916 if (idx < e820_entries && e820_table[idx].type == cpu_to_le32(type)) {
917 *address = le64_to_cpu(e820_table[idx].address);
918 *length = le64_to_cpu(e820_table[idx].length);
919 return true;
920 }
921 return false;
922 }
923
924 /* Calculates initial APIC ID for a specific CPU index
925 *
926 * Currently we need to be able to calculate the APIC ID from the CPU index
927 * alone (without requiring a CPU object), as the QEMU<->Seabios interfaces have
928 * no concept of "CPU index", and the NUMA tables on fw_cfg need the APIC ID of
929 * all CPUs up to max_cpus.
930 */
931 static uint32_t x86_cpu_apic_id_from_index(PCMachineState *pcms,
932 unsigned int cpu_index)
933 {
934 MachineState *ms = MACHINE(pcms);
935 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
936 uint32_t correct_id;
937 static bool warned;
938
939 correct_id = x86_apicid_from_cpu_idx(pcms->smp_dies, ms->smp.cores,
940 ms->smp.threads, cpu_index);
941 if (pcmc->compat_apic_id_mode) {
942 if (cpu_index != correct_id && !warned && !qtest_enabled()) {
943 error_report("APIC IDs set in compatibility mode, "
944 "CPU topology won't match the configuration");
945 warned = true;
946 }
947 return cpu_index;
948 } else {
949 return correct_id;
950 }
951 }
952
953 static void pc_build_smbios(PCMachineState *pcms)
954 {
955 uint8_t *smbios_tables, *smbios_anchor;
956 size_t smbios_tables_len, smbios_anchor_len;
957 struct smbios_phys_mem_area *mem_array;
958 unsigned i, array_count;
959 MachineState *ms = MACHINE(pcms);
960 X86CPU *cpu = X86_CPU(ms->possible_cpus->cpus[0].cpu);
961
962 /* tell smbios about cpuid version and features */
963 smbios_set_cpuid(cpu->env.cpuid_version, cpu->env.features[FEAT_1_EDX]);
964
965 smbios_tables = smbios_get_table_legacy(ms, &smbios_tables_len);
966 if (smbios_tables) {
967 fw_cfg_add_bytes(pcms->fw_cfg, FW_CFG_SMBIOS_ENTRIES,
968 smbios_tables, smbios_tables_len);
969 }
970
971 /* build the array of physical mem area from e820 table */
972 mem_array = g_malloc0(sizeof(*mem_array) * e820_get_num_entries());
973 for (i = 0, array_count = 0; i < e820_get_num_entries(); i++) {
974 uint64_t addr, len;
975
976 if (e820_get_entry(i, E820_RAM, &addr, &len)) {
977 mem_array[array_count].address = addr;
978 mem_array[array_count].length = len;
979 array_count++;
980 }
981 }
982 smbios_get_tables(ms, mem_array, array_count,
983 &smbios_tables, &smbios_tables_len,
984 &smbios_anchor, &smbios_anchor_len);
985 g_free(mem_array);
986
987 if (smbios_anchor) {
988 fw_cfg_add_file(pcms->fw_cfg, "etc/smbios/smbios-tables",
989 smbios_tables, smbios_tables_len);
990 fw_cfg_add_file(pcms->fw_cfg, "etc/smbios/smbios-anchor",
991 smbios_anchor, smbios_anchor_len);
992 }
993 }
994
995 static FWCfgState *bochs_bios_init(AddressSpace *as, PCMachineState *pcms)
996 {
997 FWCfgState *fw_cfg;
998 uint64_t *numa_fw_cfg;
999 int i;
1000 const CPUArchIdList *cpus;
1001 MachineClass *mc = MACHINE_GET_CLASS(pcms);
1002
1003 fw_cfg = fw_cfg_init_io_dma(FW_CFG_IO_BASE, FW_CFG_IO_BASE + 4, as);
1004 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, pcms->boot_cpus);
1005
1006 /* FW_CFG_MAX_CPUS is a bit confusing/problematic on x86:
1007 *
1008 * For machine types prior to 1.8, SeaBIOS needs FW_CFG_MAX_CPUS for
1009 * building MPTable, ACPI MADT, ACPI CPU hotplug and ACPI SRAT table,
1010 * that tables are based on xAPIC ID and QEMU<->SeaBIOS interface
1011 * for CPU hotplug also uses APIC ID and not "CPU index".
1012 * This means that FW_CFG_MAX_CPUS is not the "maximum number of CPUs",
1013 * but the "limit to the APIC ID values SeaBIOS may see".
1014 *
1015 * So for compatibility reasons with old BIOSes we are stuck with
1016 * "etc/max-cpus" actually being apic_id_limit
1017 */
1018 fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)pcms->apic_id_limit);
1019 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
1020 fw_cfg_add_bytes(fw_cfg, FW_CFG_ACPI_TABLES,
1021 acpi_tables, acpi_tables_len);
1022 fw_cfg_add_i32(fw_cfg, FW_CFG_IRQ0_OVERRIDE, kvm_allows_irq0_override());
1023
1024 fw_cfg_add_bytes(fw_cfg, FW_CFG_E820_TABLE,
1025 &e820_reserve, sizeof(e820_reserve));
1026 fw_cfg_add_file(fw_cfg, "etc/e820", e820_table,
1027 sizeof(struct e820_entry) * e820_entries);
1028
1029 fw_cfg_add_bytes(fw_cfg, FW_CFG_HPET, &hpet_cfg, sizeof(hpet_cfg));
1030 /* allocate memory for the NUMA channel: one (64bit) word for the number
1031 * of nodes, one word for each VCPU->node and one word for each node to
1032 * hold the amount of memory.
1033 */
1034 numa_fw_cfg = g_new0(uint64_t, 1 + pcms->apic_id_limit + nb_numa_nodes);
1035 numa_fw_cfg[0] = cpu_to_le64(nb_numa_nodes);
1036 cpus = mc->possible_cpu_arch_ids(MACHINE(pcms));
1037 for (i = 0; i < cpus->len; i++) {
1038 unsigned int apic_id = cpus->cpus[i].arch_id;
1039 assert(apic_id < pcms->apic_id_limit);
1040 numa_fw_cfg[apic_id + 1] = cpu_to_le64(cpus->cpus[i].props.node_id);
1041 }
1042 for (i = 0; i < nb_numa_nodes; i++) {
1043 numa_fw_cfg[pcms->apic_id_limit + 1 + i] =
1044 cpu_to_le64(numa_info[i].node_mem);
1045 }
1046 fw_cfg_add_bytes(fw_cfg, FW_CFG_NUMA, numa_fw_cfg,
1047 (1 + pcms->apic_id_limit + nb_numa_nodes) *
1048 sizeof(*numa_fw_cfg));
1049
1050 return fw_cfg;
1051 }
1052
1053 static long get_file_size(FILE *f)
1054 {
1055 long where, size;
1056
1057 /* XXX: on Unix systems, using fstat() probably makes more sense */
1058
1059 where = ftell(f);
1060 fseek(f, 0, SEEK_END);
1061 size = ftell(f);
1062 fseek(f, where, SEEK_SET);
1063
1064 return size;
1065 }
1066
1067 struct setup_data {
1068 uint64_t next;
1069 uint32_t type;
1070 uint32_t len;
1071 uint8_t data[0];
1072 } __attribute__((packed));
1073
1074
1075 /*
1076 * The entry point into the kernel for PVH boot is different from
1077 * the native entry point. The PVH entry is defined by the x86/HVM
1078 * direct boot ABI and is available in an ELFNOTE in the kernel binary.
1079 *
1080 * This function is passed to load_elf() when it is called from
1081 * load_elfboot() which then additionally checks for an ELF Note of
1082 * type XEN_ELFNOTE_PHYS32_ENTRY and passes it to this function to
1083 * parse the PVH entry address from the ELF Note.
1084 *
1085 * Due to trickery in elf_opts.h, load_elf() is actually available as
1086 * load_elf32() or load_elf64() and this routine needs to be able
1087 * to deal with being called as 32 or 64 bit.
1088 *
1089 * The address of the PVH entry point is saved to the 'pvh_start_addr'
1090 * global variable. (although the entry point is 32-bit, the kernel
1091 * binary can be either 32-bit or 64-bit).
1092 */
1093 static uint64_t read_pvh_start_addr(void *arg1, void *arg2, bool is64)
1094 {
1095 size_t *elf_note_data_addr;
1096
1097 /* Check if ELF Note header passed in is valid */
1098 if (arg1 == NULL) {
1099 return 0;
1100 }
1101
1102 if (is64) {
1103 struct elf64_note *nhdr64 = (struct elf64_note *)arg1;
1104 uint64_t nhdr_size64 = sizeof(struct elf64_note);
1105 uint64_t phdr_align = *(uint64_t *)arg2;
1106 uint64_t nhdr_namesz = nhdr64->n_namesz;
1107
1108 elf_note_data_addr =
1109 ((void *)nhdr64) + nhdr_size64 +
1110 QEMU_ALIGN_UP(nhdr_namesz, phdr_align);
1111 } else {
1112 struct elf32_note *nhdr32 = (struct elf32_note *)arg1;
1113 uint32_t nhdr_size32 = sizeof(struct elf32_note);
1114 uint32_t phdr_align = *(uint32_t *)arg2;
1115 uint32_t nhdr_namesz = nhdr32->n_namesz;
1116
1117 elf_note_data_addr =
1118 ((void *)nhdr32) + nhdr_size32 +
1119 QEMU_ALIGN_UP(nhdr_namesz, phdr_align);
1120 }
1121
1122 pvh_start_addr = *elf_note_data_addr;
1123
1124 return pvh_start_addr;
1125 }
1126
1127 static bool load_elfboot(const char *kernel_filename,
1128 int kernel_file_size,
1129 uint8_t *header,
1130 size_t pvh_xen_start_addr,
1131 FWCfgState *fw_cfg)
1132 {
1133 uint32_t flags = 0;
1134 uint32_t mh_load_addr = 0;
1135 uint32_t elf_kernel_size = 0;
1136 uint64_t elf_entry;
1137 uint64_t elf_low, elf_high;
1138 int kernel_size;
1139
1140 if (ldl_p(header) != 0x464c457f) {
1141 return false; /* no elfboot */
1142 }
1143
1144 bool elf_is64 = header[EI_CLASS] == ELFCLASS64;
1145 flags = elf_is64 ?
1146 ((Elf64_Ehdr *)header)->e_flags : ((Elf32_Ehdr *)header)->e_flags;
1147
1148 if (flags & 0x00010004) { /* LOAD_ELF_HEADER_HAS_ADDR */
1149 error_report("elfboot unsupported flags = %x", flags);
1150 exit(1);
1151 }
1152
1153 uint64_t elf_note_type = XEN_ELFNOTE_PHYS32_ENTRY;
1154 kernel_size = load_elf(kernel_filename, read_pvh_start_addr,
1155 NULL, &elf_note_type, &elf_entry,
1156 &elf_low, &elf_high, 0, I386_ELF_MACHINE,
1157 0, 0);
1158
1159 if (kernel_size < 0) {
1160 error_report("Error while loading elf kernel");
1161 exit(1);
1162 }
1163 mh_load_addr = elf_low;
1164 elf_kernel_size = elf_high - elf_low;
1165
1166 if (pvh_start_addr == 0) {
1167 error_report("Error loading uncompressed kernel without PVH ELF Note");
1168 exit(1);
1169 }
1170 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ENTRY, pvh_start_addr);
1171 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, mh_load_addr);
1172 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, elf_kernel_size);
1173
1174 return true;
1175 }
1176
1177 static void load_linux(PCMachineState *pcms,
1178 FWCfgState *fw_cfg)
1179 {
1180 uint16_t protocol;
1181 int setup_size, kernel_size, cmdline_size;
1182 int dtb_size, setup_data_offset;
1183 uint32_t initrd_max;
1184 uint8_t header[8192], *setup, *kernel;
1185 hwaddr real_addr, prot_addr, cmdline_addr, initrd_addr = 0;
1186 FILE *f;
1187 char *vmode;
1188 MachineState *machine = MACHINE(pcms);
1189 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
1190 struct setup_data *setup_data;
1191 const char *kernel_filename = machine->kernel_filename;
1192 const char *initrd_filename = machine->initrd_filename;
1193 const char *dtb_filename = machine->dtb;
1194 const char *kernel_cmdline = machine->kernel_cmdline;
1195
1196 /* Align to 16 bytes as a paranoia measure */
1197 cmdline_size = (strlen(kernel_cmdline)+16) & ~15;
1198
1199 /* load the kernel header */
1200 f = fopen(kernel_filename, "rb");
1201 if (!f || !(kernel_size = get_file_size(f)) ||
1202 fread(header, 1, MIN(ARRAY_SIZE(header), kernel_size), f) !=
1203 MIN(ARRAY_SIZE(header), kernel_size)) {
1204 fprintf(stderr, "qemu: could not load kernel '%s': %s\n",
1205 kernel_filename, strerror(errno));
1206 exit(1);
1207 }
1208
1209 /* kernel protocol version */
1210 #if 0
1211 fprintf(stderr, "header magic: %#x\n", ldl_p(header+0x202));
1212 #endif
1213 if (ldl_p(header+0x202) == 0x53726448) {
1214 protocol = lduw_p(header+0x206);
1215 } else {
1216 /*
1217 * This could be a multiboot kernel. If it is, let's stop treating it
1218 * like a Linux kernel.
1219 * Note: some multiboot images could be in the ELF format (the same of
1220 * PVH), so we try multiboot first since we check the multiboot magic
1221 * header before to load it.
1222 */
1223 if (load_multiboot(fw_cfg, f, kernel_filename, initrd_filename,
1224 kernel_cmdline, kernel_size, header)) {
1225 return;
1226 }
1227 /*
1228 * Check if the file is an uncompressed kernel file (ELF) and load it,
1229 * saving the PVH entry point used by the x86/HVM direct boot ABI.
1230 * If load_elfboot() is successful, populate the fw_cfg info.
1231 */
1232 if (pcmc->pvh_enabled &&
1233 load_elfboot(kernel_filename, kernel_size,
1234 header, pvh_start_addr, fw_cfg)) {
1235 fclose(f);
1236
1237 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE,
1238 strlen(kernel_cmdline) + 1);
1239 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, kernel_cmdline);
1240
1241 fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_SIZE, sizeof(header));
1242 fw_cfg_add_bytes(fw_cfg, FW_CFG_SETUP_DATA,
1243 header, sizeof(header));
1244
1245 /* load initrd */
1246 if (initrd_filename) {
1247 gsize initrd_size;
1248 gchar *initrd_data;
1249 GError *gerr = NULL;
1250
1251 if (!g_file_get_contents(initrd_filename, &initrd_data,
1252 &initrd_size, &gerr)) {
1253 fprintf(stderr, "qemu: error reading initrd %s: %s\n",
1254 initrd_filename, gerr->message);
1255 exit(1);
1256 }
1257
1258 initrd_max = pcms->below_4g_mem_size - pcmc->acpi_data_size - 1;
1259 if (initrd_size >= initrd_max) {
1260 fprintf(stderr, "qemu: initrd is too large, cannot support."
1261 "(max: %"PRIu32", need %"PRId64")\n",
1262 initrd_max, (uint64_t)initrd_size);
1263 exit(1);
1264 }
1265
1266 initrd_addr = (initrd_max - initrd_size) & ~4095;
1267
1268 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr);
1269 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size);
1270 fw_cfg_add_bytes(fw_cfg, FW_CFG_INITRD_DATA, initrd_data,
1271 initrd_size);
1272 }
1273
1274 option_rom[nb_option_roms].bootindex = 0;
1275 option_rom[nb_option_roms].name = "pvh.bin";
1276 nb_option_roms++;
1277
1278 return;
1279 }
1280 protocol = 0;
1281 }
1282
1283 if (protocol < 0x200 || !(header[0x211] & 0x01)) {
1284 /* Low kernel */
1285 real_addr = 0x90000;
1286 cmdline_addr = 0x9a000 - cmdline_size;
1287 prot_addr = 0x10000;
1288 } else if (protocol < 0x202) {
1289 /* High but ancient kernel */
1290 real_addr = 0x90000;
1291 cmdline_addr = 0x9a000 - cmdline_size;
1292 prot_addr = 0x100000;
1293 } else {
1294 /* High and recent kernel */
1295 real_addr = 0x10000;
1296 cmdline_addr = 0x20000;
1297 prot_addr = 0x100000;
1298 }
1299
1300 #if 0
1301 fprintf(stderr,
1302 "qemu: real_addr = 0x" TARGET_FMT_plx "\n"
1303 "qemu: cmdline_addr = 0x" TARGET_FMT_plx "\n"
1304 "qemu: prot_addr = 0x" TARGET_FMT_plx "\n",
1305 real_addr,
1306 cmdline_addr,
1307 prot_addr);
1308 #endif
1309
1310 /* highest address for loading the initrd */
1311 if (protocol >= 0x20c &&
1312 lduw_p(header+0x236) & XLF_CAN_BE_LOADED_ABOVE_4G) {
1313 /*
1314 * Linux has supported initrd up to 4 GB for a very long time (2007,
1315 * long before XLF_CAN_BE_LOADED_ABOVE_4G which was added in 2013),
1316 * though it only sets initrd_max to 2 GB to "work around bootloader
1317 * bugs". Luckily, QEMU firmware(which does something like bootloader)
1318 * has supported this.
1319 *
1320 * It's believed that if XLF_CAN_BE_LOADED_ABOVE_4G is set, initrd can
1321 * be loaded into any address.
1322 *
1323 * In addition, initrd_max is uint32_t simply because QEMU doesn't
1324 * support the 64-bit boot protocol (specifically the ext_ramdisk_image
1325 * field).
1326 *
1327 * Therefore here just limit initrd_max to UINT32_MAX simply as well.
1328 */
1329 initrd_max = UINT32_MAX;
1330 } else if (protocol >= 0x203) {
1331 initrd_max = ldl_p(header+0x22c);
1332 } else {
1333 initrd_max = 0x37ffffff;
1334 }
1335
1336 if (initrd_max >= pcms->below_4g_mem_size - pcmc->acpi_data_size) {
1337 initrd_max = pcms->below_4g_mem_size - pcmc->acpi_data_size - 1;
1338 }
1339
1340 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_ADDR, cmdline_addr);
1341 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, strlen(kernel_cmdline)+1);
1342 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, kernel_cmdline);
1343
1344 if (protocol >= 0x202) {
1345 stl_p(header+0x228, cmdline_addr);
1346 } else {
1347 stw_p(header+0x20, 0xA33F);
1348 stw_p(header+0x22, cmdline_addr-real_addr);
1349 }
1350
1351 /* handle vga= parameter */
1352 vmode = strstr(kernel_cmdline, "vga=");
1353 if (vmode) {
1354 unsigned int video_mode;
1355 /* skip "vga=" */
1356 vmode += 4;
1357 if (!strncmp(vmode, "normal", 6)) {
1358 video_mode = 0xffff;
1359 } else if (!strncmp(vmode, "ext", 3)) {
1360 video_mode = 0xfffe;
1361 } else if (!strncmp(vmode, "ask", 3)) {
1362 video_mode = 0xfffd;
1363 } else {
1364 video_mode = strtol(vmode, NULL, 0);
1365 }
1366 stw_p(header+0x1fa, video_mode);
1367 }
1368
1369 /* loader type */
1370 /* High nybble = B reserved for QEMU; low nybble is revision number.
1371 If this code is substantially changed, you may want to consider
1372 incrementing the revision. */
1373 if (protocol >= 0x200) {
1374 header[0x210] = 0xB0;
1375 }
1376 /* heap */
1377 if (protocol >= 0x201) {
1378 header[0x211] |= 0x80; /* CAN_USE_HEAP */
1379 stw_p(header+0x224, cmdline_addr-real_addr-0x200);
1380 }
1381
1382 /* load initrd */
1383 if (initrd_filename) {
1384 gsize initrd_size;
1385 gchar *initrd_data;
1386 GError *gerr = NULL;
1387
1388 if (protocol < 0x200) {
1389 fprintf(stderr, "qemu: linux kernel too old to load a ram disk\n");
1390 exit(1);
1391 }
1392
1393 if (!g_file_get_contents(initrd_filename, &initrd_data,
1394 &initrd_size, &gerr)) {
1395 fprintf(stderr, "qemu: error reading initrd %s: %s\n",
1396 initrd_filename, gerr->message);
1397 exit(1);
1398 }
1399 if (initrd_size >= initrd_max) {
1400 fprintf(stderr, "qemu: initrd is too large, cannot support."
1401 "(max: %"PRIu32", need %"PRId64")\n",
1402 initrd_max, (uint64_t)initrd_size);
1403 exit(1);
1404 }
1405
1406 initrd_addr = (initrd_max-initrd_size) & ~4095;
1407
1408 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr);
1409 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size);
1410 fw_cfg_add_bytes(fw_cfg, FW_CFG_INITRD_DATA, initrd_data, initrd_size);
1411
1412 stl_p(header+0x218, initrd_addr);
1413 stl_p(header+0x21c, initrd_size);
1414 }
1415
1416 /* load kernel and setup */
1417 setup_size = header[0x1f1];
1418 if (setup_size == 0) {
1419 setup_size = 4;
1420 }
1421 setup_size = (setup_size+1)*512;
1422 if (setup_size > kernel_size) {
1423 fprintf(stderr, "qemu: invalid kernel header\n");
1424 exit(1);
1425 }
1426 kernel_size -= setup_size;
1427
1428 setup = g_malloc(setup_size);
1429 kernel = g_malloc(kernel_size);
1430 fseek(f, 0, SEEK_SET);
1431 if (fread(setup, 1, setup_size, f) != setup_size) {
1432 fprintf(stderr, "fread() failed\n");
1433 exit(1);
1434 }
1435 if (fread(kernel, 1, kernel_size, f) != kernel_size) {
1436 fprintf(stderr, "fread() failed\n");
1437 exit(1);
1438 }
1439 fclose(f);
1440
1441 /* append dtb to kernel */
1442 if (dtb_filename) {
1443 if (protocol < 0x209) {
1444 fprintf(stderr, "qemu: Linux kernel too old to load a dtb\n");
1445 exit(1);
1446 }
1447
1448 dtb_size = get_image_size(dtb_filename);
1449 if (dtb_size <= 0) {
1450 fprintf(stderr, "qemu: error reading dtb %s: %s\n",
1451 dtb_filename, strerror(errno));
1452 exit(1);
1453 }
1454
1455 setup_data_offset = QEMU_ALIGN_UP(kernel_size, 16);
1456 kernel_size = setup_data_offset + sizeof(struct setup_data) + dtb_size;
1457 kernel = g_realloc(kernel, kernel_size);
1458
1459 stq_p(header+0x250, prot_addr + setup_data_offset);
1460
1461 setup_data = (struct setup_data *)(kernel + setup_data_offset);
1462 setup_data->next = 0;
1463 setup_data->type = cpu_to_le32(SETUP_DTB);
1464 setup_data->len = cpu_to_le32(dtb_size);
1465
1466 load_image_size(dtb_filename, setup_data->data, dtb_size);
1467 }
1468
1469 memcpy(setup, header, MIN(sizeof(header), setup_size));
1470
1471 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, prot_addr);
1472 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
1473 fw_cfg_add_bytes(fw_cfg, FW_CFG_KERNEL_DATA, kernel, kernel_size);
1474
1475 fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_ADDR, real_addr);
1476 fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_SIZE, setup_size);
1477 fw_cfg_add_bytes(fw_cfg, FW_CFG_SETUP_DATA, setup, setup_size);
1478
1479 option_rom[nb_option_roms].bootindex = 0;
1480 option_rom[nb_option_roms].name = "linuxboot.bin";
1481 if (pcmc->linuxboot_dma_enabled && fw_cfg_dma_enabled(fw_cfg)) {
1482 option_rom[nb_option_roms].name = "linuxboot_dma.bin";
1483 }
1484 nb_option_roms++;
1485 }
1486
1487 #define NE2000_NB_MAX 6
1488
1489 static const int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360,
1490 0x280, 0x380 };
1491 static const int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 };
1492
1493 void pc_init_ne2k_isa(ISABus *bus, NICInfo *nd)
1494 {
1495 static int nb_ne2k = 0;
1496
1497 if (nb_ne2k == NE2000_NB_MAX)
1498 return;
1499 isa_ne2000_init(bus, ne2000_io[nb_ne2k],
1500 ne2000_irq[nb_ne2k], nd);
1501 nb_ne2k++;
1502 }
1503
1504 DeviceState *cpu_get_current_apic(void)
1505 {
1506 if (current_cpu) {
1507 X86CPU *cpu = X86_CPU(current_cpu);
1508 return cpu->apic_state;
1509 } else {
1510 return NULL;
1511 }
1512 }
1513
1514 void pc_acpi_smi_interrupt(void *opaque, int irq, int level)
1515 {
1516 X86CPU *cpu = opaque;
1517
1518 if (level) {
1519 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
1520 }
1521 }
1522
1523 static void pc_new_cpu(PCMachineState *pcms, int64_t apic_id, Error **errp)
1524 {
1525 Object *cpu = NULL;
1526 Error *local_err = NULL;
1527 CPUX86State *env = NULL;
1528
1529 cpu = object_new(MACHINE(pcms)->cpu_type);
1530
1531 env = &X86_CPU(cpu)->env;
1532 env->nr_dies = pcms->smp_dies;
1533
1534 object_property_set_uint(cpu, apic_id, "apic-id", &local_err);
1535 object_property_set_bool(cpu, true, "realized", &local_err);
1536
1537 object_unref(cpu);
1538 error_propagate(errp, local_err);
1539 }
1540
1541 /*
1542 * This function is very similar to smp_parse()
1543 * in hw/core/machine.c but includes CPU die support.
1544 */
1545 void pc_smp_parse(MachineState *ms, QemuOpts *opts)
1546 {
1547 PCMachineState *pcms = PC_MACHINE(ms);
1548
1549 if (opts) {
1550 unsigned cpus = qemu_opt_get_number(opts, "cpus", 0);
1551 unsigned sockets = qemu_opt_get_number(opts, "sockets", 0);
1552 unsigned dies = qemu_opt_get_number(opts, "dies", 1);
1553 unsigned cores = qemu_opt_get_number(opts, "cores", 0);
1554 unsigned threads = qemu_opt_get_number(opts, "threads", 0);
1555
1556 /* compute missing values, prefer sockets over cores over threads */
1557 if (cpus == 0 || sockets == 0) {
1558 cores = cores > 0 ? cores : 1;
1559 threads = threads > 0 ? threads : 1;
1560 if (cpus == 0) {
1561 sockets = sockets > 0 ? sockets : 1;
1562 cpus = cores * threads * dies * sockets;
1563 } else {
1564 ms->smp.max_cpus =
1565 qemu_opt_get_number(opts, "maxcpus", cpus);
1566 sockets = ms->smp.max_cpus / (cores * threads * dies);
1567 }
1568 } else if (cores == 0) {
1569 threads = threads > 0 ? threads : 1;
1570 cores = cpus / (sockets * dies * threads);
1571 cores = cores > 0 ? cores : 1;
1572 } else if (threads == 0) {
1573 threads = cpus / (cores * dies * sockets);
1574 threads = threads > 0 ? threads : 1;
1575 } else if (sockets * dies * cores * threads < cpus) {
1576 error_report("cpu topology: "
1577 "sockets (%u) * dies (%u) * cores (%u) * threads (%u) < "
1578 "smp_cpus (%u)",
1579 sockets, dies, cores, threads, cpus);
1580 exit(1);
1581 }
1582
1583 ms->smp.max_cpus =
1584 qemu_opt_get_number(opts, "maxcpus", cpus);
1585
1586 if (ms->smp.max_cpus < cpus) {
1587 error_report("maxcpus must be equal to or greater than smp");
1588 exit(1);
1589 }
1590
1591 if (sockets * dies * cores * threads > ms->smp.max_cpus) {
1592 error_report("cpu topology: "
1593 "sockets (%u) * dies (%u) * cores (%u) * threads (%u) > "
1594 "maxcpus (%u)",
1595 sockets, dies, cores, threads,
1596 ms->smp.max_cpus);
1597 exit(1);
1598 }
1599
1600 if (sockets * dies * cores * threads != ms->smp.max_cpus) {
1601 warn_report("Invalid CPU topology deprecated: "
1602 "sockets (%u) * dies (%u) * cores (%u) * threads (%u) "
1603 "!= maxcpus (%u)",
1604 sockets, dies, cores, threads,
1605 ms->smp.max_cpus);
1606 }
1607
1608 ms->smp.cpus = cpus;
1609 ms->smp.cores = cores;
1610 ms->smp.threads = threads;
1611 pcms->smp_dies = dies;
1612 }
1613
1614 if (ms->smp.cpus > 1) {
1615 Error *blocker = NULL;
1616 error_setg(&blocker, QERR_REPLAY_NOT_SUPPORTED, "smp");
1617 replay_add_blocker(blocker);
1618 }
1619 }
1620
1621 void pc_hot_add_cpu(MachineState *ms, const int64_t id, Error **errp)
1622 {
1623 PCMachineState *pcms = PC_MACHINE(ms);
1624 int64_t apic_id = x86_cpu_apic_id_from_index(pcms, id);
1625 Error *local_err = NULL;
1626
1627 if (id < 0) {
1628 error_setg(errp, "Invalid CPU id: %" PRIi64, id);
1629 return;
1630 }
1631
1632 if (apic_id >= ACPI_CPU_HOTPLUG_ID_LIMIT) {
1633 error_setg(errp, "Unable to add CPU: %" PRIi64
1634 ", resulting APIC ID (%" PRIi64 ") is too large",
1635 id, apic_id);
1636 return;
1637 }
1638
1639 pc_new_cpu(PC_MACHINE(ms), apic_id, &local_err);
1640 if (local_err) {
1641 error_propagate(errp, local_err);
1642 return;
1643 }
1644 }
1645
1646 void pc_cpus_init(PCMachineState *pcms)
1647 {
1648 int i;
1649 const CPUArchIdList *possible_cpus;
1650 MachineState *ms = MACHINE(pcms);
1651 MachineClass *mc = MACHINE_GET_CLASS(pcms);
1652 PCMachineClass *pcmc = PC_MACHINE_CLASS(mc);
1653
1654 x86_cpu_set_default_version(pcmc->default_cpu_version);
1655
1656 /* Calculates the limit to CPU APIC ID values
1657 *
1658 * Limit for the APIC ID value, so that all
1659 * CPU APIC IDs are < pcms->apic_id_limit.
1660 *
1661 * This is used for FW_CFG_MAX_CPUS. See comments on bochs_bios_init().
1662 */
1663 pcms->apic_id_limit = x86_cpu_apic_id_from_index(pcms,
1664 ms->smp.max_cpus - 1) + 1;
1665 possible_cpus = mc->possible_cpu_arch_ids(ms);
1666 for (i = 0; i < ms->smp.cpus; i++) {
1667 pc_new_cpu(pcms, possible_cpus->cpus[i].arch_id, &error_fatal);
1668 }
1669 }
1670
1671 static void pc_build_feature_control_file(PCMachineState *pcms)
1672 {
1673 MachineState *ms = MACHINE(pcms);
1674 X86CPU *cpu = X86_CPU(ms->possible_cpus->cpus[0].cpu);
1675 CPUX86State *env = &cpu->env;
1676 uint32_t unused, ecx, edx;
1677 uint64_t feature_control_bits = 0;
1678 uint64_t *val;
1679
1680 cpu_x86_cpuid(env, 1, 0, &unused, &unused, &ecx, &edx);
1681 if (ecx & CPUID_EXT_VMX) {
1682 feature_control_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
1683 }
1684
1685 if ((edx & (CPUID_EXT2_MCE | CPUID_EXT2_MCA)) ==
1686 (CPUID_EXT2_MCE | CPUID_EXT2_MCA) &&
1687 (env->mcg_cap & MCG_LMCE_P)) {
1688 feature_control_bits |= FEATURE_CONTROL_LMCE;
1689 }
1690
1691 if (!feature_control_bits) {
1692 return;
1693 }
1694
1695 val = g_malloc(sizeof(*val));
1696 *val = cpu_to_le64(feature_control_bits | FEATURE_CONTROL_LOCKED);
1697 fw_cfg_add_file(pcms->fw_cfg, "etc/msr_feature_control", val, sizeof(*val));
1698 }
1699
1700 static void rtc_set_cpus_count(ISADevice *rtc, uint16_t cpus_count)
1701 {
1702 if (cpus_count > 0xff) {
1703 /* If the number of CPUs can't be represented in 8 bits, the
1704 * BIOS must use "FW_CFG_NB_CPUS". Set RTC field to 0 just
1705 * to make old BIOSes fail more predictably.
1706 */
1707 rtc_set_memory(rtc, 0x5f, 0);
1708 } else {
1709 rtc_set_memory(rtc, 0x5f, cpus_count - 1);
1710 }
1711 }
1712
1713 static
1714 void pc_machine_done(Notifier *notifier, void *data)
1715 {
1716 PCMachineState *pcms = container_of(notifier,
1717 PCMachineState, machine_done);
1718 PCIBus *bus = pcms->bus;
1719
1720 /* set the number of CPUs */
1721 rtc_set_cpus_count(pcms->rtc, pcms->boot_cpus);
1722
1723 if (bus) {
1724 int extra_hosts = 0;
1725
1726 QLIST_FOREACH(bus, &bus->child, sibling) {
1727 /* look for expander root buses */
1728 if (pci_bus_is_root(bus)) {
1729 extra_hosts++;
1730 }
1731 }
1732 if (extra_hosts && pcms->fw_cfg) {
1733 uint64_t *val = g_malloc(sizeof(*val));
1734 *val = cpu_to_le64(extra_hosts);
1735 fw_cfg_add_file(pcms->fw_cfg,
1736 "etc/extra-pci-roots", val, sizeof(*val));
1737 }
1738 }
1739
1740 acpi_setup();
1741 if (pcms->fw_cfg) {
1742 pc_build_smbios(pcms);
1743 pc_build_feature_control_file(pcms);
1744 /* update FW_CFG_NB_CPUS to account for -device added CPUs */
1745 fw_cfg_modify_i16(pcms->fw_cfg, FW_CFG_NB_CPUS, pcms->boot_cpus);
1746 }
1747
1748 if (pcms->apic_id_limit > 255 && !xen_enabled()) {
1749 IntelIOMMUState *iommu = INTEL_IOMMU_DEVICE(x86_iommu_get_default());
1750
1751 if (!iommu || !x86_iommu_ir_supported(X86_IOMMU_DEVICE(iommu)) ||
1752 iommu->intr_eim != ON_OFF_AUTO_ON) {
1753 error_report("current -smp configuration requires "
1754 "Extended Interrupt Mode enabled. "
1755 "You can add an IOMMU using: "
1756 "-device intel-iommu,intremap=on,eim=on");
1757 exit(EXIT_FAILURE);
1758 }
1759 }
1760 }
1761
1762 void pc_guest_info_init(PCMachineState *pcms)
1763 {
1764 int i;
1765
1766 pcms->apic_xrupt_override = kvm_allows_irq0_override();
1767 pcms->numa_nodes = nb_numa_nodes;
1768 pcms->node_mem = g_malloc0(pcms->numa_nodes *
1769 sizeof *pcms->node_mem);
1770 for (i = 0; i < nb_numa_nodes; i++) {
1771 pcms->node_mem[i] = numa_info[i].node_mem;
1772 }
1773
1774 pcms->machine_done.notify = pc_machine_done;
1775 qemu_add_machine_init_done_notifier(&pcms->machine_done);
1776 }
1777
1778 /* setup pci memory address space mapping into system address space */
1779 void pc_pci_as_mapping_init(Object *owner, MemoryRegion *system_memory,
1780 MemoryRegion *pci_address_space)
1781 {
1782 /* Set to lower priority than RAM */
1783 memory_region_add_subregion_overlap(system_memory, 0x0,
1784 pci_address_space, -1);
1785 }
1786
1787 void xen_load_linux(PCMachineState *pcms)
1788 {
1789 int i;
1790 FWCfgState *fw_cfg;
1791
1792 assert(MACHINE(pcms)->kernel_filename != NULL);
1793
1794 fw_cfg = fw_cfg_init_io(FW_CFG_IO_BASE);
1795 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, pcms->boot_cpus);
1796 rom_set_fw(fw_cfg);
1797
1798 load_linux(pcms, fw_cfg);
1799 for (i = 0; i < nb_option_roms; i++) {
1800 assert(!strcmp(option_rom[i].name, "linuxboot.bin") ||
1801 !strcmp(option_rom[i].name, "linuxboot_dma.bin") ||
1802 !strcmp(option_rom[i].name, "pvh.bin") ||
1803 !strcmp(option_rom[i].name, "multiboot.bin"));
1804 rom_add_option(option_rom[i].name, option_rom[i].bootindex);
1805 }
1806 pcms->fw_cfg = fw_cfg;
1807 }
1808
1809 void pc_memory_init(PCMachineState *pcms,
1810 MemoryRegion *system_memory,
1811 MemoryRegion *rom_memory,
1812 MemoryRegion **ram_memory)
1813 {
1814 int linux_boot, i;
1815 MemoryRegion *ram, *option_rom_mr;
1816 MemoryRegion *ram_below_4g, *ram_above_4g;
1817 FWCfgState *fw_cfg;
1818 MachineState *machine = MACHINE(pcms);
1819 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
1820
1821 assert(machine->ram_size == pcms->below_4g_mem_size +
1822 pcms->above_4g_mem_size);
1823
1824 linux_boot = (machine->kernel_filename != NULL);
1825
1826 /* Allocate RAM. We allocate it as a single memory region and use
1827 * aliases to address portions of it, mostly for backwards compatibility
1828 * with older qemus that used qemu_ram_alloc().
1829 */
1830 ram = g_malloc(sizeof(*ram));
1831 memory_region_allocate_system_memory(ram, NULL, "pc.ram",
1832 machine->ram_size);
1833 *ram_memory = ram;
1834 ram_below_4g = g_malloc(sizeof(*ram_below_4g));
1835 memory_region_init_alias(ram_below_4g, NULL, "ram-below-4g", ram,
1836 0, pcms->below_4g_mem_size);
1837 memory_region_add_subregion(system_memory, 0, ram_below_4g);
1838 e820_add_entry(0, pcms->below_4g_mem_size, E820_RAM);
1839 if (pcms->above_4g_mem_size > 0) {
1840 ram_above_4g = g_malloc(sizeof(*ram_above_4g));
1841 memory_region_init_alias(ram_above_4g, NULL, "ram-above-4g", ram,
1842 pcms->below_4g_mem_size,
1843 pcms->above_4g_mem_size);
1844 memory_region_add_subregion(system_memory, 0x100000000ULL,
1845 ram_above_4g);
1846 e820_add_entry(0x100000000ULL, pcms->above_4g_mem_size, E820_RAM);
1847 }
1848
1849 if (!pcmc->has_reserved_memory &&
1850 (machine->ram_slots ||
1851 (machine->maxram_size > machine->ram_size))) {
1852 MachineClass *mc = MACHINE_GET_CLASS(machine);
1853
1854 error_report("\"-memory 'slots|maxmem'\" is not supported by: %s",
1855 mc->name);
1856 exit(EXIT_FAILURE);
1857 }
1858
1859 /* always allocate the device memory information */
1860 machine->device_memory = g_malloc0(sizeof(*machine->device_memory));
1861
1862 /* initialize device memory address space */
1863 if (pcmc->has_reserved_memory &&
1864 (machine->ram_size < machine->maxram_size)) {
1865 ram_addr_t device_mem_size = machine->maxram_size - machine->ram_size;
1866
1867 if (machine->ram_slots > ACPI_MAX_RAM_SLOTS) {
1868 error_report("unsupported amount of memory slots: %"PRIu64,
1869 machine->ram_slots);
1870 exit(EXIT_FAILURE);
1871 }
1872
1873 if (QEMU_ALIGN_UP(machine->maxram_size,
1874 TARGET_PAGE_SIZE) != machine->maxram_size) {
1875 error_report("maximum memory size must by aligned to multiple of "
1876 "%d bytes", TARGET_PAGE_SIZE);
1877 exit(EXIT_FAILURE);
1878 }
1879
1880 machine->device_memory->base =
1881 ROUND_UP(0x100000000ULL + pcms->above_4g_mem_size, 1 * GiB);
1882
1883 if (pcmc->enforce_aligned_dimm) {
1884 /* size device region assuming 1G page max alignment per slot */
1885 device_mem_size += (1 * GiB) * machine->ram_slots;
1886 }
1887
1888 if ((machine->device_memory->base + device_mem_size) <
1889 device_mem_size) {
1890 error_report("unsupported amount of maximum memory: " RAM_ADDR_FMT,
1891 machine->maxram_size);
1892 exit(EXIT_FAILURE);
1893 }
1894
1895 memory_region_init(&machine->device_memory->mr, OBJECT(pcms),
1896 "device-memory", device_mem_size);
1897 memory_region_add_subregion(system_memory, machine->device_memory->base,
1898 &machine->device_memory->mr);
1899 }
1900
1901 /* Initialize PC system firmware */
1902 pc_system_firmware_init(pcms, rom_memory);
1903
1904 option_rom_mr = g_malloc(sizeof(*option_rom_mr));
1905 memory_region_init_ram(option_rom_mr, NULL, "pc.rom", PC_ROM_SIZE,
1906 &error_fatal);
1907 if (pcmc->pci_enabled) {
1908 memory_region_set_readonly(option_rom_mr, true);
1909 }
1910 memory_region_add_subregion_overlap(rom_memory,
1911 PC_ROM_MIN_VGA,
1912 option_rom_mr,
1913 1);
1914
1915 fw_cfg = bochs_bios_init(&address_space_memory, pcms);
1916
1917 rom_set_fw(fw_cfg);
1918
1919 if (pcmc->has_reserved_memory && machine->device_memory->base) {
1920 uint64_t *val = g_malloc(sizeof(*val));
1921 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
1922 uint64_t res_mem_end = machine->device_memory->base;
1923
1924 if (!pcmc->broken_reserved_end) {
1925 res_mem_end += memory_region_size(&machine->device_memory->mr);
1926 }
1927 *val = cpu_to_le64(ROUND_UP(res_mem_end, 1 * GiB));
1928 fw_cfg_add_file(fw_cfg, "etc/reserved-memory-end", val, sizeof(*val));
1929 }
1930
1931 if (linux_boot) {
1932 load_linux(pcms, fw_cfg);
1933 }
1934
1935 for (i = 0; i < nb_option_roms; i++) {
1936 rom_add_option(option_rom[i].name, option_rom[i].bootindex);
1937 }
1938 pcms->fw_cfg = fw_cfg;
1939
1940 /* Init default IOAPIC address space */
1941 pcms->ioapic_as = &address_space_memory;
1942 }
1943
1944 /*
1945 * The 64bit pci hole starts after "above 4G RAM" and
1946 * potentially the space reserved for memory hotplug.
1947 */
1948 uint64_t pc_pci_hole64_start(void)
1949 {
1950 PCMachineState *pcms = PC_MACHINE(qdev_get_machine());
1951 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
1952 MachineState *ms = MACHINE(pcms);
1953 uint64_t hole64_start = 0;
1954
1955 if (pcmc->has_reserved_memory && ms->device_memory->base) {
1956 hole64_start = ms->device_memory->base;
1957 if (!pcmc->broken_reserved_end) {
1958 hole64_start += memory_region_size(&ms->device_memory->mr);
1959 }
1960 } else {
1961 hole64_start = 0x100000000ULL + pcms->above_4g_mem_size;
1962 }
1963
1964 return ROUND_UP(hole64_start, 1 * GiB);
1965 }
1966
1967 qemu_irq pc_allocate_cpu_irq(void)
1968 {
1969 return qemu_allocate_irq(pic_irq_request, NULL, 0);
1970 }
1971
1972 DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus)
1973 {
1974 DeviceState *dev = NULL;
1975
1976 rom_set_order_override(FW_CFG_ORDER_OVERRIDE_VGA);
1977 if (pci_bus) {
1978 PCIDevice *pcidev = pci_vga_init(pci_bus);
1979 dev = pcidev ? &pcidev->qdev : NULL;
1980 } else if (isa_bus) {
1981 ISADevice *isadev = isa_vga_init(isa_bus);
1982 dev = isadev ? DEVICE(isadev) : NULL;
1983 }
1984 rom_reset_order_override();
1985 return dev;
1986 }
1987
1988 static const MemoryRegionOps ioport80_io_ops = {
1989 .write = ioport80_write,
1990 .read = ioport80_read,
1991 .endianness = DEVICE_NATIVE_ENDIAN,
1992 .impl = {
1993 .min_access_size = 1,
1994 .max_access_size = 1,
1995 },
1996 };
1997
1998 static const MemoryRegionOps ioportF0_io_ops = {
1999 .write = ioportF0_write,
2000 .read = ioportF0_read,
2001 .endianness = DEVICE_NATIVE_ENDIAN,
2002 .impl = {
2003 .min_access_size = 1,
2004 .max_access_size = 1,
2005 },
2006 };
2007
2008 static void pc_superio_init(ISABus *isa_bus, bool create_fdctrl, bool no_vmport)
2009 {
2010 int i;
2011 DriveInfo *fd[MAX_FD];
2012 qemu_irq *a20_line;
2013 ISADevice *i8042, *port92, *vmmouse;
2014
2015 serial_hds_isa_init(isa_bus, 0, MAX_ISA_SERIAL_PORTS);
2016 parallel_hds_isa_init(isa_bus, MAX_PARALLEL_PORTS);
2017
2018 for (i = 0; i < MAX_FD; i++) {
2019 fd[i] = drive_get(IF_FLOPPY, 0, i);
2020 create_fdctrl |= !!fd[i];
2021 }
2022 if (create_fdctrl) {
2023 fdctrl_init_isa(isa_bus, fd);
2024 }
2025
2026 i8042 = isa_create_simple(isa_bus, "i8042");
2027 if (!no_vmport) {
2028 vmport_init(isa_bus);
2029 vmmouse = isa_try_create(isa_bus, "vmmouse");
2030 } else {
2031 vmmouse = NULL;
2032 }
2033 if (vmmouse) {
2034 DeviceState *dev = DEVICE(vmmouse);
2035 qdev_prop_set_ptr(dev, "ps2_mouse", i8042);
2036 qdev_init_nofail(dev);
2037 }
2038 port92 = isa_create_simple(isa_bus, "port92");
2039
2040 a20_line = qemu_allocate_irqs(handle_a20_line_change, first_cpu, 2);
2041 i8042_setup_a20_line(i8042, a20_line[0]);
2042 port92_init(port92, a20_line[1]);
2043 g_free(a20_line);
2044 }
2045
2046 void pc_basic_device_init(ISABus *isa_bus, qemu_irq *gsi,
2047 ISADevice **rtc_state,
2048 bool create_fdctrl,
2049 bool no_vmport,
2050 bool has_pit,
2051 uint32_t hpet_irqs)
2052 {
2053 int i;
2054 DeviceState *hpet = NULL;
2055 int pit_isa_irq = 0;
2056 qemu_irq pit_alt_irq = NULL;
2057 qemu_irq rtc_irq = NULL;
2058 ISADevice *pit = NULL;
2059 MemoryRegion *ioport80_io = g_new(MemoryRegion, 1);
2060 MemoryRegion *ioportF0_io = g_new(MemoryRegion, 1);
2061
2062 memory_region_init_io(ioport80_io, NULL, &ioport80_io_ops, NULL, "ioport80", 1);
2063 memory_region_add_subregion(isa_bus->address_space_io, 0x80, ioport80_io);
2064
2065 memory_region_init_io(ioportF0_io, NULL, &ioportF0_io_ops, NULL, "ioportF0", 1);
2066 memory_region_add_subregion(isa_bus->address_space_io, 0xf0, ioportF0_io);
2067
2068 /*
2069 * Check if an HPET shall be created.
2070 *
2071 * Without KVM_CAP_PIT_STATE2, we cannot switch off the in-kernel PIT
2072 * when the HPET wants to take over. Thus we have to disable the latter.
2073 */
2074 if (!no_hpet && (!kvm_irqchip_in_kernel() || kvm_has_pit_state2())) {
2075 /* In order to set property, here not using sysbus_try_create_simple */
2076 hpet = qdev_try_create(NULL, TYPE_HPET);
2077 if (hpet) {
2078 /* For pc-piix-*, hpet's intcap is always IRQ2. For pc-q35-1.7
2079 * and earlier, use IRQ2 for compat. Otherwise, use IRQ16~23,
2080 * IRQ8 and IRQ2.
2081 */
2082 uint8_t compat = object_property_get_uint(OBJECT(hpet),
2083 HPET_INTCAP, NULL);
2084 if (!compat) {
2085 qdev_prop_set_uint32(hpet, HPET_INTCAP, hpet_irqs);
2086 }
2087 qdev_init_nofail(hpet);
2088 sysbus_mmio_map(SYS_BUS_DEVICE(hpet), 0, HPET_BASE);
2089
2090 for (i = 0; i < GSI_NUM_PINS; i++) {
2091 sysbus_connect_irq(SYS_BUS_DEVICE(hpet), i, gsi[i]);
2092 }
2093 pit_isa_irq = -1;
2094 pit_alt_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_PIT_INT);
2095 rtc_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_RTC_INT);
2096 }
2097 }
2098 *rtc_state = mc146818_rtc_init(isa_bus, 2000, rtc_irq);
2099
2100 qemu_register_boot_set(pc_boot_set, *rtc_state);
2101
2102 if (!xen_enabled() && has_pit) {
2103 if (kvm_pit_in_kernel()) {
2104 pit = kvm_pit_init(isa_bus, 0x40);
2105 } else {
2106 pit = i8254_pit_init(isa_bus, 0x40, pit_isa_irq, pit_alt_irq);
2107 }
2108 if (hpet) {
2109 /* connect PIT to output control line of the HPET */
2110 qdev_connect_gpio_out(hpet, 0, qdev_get_gpio_in(DEVICE(pit), 0));
2111 }
2112 pcspk_init(isa_bus, pit);
2113 }
2114
2115 i8257_dma_init(isa_bus, 0);
2116
2117 /* Super I/O */
2118 pc_superio_init(isa_bus, create_fdctrl, no_vmport);
2119 }
2120
2121 void pc_nic_init(PCMachineClass *pcmc, ISABus *isa_bus, PCIBus *pci_bus)
2122 {
2123 int i;
2124
2125 rom_set_order_override(FW_CFG_ORDER_OVERRIDE_NIC);
2126 for (i = 0; i < nb_nics; i++) {
2127 NICInfo *nd = &nd_table[i];
2128 const char *model = nd->model ? nd->model : pcmc->default_nic_model;
2129
2130 if (g_str_equal(model, "ne2k_isa")) {
2131 pc_init_ne2k_isa(isa_bus, nd);
2132 } else {
2133 pci_nic_init_nofail(nd, pci_bus, model, NULL);
2134 }
2135 }
2136 rom_reset_order_override();
2137 }
2138
2139 void ioapic_init_gsi(GSIState *gsi_state, const char *parent_name)
2140 {
2141 DeviceState *dev;
2142 SysBusDevice *d;
2143 unsigned int i;
2144
2145 if (kvm_ioapic_in_kernel()) {
2146 dev = qdev_create(NULL, TYPE_KVM_IOAPIC);
2147 } else {
2148 dev = qdev_create(NULL, TYPE_IOAPIC);
2149 }
2150 if (parent_name) {
2151 object_property_add_child(object_resolve_path(parent_name, NULL),
2152 "ioapic", OBJECT(dev), NULL);
2153 }
2154 qdev_init_nofail(dev);
2155 d = SYS_BUS_DEVICE(dev);
2156 sysbus_mmio_map(d, 0, IO_APIC_DEFAULT_ADDRESS);
2157
2158 for (i = 0; i < IOAPIC_NUM_PINS; i++) {
2159 gsi_state->ioapic_irq[i] = qdev_get_gpio_in(dev, i);
2160 }
2161 }
2162
2163 static void pc_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
2164 Error **errp)
2165 {
2166 const PCMachineState *pcms = PC_MACHINE(hotplug_dev);
2167 const PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
2168 const MachineState *ms = MACHINE(hotplug_dev);
2169 const bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM);
2170 const uint64_t legacy_align = TARGET_PAGE_SIZE;
2171 Error *local_err = NULL;
2172
2173 /*
2174 * When -no-acpi is used with Q35 machine type, no ACPI is built,
2175 * but pcms->acpi_dev is still created. Check !acpi_enabled in
2176 * addition to cover this case.
2177 */
2178 if (!pcms->acpi_dev || !acpi_enabled) {
2179 error_setg(errp,
2180 "memory hotplug is not enabled: missing acpi device or acpi disabled");
2181 return;
2182 }
2183
2184 if (is_nvdimm && !ms->nvdimms_state->is_enabled) {
2185 error_setg(errp, "nvdimm is not enabled: missing 'nvdimm' in '-M'");
2186 return;
2187 }
2188
2189 hotplug_handler_pre_plug(pcms->acpi_dev, dev, &local_err);
2190 if (local_err) {
2191 error_propagate(errp, local_err);
2192 return;
2193 }
2194
2195 pc_dimm_pre_plug(PC_DIMM(dev), MACHINE(hotplug_dev),
2196 pcmc->enforce_aligned_dimm ? NULL : &legacy_align, errp);
2197 }
2198
2199 static void pc_memory_plug(HotplugHandler *hotplug_dev,
2200 DeviceState *dev, Error **errp)
2201 {
2202 Error *local_err = NULL;
2203 PCMachineState *pcms = PC_MACHINE(hotplug_dev);
2204 MachineState *ms = MACHINE(hotplug_dev);
2205 bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM);
2206
2207 pc_dimm_plug(PC_DIMM(dev), MACHINE(pcms), &local_err);
2208 if (local_err) {
2209 goto out;
2210 }
2211
2212 if (is_nvdimm) {
2213 nvdimm_plug(ms->nvdimms_state);
2214 }
2215
2216 hotplug_handler_plug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &error_abort);
2217 out:
2218 error_propagate(errp, local_err);
2219 }
2220
2221 static void pc_memory_unplug_request(HotplugHandler *hotplug_dev,
2222 DeviceState *dev, Error **errp)
2223 {
2224 Error *local_err = NULL;
2225 PCMachineState *pcms = PC_MACHINE(hotplug_dev);
2226
2227 /*
2228 * When -no-acpi is used with Q35 machine type, no ACPI is built,
2229 * but pcms->acpi_dev is still created. Check !acpi_enabled in
2230 * addition to cover this case.
2231 */
2232 if (!pcms->acpi_dev || !acpi_enabled) {
2233 error_setg(&local_err,
2234 "memory hotplug is not enabled: missing acpi device or acpi disabled");
2235 goto out;
2236 }
2237
2238 if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) {
2239 error_setg(&local_err,
2240 "nvdimm device hot unplug is not supported yet.");
2241 goto out;
2242 }
2243
2244 hotplug_handler_unplug_request(HOTPLUG_HANDLER(pcms->acpi_dev), dev,
2245 &local_err);
2246 out:
2247 error_propagate(errp, local_err);
2248 }
2249
2250 static void pc_memory_unplug(HotplugHandler *hotplug_dev,
2251 DeviceState *dev, Error **errp)
2252 {
2253 PCMachineState *pcms = PC_MACHINE(hotplug_dev);
2254 Error *local_err = NULL;
2255
2256 hotplug_handler_unplug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err);
2257 if (local_err) {
2258 goto out;
2259 }
2260
2261 pc_dimm_unplug(PC_DIMM(dev), MACHINE(pcms));
2262 object_property_set_bool(OBJECT(dev), false, "realized", NULL);
2263 out:
2264 error_propagate(errp, local_err);
2265 }
2266
2267 static int pc_apic_cmp(const void *a, const void *b)
2268 {
2269 CPUArchId *apic_a = (CPUArchId *)a;
2270 CPUArchId *apic_b = (CPUArchId *)b;
2271
2272 return apic_a->arch_id - apic_b->arch_id;
2273 }
2274
2275 /* returns pointer to CPUArchId descriptor that matches CPU's apic_id
2276 * in ms->possible_cpus->cpus, if ms->possible_cpus->cpus has no
2277 * entry corresponding to CPU's apic_id returns NULL.
2278 */
2279 static CPUArchId *pc_find_cpu_slot(MachineState *ms, uint32_t id, int *idx)
2280 {
2281 CPUArchId apic_id, *found_cpu;
2282
2283 apic_id.arch_id = id;
2284 found_cpu = bsearch(&apic_id, ms->possible_cpus->cpus,
2285 ms->possible_cpus->len, sizeof(*ms->possible_cpus->cpus),
2286 pc_apic_cmp);
2287 if (found_cpu && idx) {
2288 *idx = found_cpu - ms->possible_cpus->cpus;
2289 }
2290 return found_cpu;
2291 }
2292
2293 static void pc_cpu_plug(HotplugHandler *hotplug_dev,
2294 DeviceState *dev, Error **errp)
2295 {
2296 CPUArchId *found_cpu;
2297 Error *local_err = NULL;
2298 X86CPU *cpu = X86_CPU(dev);
2299 PCMachineState *pcms = PC_MACHINE(hotplug_dev);
2300
2301 if (pcms->acpi_dev) {
2302 hotplug_handler_plug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err);
2303 if (local_err) {
2304 goto out;
2305 }
2306 }
2307
2308 /* increment the number of CPUs */
2309 pcms->boot_cpus++;
2310 if (pcms->rtc) {
2311 rtc_set_cpus_count(pcms->rtc, pcms->boot_cpus);
2312 }
2313 if (pcms->fw_cfg) {
2314 fw_cfg_modify_i16(pcms->fw_cfg, FW_CFG_NB_CPUS, pcms->boot_cpus);
2315 }
2316
2317 found_cpu = pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, NULL);
2318 found_cpu->cpu = OBJECT(dev);
2319 out:
2320 error_propagate(errp, local_err);
2321 }
2322 static void pc_cpu_unplug_request_cb(HotplugHandler *hotplug_dev,
2323 DeviceState *dev, Error **errp)
2324 {
2325 int idx = -1;
2326 Error *local_err = NULL;
2327 X86CPU *cpu = X86_CPU(dev);
2328 PCMachineState *pcms = PC_MACHINE(hotplug_dev);
2329
2330 if (!pcms->acpi_dev) {
2331 error_setg(&local_err, "CPU hot unplug not supported without ACPI");
2332 goto out;
2333 }
2334
2335 pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, &idx);
2336 assert(idx != -1);
2337 if (idx == 0) {
2338 error_setg(&local_err, "Boot CPU is unpluggable");
2339 goto out;
2340 }
2341
2342 hotplug_handler_unplug_request(HOTPLUG_HANDLER(pcms->acpi_dev), dev,
2343 &local_err);
2344 if (local_err) {
2345 goto out;
2346 }
2347
2348 out:
2349 error_propagate(errp, local_err);
2350
2351 }
2352
2353 static void pc_cpu_unplug_cb(HotplugHandler *hotplug_dev,
2354 DeviceState *dev, Error **errp)
2355 {
2356 CPUArchId *found_cpu;
2357 Error *local_err = NULL;
2358 X86CPU *cpu = X86_CPU(dev);
2359 PCMachineState *pcms = PC_MACHINE(hotplug_dev);
2360
2361 hotplug_handler_unplug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err);
2362 if (local_err) {
2363 goto out;
2364 }
2365
2366 found_cpu = pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, NULL);
2367 found_cpu->cpu = NULL;
2368 object_property_set_bool(OBJECT(dev), false, "realized", NULL);
2369
2370 /* decrement the number of CPUs */
2371 pcms->boot_cpus--;
2372 /* Update the number of CPUs in CMOS */
2373 rtc_set_cpus_count(pcms->rtc, pcms->boot_cpus);
2374 fw_cfg_modify_i16(pcms->fw_cfg, FW_CFG_NB_CPUS, pcms->boot_cpus);
2375 out:
2376 error_propagate(errp, local_err);
2377 }
2378
2379 static void pc_cpu_pre_plug(HotplugHandler *hotplug_dev,
2380 DeviceState *dev, Error **errp)
2381 {
2382 int idx;
2383 CPUState *cs;
2384 CPUArchId *cpu_slot;
2385 X86CPUTopoInfo topo;
2386 X86CPU *cpu = X86_CPU(dev);
2387 CPUX86State *env = &cpu->env;
2388 MachineState *ms = MACHINE(hotplug_dev);
2389 PCMachineState *pcms = PC_MACHINE(hotplug_dev);
2390 unsigned int smp_cores = ms->smp.cores;
2391 unsigned int smp_threads = ms->smp.threads;
2392
2393 if(!object_dynamic_cast(OBJECT(cpu), ms->cpu_type)) {
2394 error_setg(errp, "Invalid CPU type, expected cpu type: '%s'",
2395 ms->cpu_type);
2396 return;
2397 }
2398
2399 env->nr_dies = pcms->smp_dies;
2400
2401 /*
2402 * If APIC ID is not set,
2403 * set it based on socket/die/core/thread properties.
2404 */
2405 if (cpu->apic_id == UNASSIGNED_APIC_ID) {
2406 int max_socket = (ms->smp.max_cpus - 1) /
2407 smp_threads / smp_cores / pcms->smp_dies;
2408
2409 if (cpu->socket_id < 0) {
2410 error_setg(errp, "CPU socket-id is not set");
2411 return;
2412 } else if (cpu->socket_id > max_socket) {
2413 error_setg(errp, "Invalid CPU socket-id: %u must be in range 0:%u",
2414 cpu->socket_id, max_socket);
2415 return;
2416 } else if (cpu->die_id > pcms->smp_dies - 1) {
2417 error_setg(errp, "Invalid CPU die-id: %u must be in range 0:%u",
2418 cpu->die_id, max_socket);
2419 return;
2420 }
2421 if (cpu->core_id < 0) {
2422 error_setg(errp, "CPU core-id is not set");
2423 return;
2424 } else if (cpu->core_id > (smp_cores - 1)) {
2425 error_setg(errp, "Invalid CPU core-id: %u must be in range 0:%u",
2426 cpu->core_id, smp_cores - 1);
2427 return;
2428 }
2429 if (cpu->thread_id < 0) {
2430 error_setg(errp, "CPU thread-id is not set");
2431 return;
2432 } else if (cpu->thread_id > (smp_threads - 1)) {
2433 error_setg(errp, "Invalid CPU thread-id: %u must be in range 0:%u",
2434 cpu->thread_id, smp_threads - 1);
2435 return;
2436 }
2437
2438 topo.pkg_id = cpu->socket_id;
2439 topo.die_id = cpu->die_id;
2440 topo.core_id = cpu->core_id;
2441 topo.smt_id = cpu->thread_id;
2442 cpu->apic_id = apicid_from_topo_ids(pcms->smp_dies, smp_cores,
2443 smp_threads, &topo);
2444 }
2445
2446 cpu_slot = pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, &idx);
2447 if (!cpu_slot) {
2448 MachineState *ms = MACHINE(pcms);
2449
2450 x86_topo_ids_from_apicid(cpu->apic_id, pcms->smp_dies,
2451 smp_cores, smp_threads, &topo);
2452 error_setg(errp,
2453 "Invalid CPU [socket: %u, die: %u, core: %u, thread: %u] with"
2454 " APIC ID %" PRIu32 ", valid index range 0:%d",
2455 topo.pkg_id, topo.die_id, topo.core_id, topo.smt_id,
2456 cpu->apic_id, ms->possible_cpus->len - 1);
2457 return;
2458 }
2459
2460 if (cpu_slot->cpu) {
2461 error_setg(errp, "CPU[%d] with APIC ID %" PRIu32 " exists",
2462 idx, cpu->apic_id);
2463 return;
2464 }
2465
2466 /* if 'address' properties socket-id/core-id/thread-id are not set, set them
2467 * so that machine_query_hotpluggable_cpus would show correct values
2468 */
2469 /* TODO: move socket_id/core_id/thread_id checks into x86_cpu_realizefn()
2470 * once -smp refactoring is complete and there will be CPU private
2471 * CPUState::nr_cores and CPUState::nr_threads fields instead of globals */
2472 x86_topo_ids_from_apicid(cpu->apic_id, pcms->smp_dies,
2473 smp_cores, smp_threads, &topo);
2474 if (cpu->socket_id != -1 && cpu->socket_id != topo.pkg_id) {
2475 error_setg(errp, "property socket-id: %u doesn't match set apic-id:"
2476 " 0x%x (socket-id: %u)", cpu->socket_id, cpu->apic_id, topo.pkg_id);
2477 return;
2478 }
2479 cpu->socket_id = topo.pkg_id;
2480
2481 if (cpu->die_id != -1 && cpu->die_id != topo.die_id) {
2482 error_setg(errp, "property die-id: %u doesn't match set apic-id:"
2483 " 0x%x (die-id: %u)", cpu->die_id, cpu->apic_id, topo.die_id);
2484 return;
2485 }
2486 cpu->die_id = topo.die_id;
2487
2488 if (cpu->core_id != -1 && cpu->core_id != topo.core_id) {
2489 error_setg(errp, "property core-id: %u doesn't match set apic-id:"
2490 " 0x%x (core-id: %u)", cpu->core_id, cpu->apic_id, topo.core_id);
2491 return;
2492 }
2493 cpu->core_id = topo.core_id;
2494
2495 if (cpu->thread_id != -1 && cpu->thread_id != topo.smt_id) {
2496 error_setg(errp, "property thread-id: %u doesn't match set apic-id:"
2497 " 0x%x (thread-id: %u)", cpu->thread_id, cpu->apic_id, topo.smt_id);
2498 return;
2499 }
2500 cpu->thread_id = topo.smt_id;
2501
2502 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_VPINDEX) &&
2503 !kvm_hv_vpindex_settable()) {
2504 error_setg(errp, "kernel doesn't allow setting HyperV VP_INDEX");
2505 return;
2506 }
2507
2508 cs = CPU(cpu);
2509 cs->cpu_index = idx;
2510
2511 numa_cpu_pre_plug(cpu_slot, dev, errp);
2512 }
2513
2514 static void pc_virtio_pmem_pci_pre_plug(HotplugHandler *hotplug_dev,
2515 DeviceState *dev, Error **errp)
2516 {
2517 HotplugHandler *hotplug_dev2 = qdev_get_bus_hotplug_handler(dev);
2518 Error *local_err = NULL;
2519
2520 if (!hotplug_dev2) {
2521 /*
2522 * Without a bus hotplug handler, we cannot control the plug/unplug
2523 * order. This should never be the case on x86, however better add
2524 * a safety net.
2525 */
2526 error_setg(errp, "virtio-pmem-pci not supported on this bus.");
2527 return;
2528 }
2529 /*
2530 * First, see if we can plug this memory device at all. If that
2531 * succeeds, branch of to the actual hotplug handler.
2532 */
2533 memory_device_pre_plug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev), NULL,
2534 &local_err);
2535 if (!local_err) {
2536 hotplug_handler_pre_plug(hotplug_dev2, dev, &local_err);
2537 }
2538 error_propagate(errp, local_err);
2539 }
2540
2541 static void pc_virtio_pmem_pci_plug(HotplugHandler *hotplug_dev,
2542 DeviceState *dev, Error **errp)
2543 {
2544 HotplugHandler *hotplug_dev2 = qdev_get_bus_hotplug_handler(dev);
2545 Error *local_err = NULL;
2546
2547 /*
2548 * Plug the memory device first and then branch off to the actual
2549 * hotplug handler. If that one fails, we can easily undo the memory
2550 * device bits.
2551 */
2552 memory_device_plug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev));
2553 hotplug_handler_plug(hotplug_dev2, dev, &local_err);
2554 if (local_err) {
2555 memory_device_unplug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev));
2556 }
2557 error_propagate(errp, local_err);
2558 }
2559
2560 static void pc_virtio_pmem_pci_unplug_request(HotplugHandler *hotplug_dev,
2561 DeviceState *dev, Error **errp)
2562 {
2563 /* We don't support virtio pmem hot unplug */
2564 error_setg(errp, "virtio pmem device unplug not supported.");
2565 }
2566
2567 static void pc_virtio_pmem_pci_unplug(HotplugHandler *hotplug_dev,
2568 DeviceState *dev, Error **errp)
2569 {
2570 /* We don't support virtio pmem hot unplug */
2571 }
2572
2573 static void pc_machine_device_pre_plug_cb(HotplugHandler *hotplug_dev,
2574 DeviceState *dev, Error **errp)
2575 {
2576 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
2577 pc_memory_pre_plug(hotplug_dev, dev, errp);
2578 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
2579 pc_cpu_pre_plug(hotplug_dev, dev, errp);
2580 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI)) {
2581 pc_virtio_pmem_pci_pre_plug(hotplug_dev, dev, errp);
2582 }
2583 }
2584
2585 static void pc_machine_device_plug_cb(HotplugHandler *hotplug_dev,
2586 DeviceState *dev, Error **errp)
2587 {
2588 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
2589 pc_memory_plug(hotplug_dev, dev, errp);
2590 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
2591 pc_cpu_plug(hotplug_dev, dev, errp);
2592 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI)) {
2593 pc_virtio_pmem_pci_plug(hotplug_dev, dev, errp);
2594 }
2595 }
2596
2597 static void pc_machine_device_unplug_request_cb(HotplugHandler *hotplug_dev,
2598 DeviceState *dev, Error **errp)
2599 {
2600 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
2601 pc_memory_unplug_request(hotplug_dev, dev, errp);
2602 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
2603 pc_cpu_unplug_request_cb(hotplug_dev, dev, errp);
2604 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI)) {
2605 pc_virtio_pmem_pci_unplug_request(hotplug_dev, dev, errp);
2606 } else {
2607 error_setg(errp, "acpi: device unplug request for not supported device"
2608 " type: %s", object_get_typename(OBJECT(dev)));
2609 }
2610 }
2611
2612 static void pc_machine_device_unplug_cb(HotplugHandler *hotplug_dev,
2613 DeviceState *dev, Error **errp)
2614 {
2615 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
2616 pc_memory_unplug(hotplug_dev, dev, errp);
2617 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
2618 pc_cpu_unplug_cb(hotplug_dev, dev, errp);
2619 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI)) {
2620 pc_virtio_pmem_pci_unplug(hotplug_dev, dev, errp);
2621 } else {
2622 error_setg(errp, "acpi: device unplug for not supported device"
2623 " type: %s", object_get_typename(OBJECT(dev)));
2624 }
2625 }
2626
2627 static HotplugHandler *pc_get_hotplug_handler(MachineState *machine,
2628 DeviceState *dev)
2629 {
2630 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) ||
2631 object_dynamic_cast(OBJECT(dev), TYPE_CPU) ||
2632 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI)) {
2633 return HOTPLUG_HANDLER(machine);
2634 }
2635
2636 return NULL;
2637 }
2638
2639 static void
2640 pc_machine_get_device_memory_region_size(Object *obj, Visitor *v,
2641 const char *name, void *opaque,
2642 Error **errp)
2643 {
2644 MachineState *ms = MACHINE(obj);
2645 int64_t value = 0;
2646
2647 if (ms->device_memory) {
2648 value = memory_region_size(&ms->device_memory->mr);
2649 }
2650
2651 visit_type_int(v, name, &value, errp);
2652 }
2653
2654 static void pc_machine_get_max_ram_below_4g(Object *obj, Visitor *v,
2655 const char *name, void *opaque,
2656 Error **errp)
2657 {
2658 PCMachineState *pcms = PC_MACHINE(obj);
2659 uint64_t value = pcms->max_ram_below_4g;
2660
2661 visit_type_size(v, name, &value, errp);
2662 }
2663
2664 static void pc_machine_set_max_ram_below_4g(Object *obj, Visitor *v,
2665 const char *name, void *opaque,
2666 Error **errp)
2667 {
2668 PCMachineState *pcms = PC_MACHINE(obj);
2669 Error *error = NULL;
2670 uint64_t value;
2671
2672 visit_type_size(v, name, &value, &error);
2673 if (error) {
2674 error_propagate(errp, error);
2675 return;
2676 }
2677 if (value > 4 * GiB) {
2678 error_setg(&error,
2679 "Machine option 'max-ram-below-4g=%"PRIu64
2680 "' expects size less than or equal to 4G", value);
2681 error_propagate(errp, error);
2682 return;
2683 }
2684
2685 if (value < 1 * MiB) {
2686 warn_report("Only %" PRIu64 " bytes of RAM below the 4GiB boundary,"
2687 "BIOS may not work with less than 1MiB", value);
2688 }
2689
2690 pcms->max_ram_below_4g = value;
2691 }
2692
2693 static void pc_machine_get_vmport(Object *obj, Visitor *v, const char *name,
2694 void *opaque, Error **errp)
2695 {
2696 PCMachineState *pcms = PC_MACHINE(obj);
2697 OnOffAuto vmport = pcms->vmport;
2698
2699 visit_type_OnOffAuto(v, name, &vmport, errp);
2700 }
2701
2702 static void pc_machine_set_vmport(Object *obj, Visitor *v, const char *name,
2703 void *opaque, Error **errp)
2704 {
2705 PCMachineState *pcms = PC_MACHINE(obj);
2706
2707 visit_type_OnOffAuto(v, name, &pcms->vmport, errp);
2708 }
2709
2710 bool pc_machine_is_smm_enabled(PCMachineState *pcms)
2711 {
2712 bool smm_available = false;
2713
2714 if (pcms->smm == ON_OFF_AUTO_OFF) {
2715 return false;
2716 }
2717
2718 if (tcg_enabled() || qtest_enabled()) {
2719 smm_available = true;
2720 } else if (kvm_enabled()) {
2721 smm_available = kvm_has_smm();
2722 }
2723
2724 if (smm_available) {
2725 return true;
2726 }
2727
2728 if (pcms->smm == ON_OFF_AUTO_ON) {
2729 error_report("System Management Mode not supported by this hypervisor.");
2730 exit(1);
2731 }
2732 return false;
2733 }
2734
2735 static void pc_machine_get_smm(Object *obj, Visitor *v, const char *name,
2736 void *opaque, Error **errp)
2737 {
2738 PCMachineState *pcms = PC_MACHINE(obj);
2739 OnOffAuto smm = pcms->smm;
2740
2741 visit_type_OnOffAuto(v, name, &smm, errp);
2742 }
2743
2744 static void pc_machine_set_smm(Object *obj, Visitor *v, const char *name,
2745 void *opaque, Error **errp)
2746 {
2747 PCMachineState *pcms = PC_MACHINE(obj);
2748
2749 visit_type_OnOffAuto(v, name, &pcms->smm, errp);
2750 }
2751
2752 static bool pc_machine_get_smbus(Object *obj, Error **errp)
2753 {
2754 PCMachineState *pcms = PC_MACHINE(obj);
2755
2756 return pcms->smbus_enabled;
2757 }
2758
2759 static void pc_machine_set_smbus(Object *obj, bool value, Error **errp)
2760 {
2761 PCMachineState *pcms = PC_MACHINE(obj);
2762
2763 pcms->smbus_enabled = value;
2764 }
2765
2766 static bool pc_machine_get_sata(Object *obj, Error **errp)
2767 {
2768 PCMachineState *pcms = PC_MACHINE(obj);
2769
2770 return pcms->sata_enabled;
2771 }
2772
2773 static void pc_machine_set_sata(Object *obj, bool value, Error **errp)
2774 {
2775 PCMachineState *pcms = PC_MACHINE(obj);
2776
2777 pcms->sata_enabled = value;
2778 }
2779
2780 static bool pc_machine_get_pit(Object *obj, Error **errp)
2781 {
2782 PCMachineState *pcms = PC_MACHINE(obj);
2783
2784 return pcms->pit_enabled;
2785 }
2786
2787 static void pc_machine_set_pit(Object *obj, bool value, Error **errp)
2788 {
2789 PCMachineState *pcms = PC_MACHINE(obj);
2790
2791 pcms->pit_enabled = value;
2792 }
2793
2794 static void pc_machine_initfn(Object *obj)
2795 {
2796 PCMachineState *pcms = PC_MACHINE(obj);
2797
2798 pcms->max_ram_below_4g = 0; /* use default */
2799 pcms->smm = ON_OFF_AUTO_AUTO;
2800 #ifdef CONFIG_VMPORT
2801 pcms->vmport = ON_OFF_AUTO_AUTO;
2802 #else
2803 pcms->vmport = ON_OFF_AUTO_OFF;
2804 #endif /* CONFIG_VMPORT */
2805 /* acpi build is enabled by default if machine supports it */
2806 pcms->acpi_build_enabled = PC_MACHINE_GET_CLASS(pcms)->has_acpi_build;
2807 pcms->smbus_enabled = true;
2808 pcms->sata_enabled = true;
2809 pcms->pit_enabled = true;
2810 pcms->smp_dies = 1;
2811
2812 pc_system_flash_create(pcms);
2813 }
2814
2815 static void pc_machine_reset(MachineState *machine)
2816 {
2817 CPUState *cs;
2818 X86CPU *cpu;
2819
2820 qemu_devices_reset();
2821
2822 /* Reset APIC after devices have been reset to cancel
2823 * any changes that qemu_devices_reset() might have done.
2824 */
2825 CPU_FOREACH(cs) {
2826 cpu = X86_CPU(cs);
2827
2828 if (cpu->apic_state) {
2829 device_reset(cpu->apic_state);
2830 }
2831 }
2832 }
2833
2834 static CpuInstanceProperties
2835 pc_cpu_index_to_props(MachineState *ms, unsigned cpu_index)
2836 {
2837 MachineClass *mc = MACHINE_GET_CLASS(ms);
2838 const CPUArchIdList *possible_cpus = mc->possible_cpu_arch_ids(ms);
2839
2840 assert(cpu_index < possible_cpus->len);
2841 return possible_cpus->cpus[cpu_index].props;
2842 }
2843
2844 static int64_t pc_get_default_cpu_node_id(const MachineState *ms, int idx)
2845 {
2846 X86CPUTopoInfo topo;
2847 PCMachineState *pcms = PC_MACHINE(ms);
2848
2849 assert(idx < ms->possible_cpus->len);
2850 x86_topo_ids_from_apicid(ms->possible_cpus->cpus[idx].arch_id,
2851 pcms->smp_dies, ms->smp.cores,
2852 ms->smp.threads, &topo);
2853 return topo.pkg_id % nb_numa_nodes;
2854 }
2855
2856 static const CPUArchIdList *pc_possible_cpu_arch_ids(MachineState *ms)
2857 {
2858 PCMachineState *pcms = PC_MACHINE(ms);
2859 int i;
2860 unsigned int max_cpus = ms->smp.max_cpus;
2861
2862 if (ms->possible_cpus) {
2863 /*
2864 * make sure that max_cpus hasn't changed since the first use, i.e.
2865 * -smp hasn't been parsed after it
2866 */
2867 assert(ms->possible_cpus->len == max_cpus);
2868 return ms->possible_cpus;
2869 }
2870
2871 ms->possible_cpus = g_malloc0(sizeof(CPUArchIdList) +
2872 sizeof(CPUArchId) * max_cpus);
2873 ms->possible_cpus->len = max_cpus;
2874 for (i = 0; i < ms->possible_cpus->len; i++) {
2875 X86CPUTopoInfo topo;
2876
2877 ms->possible_cpus->cpus[i].type = ms->cpu_type;
2878 ms->possible_cpus->cpus[i].vcpus_count = 1;
2879 ms->possible_cpus->cpus[i].arch_id = x86_cpu_apic_id_from_index(pcms, i);
2880 x86_topo_ids_from_apicid(ms->possible_cpus->cpus[i].arch_id,
2881 pcms->smp_dies, ms->smp.cores,
2882 ms->smp.threads, &topo);
2883 ms->possible_cpus->cpus[i].props.has_socket_id = true;
2884 ms->possible_cpus->cpus[i].props.socket_id = topo.pkg_id;
2885 ms->possible_cpus->cpus[i].props.has_die_id = true;
2886 ms->possible_cpus->cpus[i].props.die_id = topo.die_id;
2887 ms->possible_cpus->cpus[i].props.has_core_id = true;
2888 ms->possible_cpus->cpus[i].props.core_id = topo.core_id;
2889 ms->possible_cpus->cpus[i].props.has_thread_id = true;
2890 ms->possible_cpus->cpus[i].props.thread_id = topo.smt_id;
2891 }
2892 return ms->possible_cpus;
2893 }
2894
2895 static void x86_nmi(NMIState *n, int cpu_index, Error **errp)
2896 {
2897 /* cpu index isn't used */
2898 CPUState *cs;
2899
2900 CPU_FOREACH(cs) {
2901 X86CPU *cpu = X86_CPU(cs);
2902
2903 if (!cpu->apic_state) {
2904 cpu_interrupt(cs, CPU_INTERRUPT_NMI);
2905 } else {
2906 apic_deliver_nmi(cpu->apic_state);
2907 }
2908 }
2909 }
2910
2911 static void pc_machine_class_init(ObjectClass *oc, void *data)
2912 {
2913 MachineClass *mc = MACHINE_CLASS(oc);
2914 PCMachineClass *pcmc = PC_MACHINE_CLASS(oc);
2915 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc);
2916 NMIClass *nc = NMI_CLASS(oc);
2917
2918 pcmc->pci_enabled = true;
2919 pcmc->has_acpi_build = true;
2920 pcmc->rsdp_in_ram = true;
2921 pcmc->smbios_defaults = true;
2922 pcmc->smbios_uuid_encoded = true;
2923 pcmc->gigabyte_align = true;
2924 pcmc->has_reserved_memory = true;
2925 pcmc->kvmclock_enabled = true;
2926 pcmc->enforce_aligned_dimm = true;
2927 /* BIOS ACPI tables: 128K. Other BIOS datastructures: less than 4K reported
2928 * to be used at the moment, 32K should be enough for a while. */
2929 pcmc->acpi_data_size = 0x20000 + 0x8000;
2930 pcmc->save_tsc_khz = true;
2931 pcmc->linuxboot_dma_enabled = true;
2932 pcmc->pvh_enabled = true;
2933 assert(!mc->get_hotplug_handler);
2934 mc->get_hotplug_handler = pc_get_hotplug_handler;
2935 mc->cpu_index_to_instance_props = pc_cpu_index_to_props;
2936 mc->get_default_cpu_node_id = pc_get_default_cpu_node_id;
2937 mc->possible_cpu_arch_ids = pc_possible_cpu_arch_ids;
2938 mc->auto_enable_numa_with_memhp = true;
2939 mc->has_hotpluggable_cpus = true;
2940 mc->default_boot_order = "cad";
2941 mc->hot_add_cpu = pc_hot_add_cpu;
2942 mc->smp_parse = pc_smp_parse;
2943 mc->block_default_type = IF_IDE;
2944 mc->max_cpus = 255;
2945 mc->reset = pc_machine_reset;
2946 hc->pre_plug = pc_machine_device_pre_plug_cb;
2947 hc->plug = pc_machine_device_plug_cb;
2948 hc->unplug_request = pc_machine_device_unplug_request_cb;
2949 hc->unplug = pc_machine_device_unplug_cb;
2950 nc->nmi_monitor_handler = x86_nmi;
2951 mc->default_cpu_type = TARGET_DEFAULT_CPU_TYPE;
2952 mc->nvdimm_supported = true;
2953 mc->numa_mem_supported = true;
2954
2955 object_class_property_add(oc, PC_MACHINE_DEVMEM_REGION_SIZE, "int",
2956 pc_machine_get_device_memory_region_size, NULL,
2957 NULL, NULL, &error_abort);
2958
2959 object_class_property_add(oc, PC_MACHINE_MAX_RAM_BELOW_4G, "size",
2960 pc_machine_get_max_ram_below_4g, pc_machine_set_max_ram_below_4g,
2961 NULL, NULL, &error_abort);
2962
2963 object_class_property_set_description(oc, PC_MACHINE_MAX_RAM_BELOW_4G,
2964 "Maximum ram below the 4G boundary (32bit boundary)", &error_abort);
2965
2966 object_class_property_add(oc, PC_MACHINE_SMM, "OnOffAuto",
2967 pc_machine_get_smm, pc_machine_set_smm,
2968 NULL, NULL, &error_abort);
2969 object_class_property_set_description(oc, PC_MACHINE_SMM,
2970 "Enable SMM (pc & q35)", &error_abort);
2971
2972 object_class_property_add(oc, PC_MACHINE_VMPORT, "OnOffAuto",
2973 pc_machine_get_vmport, pc_machine_set_vmport,
2974 NULL, NULL, &error_abort);
2975 object_class_property_set_description(oc, PC_MACHINE_VMPORT,
2976 "Enable vmport (pc & q35)", &error_abort);
2977
2978 object_class_property_add_bool(oc, PC_MACHINE_SMBUS,
2979 pc_machine_get_smbus, pc_machine_set_smbus, &error_abort);
2980
2981 object_class_property_add_bool(oc, PC_MACHINE_SATA,
2982 pc_machine_get_sata, pc_machine_set_sata, &error_abort);
2983
2984 object_class_property_add_bool(oc, PC_MACHINE_PIT,
2985 pc_machine_get_pit, pc_machine_set_pit, &error_abort);
2986 }
2987
2988 static const TypeInfo pc_machine_info = {
2989 .name = TYPE_PC_MACHINE,
2990 .parent = TYPE_MACHINE,
2991 .abstract = true,
2992 .instance_size = sizeof(PCMachineState),
2993 .instance_init = pc_machine_initfn,
2994 .class_size = sizeof(PCMachineClass),
2995 .class_init = pc_machine_class_init,
2996 .interfaces = (InterfaceInfo[]) {
2997 { TYPE_HOTPLUG_HANDLER },
2998 { TYPE_NMI },
2999 { }
3000 },
3001 };
3002
3003 static void pc_machine_register_types(void)
3004 {
3005 type_register_static(&pc_machine_info);
3006 }
3007
3008 type_init(pc_machine_register_types)
armbru's QEMU hackery