include/hw/arm/raspi_platform.h

   1 /*
   2  * bcm2708 aka bcm2835/2836 aka Raspberry Pi/Pi2 SoC platform defines
   3  *
   4  * These definitions are derived from those in Raspbian Linux at
   5  * arch/arm/mach-{bcm2708,bcm2709}/include/mach/platform.h
   6  * where they carry the following notice:
   7  *
   8  * Copyright (C) 2010 Broadcom
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License as published by
  12  * the Free Software Foundation; either version 2 of the License, or
  13  * (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License
  21  * along with this program. If not, see <https://www.gnu.org/licenses/>.
  22  *
  23  * Various undocumented addresses and names come from Herman Hermitage's VC4
  24  * documentation:
  25  * https://github.com/hermanhermitage/videocoreiv/wiki/MMIO-Register-map
  26  */
  27
  28 #ifndef HW_ARM_RASPI_PLATFORM_H
  29 #define HW_ARM_RASPI_PLATFORM_H
  30
  31 #define MSYNC_OFFSET            0x0000   /* Multicore Sync Block */
  32 #define CCPT_OFFSET             0x1000   /* Compact Camera Port 2 TX */
  33 #define INTE_OFFSET             0x2000   /* VC Interrupt controller */
  34 #define ST_OFFSET               0x3000   /* System Timer */
  35 #define TXP_OFFSET              0x4000   /* Transposer */
  36 #define JPEG_OFFSET             0x5000
  37 #define MPHI_OFFSET             0x6000   /* Message-based Parallel Host Intf. */
  38 #define DMA_OFFSET              0x7000   /* DMA controller, channels 0-14 */
  39 #define ARBA_OFFSET             0x9000
  40 #define BRDG_OFFSET             0xa000
  41 #define ARM_OFFSET              0xB000   /* ARM control block */
  42 #define ARMCTRL_OFFSET          (ARM_OFFSET + 0x000)
  43 #define ARMCTRL_IC_OFFSET       (ARM_OFFSET + 0x200) /* Interrupt controller */
  44 #define ARMCTRL_TIMER0_1_OFFSET (ARM_OFFSET + 0x400) /* Timer 0 and 1 (SP804) */
  45 #define ARMCTRL_0_SBM_OFFSET    (ARM_OFFSET + 0x800) /* User 0 (ARM) Semaphores
  46                                                       * Doorbells & Mailboxes */
  47 #define PM_OFFSET               0x100000 /* Power Management */
  48 #define CPRMAN_OFFSET           0x101000 /* Clock Management */
  49 #define AVS_OFFSET              0x103000 /* Audio Video Standard */
  50 #define RNG_OFFSET              0x104000
  51 #define GPIO_OFFSET             0x200000
  52 #define UART0_OFFSET            0x201000 /* PL011 */
  53 #define MMCI0_OFFSET            0x202000 /* Legacy MMC */
  54 #define I2S_OFFSET              0x203000 /* PCM */
  55 #define SPI0_OFFSET             0x204000 /* SPI master */
  56 #define BSC0_OFFSET             0x205000 /* BSC0 I2C/TWI */
  57 #define PIXV0_OFFSET            0x206000
  58 #define PIXV1_OFFSET            0x207000
  59 #define DPI_OFFSET              0x208000
  60 #define DSI0_OFFSET             0x209000 /* Display Serial Interface */
  61 #define PWM_OFFSET              0x20c000
  62 #define PERM_OFFSET             0x20d000
  63 #define TEC_OFFSET              0x20e000
  64 #define OTP_OFFSET              0x20f000
  65 #define SLIM_OFFSET             0x210000 /* SLIMbus */
  66 #define CPG_OFFSET              0x211000
  67 #define THERMAL_OFFSET          0x212000
  68 #define AVSP_OFFSET             0x213000
  69 #define BSC_SL_OFFSET           0x214000 /* SPI slave (bootrom) */
  70 #define AUX_OFFSET              0x215000 /* AUX: UART1/SPI1/SPI2 */
  71 #define EMMC1_OFFSET            0x300000
  72 #define EMMC2_OFFSET            0x340000
  73 #define HVS_OFFSET              0x400000
  74 #define SMI_OFFSET              0x600000
  75 #define DSI1_OFFSET             0x700000
  76 #define UCAM_OFFSET             0x800000
  77 #define CMI_OFFSET              0x802000
  78 #define BSC1_OFFSET             0x804000 /* BSC1 I2C/TWI */
  79 #define BSC2_OFFSET             0x805000 /* BSC2 I2C/TWI */
  80 #define VECA_OFFSET             0x806000
  81 #define PIXV2_OFFSET            0x807000
  82 #define HDMI_OFFSET             0x808000
  83 #define HDCP_OFFSET             0x809000
  84 #define ARBR0_OFFSET            0x80a000
  85 #define DBUS_OFFSET             0x900000
  86 #define AVE0_OFFSET             0x910000
  87 #define USB_OTG_OFFSET          0x980000 /* DTC_OTG USB controller */
  88 #define V3D_OFFSET              0xc00000
  89 #define SDRAMC_OFFSET           0xe00000
  90 #define L2CC_OFFSET             0xe01000 /* Level 2 Cache controller */
  91 #define L1CC_OFFSET             0xe02000 /* Level 1 Cache controller */
  92 #define ARBR1_OFFSET            0xe04000
  93 #define DMA15_OFFSET            0xE05000 /* DMA controller, channel 15 */
  94 #define DCRC_OFFSET             0xe07000
  95 #define AXIP_OFFSET             0xe08000
  96
  97 /* GPU interrupts */
  98 #define INTERRUPT_TIMER0               0
  99 #define INTERRUPT_TIMER1               1
 100 #define INTERRUPT_TIMER2               2
 101 #define INTERRUPT_TIMER3               3
 102 #define INTERRUPT_CODEC0               4
 103 #define INTERRUPT_CODEC1               5
 104 #define INTERRUPT_CODEC2               6
 105 #define INTERRUPT_JPEG                 7
 106 #define INTERRUPT_ISP                  8
 107 #define INTERRUPT_USB                  9
 108 #define INTERRUPT_3D                   10
 109 #define INTERRUPT_TRANSPOSER           11
 110 #define INTERRUPT_MULTICORESYNC0       12
 111 #define INTERRUPT_MULTICORESYNC1       13
 112 #define INTERRUPT_MULTICORESYNC2       14
 113 #define INTERRUPT_MULTICORESYNC3       15
 114 #define INTERRUPT_DMA0                 16
 115 #define INTERRUPT_DMA1                 17
 116 #define INTERRUPT_DMA2                 18
 117 #define INTERRUPT_DMA3                 19
 118 #define INTERRUPT_DMA4                 20
 119 #define INTERRUPT_DMA5                 21
 120 #define INTERRUPT_DMA6                 22
 121 #define INTERRUPT_DMA7                 23
 122 #define INTERRUPT_DMA8                 24
 123 #define INTERRUPT_DMA9                 25
 124 #define INTERRUPT_DMA10                26
 125 #define INTERRUPT_DMA11                27
 126 #define INTERRUPT_DMA12                28
 127 #define INTERRUPT_AUX                  29
 128 #define INTERRUPT_ARM                  30
 129 #define INTERRUPT_VPUDMA               31
 130 #define INTERRUPT_HOSTPORT             32
 131 #define INTERRUPT_VIDEOSCALER          33
 132 #define INTERRUPT_CCP2TX               34
 133 #define INTERRUPT_SDC                  35
 134 #define INTERRUPT_DSI0                 36
 135 #define INTERRUPT_AVE                  37
 136 #define INTERRUPT_CAM0                 38
 137 #define INTERRUPT_CAM1                 39
 138 #define INTERRUPT_HDMI0                40
 139 #define INTERRUPT_HDMI1                41
 140 #define INTERRUPT_PIXELVALVE1          42
 141 #define INTERRUPT_I2CSPISLV            43
 142 #define INTERRUPT_DSI1                 44
 143 #define INTERRUPT_PWA0                 45
 144 #define INTERRUPT_PWA1                 46
 145 #define INTERRUPT_CPR                  47
 146 #define INTERRUPT_SMI                  48
 147 #define INTERRUPT_GPIO0                49
 148 #define INTERRUPT_GPIO1                50
 149 #define INTERRUPT_GPIO2                51
 150 #define INTERRUPT_GPIO3                52
 151 #define INTERRUPT_I2C                  53
 152 #define INTERRUPT_SPI                  54
 153 #define INTERRUPT_I2SPCM               55
 154 #define INTERRUPT_SDIO                 56
 155 #define INTERRUPT_UART0                57
 156 #define INTERRUPT_SLIMBUS              58
 157 #define INTERRUPT_VEC                  59
 158 #define INTERRUPT_CPG                  60
 159 #define INTERRUPT_RNG                  61
 160 #define INTERRUPT_ARASANSDIO           62
 161 #define INTERRUPT_AVSPMON              63
 162
 163 /* ARM CPU IRQs use a private number space */
 164 #define INTERRUPT_ARM_TIMER            0
 165 #define INTERRUPT_ARM_MAILBOX          1
 166 #define INTERRUPT_ARM_DOORBELL_0       2
 167 #define INTERRUPT_ARM_DOORBELL_1       3
 168 #define INTERRUPT_VPU0_HALTED          4
 169 #define INTERRUPT_VPU1_HALTED          5
 170 #define INTERRUPT_ILLEGAL_TYPE0        6
 171 #define INTERRUPT_ILLEGAL_TYPE1        7
 172
 173 /* Clock rates */
 174 #define RPI_FIRMWARE_EMMC_CLK_RATE    50000000
 175 #define RPI_FIRMWARE_UART_CLK_RATE    3000000
 176 /*
 177  * TODO: this is really SoC-specific; we might want to
 178  * set it per-SoC if it turns out any guests care.
 179  */
 180 #define RPI_FIRMWARE_CORE_CLK_RATE    350000000
 181 #define RPI_FIRMWARE_DEFAULT_CLK_RATE 700000000
 182
 183 #endif