include/hw/cxl/cxl_events.h

   1 /*
   2  * QEMU CXL Events
   3  *
   4  * Copyright (c) 2022 Intel
   5  *
   6  * This work is licensed under the terms of the GNU GPL, version 2. See the
   7  * COPYING file in the top-level directory.
   8  */
   9
  10 #ifndef CXL_EVENTS_H
  11 #define CXL_EVENTS_H
  12
  13 #include "qemu/uuid.h"
  14
  15 /*
  16  * CXL rev 3.0 section 8.2.9.2.2; Table 8-49
  17  *
  18  * Define these as the bit position for the event status register for ease of
  19  * setting the status.
  20  */
  21 typedef enum CXLEventLogType {
  22     CXL_EVENT_TYPE_INFO          = 0,
  23     CXL_EVENT_TYPE_WARN          = 1,
  24     CXL_EVENT_TYPE_FAIL          = 2,
  25     CXL_EVENT_TYPE_FATAL         = 3,
  26     CXL_EVENT_TYPE_DYNAMIC_CAP   = 4,
  27     CXL_EVENT_TYPE_MAX
  28 } CXLEventLogType;
  29
  30 /*
  31  * Common Event Record Format
  32  * CXL rev 3.0 section 8.2.9.2.1; Table 8-42
  33  */
  34 #define CXL_EVENT_REC_HDR_RES_LEN 0xf
  35 typedef struct CXLEventRecordHdr {
  36     QemuUUID id;
  37     uint8_t length;
  38     uint8_t flags[3];
  39     uint16_t handle;
  40     uint16_t related_handle;
  41     uint64_t timestamp;
  42     uint8_t maint_op_class;
  43     uint8_t reserved[CXL_EVENT_REC_HDR_RES_LEN];
  44 } QEMU_PACKED CXLEventRecordHdr;
  45
  46 #define CXL_EVENT_RECORD_DATA_LENGTH 0x50
  47 typedef struct CXLEventRecordRaw {
  48     CXLEventRecordHdr hdr;
  49     uint8_t data[CXL_EVENT_RECORD_DATA_LENGTH];
  50 } QEMU_PACKED CXLEventRecordRaw;
  51 #define CXL_EVENT_RECORD_SIZE (sizeof(CXLEventRecordRaw))
  52
  53 /*
  54  * Get Event Records output payload
  55  * CXL rev 3.0 section 8.2.9.2.2; Table 8-50
  56  */
  57 #define CXL_GET_EVENT_FLAG_OVERFLOW     BIT(0)
  58 #define CXL_GET_EVENT_FLAG_MORE_RECORDS BIT(1)
  59 typedef struct CXLGetEventPayload {
  60     uint8_t flags;
  61     uint8_t reserved1;
  62     uint16_t overflow_err_count;
  63     uint64_t first_overflow_timestamp;
  64     uint64_t last_overflow_timestamp;
  65     uint16_t record_count;
  66     uint8_t reserved2[0xa];
  67     CXLEventRecordRaw records[];
  68 } QEMU_PACKED CXLGetEventPayload;
  69 #define CXL_EVENT_PAYLOAD_HDR_SIZE (sizeof(CXLGetEventPayload))
  70
  71 /*
  72  * Clear Event Records input payload
  73  * CXL rev 3.0 section 8.2.9.2.3; Table 8-51
  74  */
  75 typedef struct CXLClearEventPayload {
  76     uint8_t event_log;      /* CXLEventLogType */
  77     uint8_t clear_flags;
  78     uint8_t nr_recs;
  79     uint8_t reserved[3];
  80     uint16_t handle[];
  81 } CXLClearEventPayload;
  82
  83 /**
  84  * Event Interrupt Policy
  85  *
  86  * CXL rev 3.0 section 8.2.9.2.4; Table 8-52
  87  */
  88 typedef enum CXLEventIntMode {
  89     CXL_INT_NONE     = 0x00,
  90     CXL_INT_MSI_MSIX = 0x01,
  91     CXL_INT_FW       = 0x02,
  92     CXL_INT_RES      = 0x03,
  93 } CXLEventIntMode;
  94 #define CXL_EVENT_INT_MODE_MASK 0x3
  95 #define CXL_EVENT_INT_SETTING(vector) \
  96     ((((uint8_t)vector & 0xf) << 4) | CXL_INT_MSI_MSIX)
  97 typedef struct CXLEventInterruptPolicy {
  98     uint8_t info_settings;
  99     uint8_t warn_settings;
 100     uint8_t failure_settings;
 101     uint8_t fatal_settings;
 102     uint8_t dyn_cap_settings;
 103 } QEMU_PACKED CXLEventInterruptPolicy;
 104 /* DCD is optional but other fields are not */
 105 #define CXL_EVENT_INT_SETTING_MIN_LEN 4
 106
 107 /*
 108  * General Media Event Record
 109  * CXL rev 3.0 Section 8.2.9.2.1.1; Table 8-43
 110  */
 111 #define CXL_EVENT_GEN_MED_COMP_ID_SIZE  0x10
 112 #define CXL_EVENT_GEN_MED_RES_SIZE      0x2e
 113 typedef struct CXLEventGenMedia {
 114     CXLEventRecordHdr hdr;
 115     uint64_t phys_addr;
 116     uint8_t descriptor;
 117     uint8_t type;
 118     uint8_t transaction_type;
 119     uint16_t validity_flags;
 120     uint8_t channel;
 121     uint8_t rank;
 122     uint8_t device[3];
 123     uint8_t component_id[CXL_EVENT_GEN_MED_COMP_ID_SIZE];
 124     uint8_t reserved[CXL_EVENT_GEN_MED_RES_SIZE];
 125 } QEMU_PACKED CXLEventGenMedia;
 126
 127 /*
 128  * DRAM Event Record
 129  * CXL Rev 3.0 Section 8.2.9.2.1.2: Table 8-44
 130  * All fields little endian.
 131  */
 132 typedef struct CXLEventDram {
 133     CXLEventRecordHdr hdr;
 134     uint64_t phys_addr;
 135     uint8_t descriptor;
 136     uint8_t type;
 137     uint8_t transaction_type;
 138     uint16_t validity_flags;
 139     uint8_t channel;
 140     uint8_t rank;
 141     uint8_t nibble_mask[3];
 142     uint8_t bank_group;
 143     uint8_t bank;
 144     uint8_t row[3];
 145     uint16_t column;
 146     uint64_t correction_mask[4];
 147     uint8_t reserved[0x17];
 148 } QEMU_PACKED CXLEventDram;
 149
 150 /*
 151  * Memory Module Event Record
 152  * CXL Rev 3.0 Section 8.2.9.2.1.3: Table 8-45
 153  * All fields little endian.
 154  */
 155 typedef struct CXLEventMemoryModule {
 156     CXLEventRecordHdr hdr;
 157     uint8_t type;
 158     uint8_t health_status;
 159     uint8_t media_status;
 160     uint8_t additional_status;
 161     uint8_t life_used;
 162     int16_t temperature;
 163     uint32_t dirty_shutdown_count;
 164     uint32_t corrected_volatile_error_count;
 165     uint32_t corrected_persistent_error_count;
 166     uint8_t reserved[0x3d];
 167 } QEMU_PACKED CXLEventMemoryModule;
 168
 169 #endif /* CXL_EVENTS_H */