include/hw/pci/pcie_regs.h

   1 /*
   2  * constants for pcie configurations space from pci express spec.
   3  *
   4  * TODO:
   5  * Those constants and macros should go to Linux pci_regs.h
   6  * Once they're merged, they will go away.
   7  */
   8 #ifndef QEMU_PCIE_REGS_H
   9 #define QEMU_PCIE_REGS_H
  10
  11
  12 /* express capability */
  13
  14 #define PCI_EXP_VER1_SIZEOF             0x14 /* express capability of ver. 1 */
  15 #define PCI_EXP_VER2_SIZEOF             0x3c /* express capability of ver. 2 */
  16 #define PCI_EXT_CAP_VER_SHIFT           16
  17 #define PCI_EXT_CAP_NEXT_SHIFT          20
  18 #define PCI_EXT_CAP_NEXT_MASK           (0xffc << PCI_EXT_CAP_NEXT_SHIFT)
  19
  20 #define PCI_EXT_CAP(id, ver, next)                                      \
  21     ((id) |                                                             \
  22      ((ver) << PCI_EXT_CAP_VER_SHIFT) |                                 \
  23      ((next) << PCI_EXT_CAP_NEXT_SHIFT))
  24
  25 #define PCI_EXT_CAP_ALIGN               4
  26 #define PCI_EXT_CAP_ALIGNUP(x)                                  \
  27     (((x) + PCI_EXT_CAP_ALIGN - 1) & ~(PCI_EXT_CAP_ALIGN - 1))
  28
  29 /* PCI_EXP_FLAGS */
  30 #define PCI_EXP_FLAGS_VER1              1
  31 #define PCI_EXP_FLAGS_VER2              2
  32 #define PCI_EXP_FLAGS_IRQ_SHIFT         ctz32(PCI_EXP_FLAGS_IRQ)
  33 #define PCI_EXP_FLAGS_TYPE_SHIFT        ctz32(PCI_EXP_FLAGS_TYPE)
  34
  35 /* PCI_EXP_LINK{CAP, STA} */
  36 /* link speed */
  37 typedef enum PCIExpLinkSpeed {
  38     QEMU_PCI_EXP_LNK_2_5GT = 1,
  39     QEMU_PCI_EXP_LNK_5GT,
  40     QEMU_PCI_EXP_LNK_8GT,
  41     QEMU_PCI_EXP_LNK_16GT,
  42 } PCIExpLinkSpeed;
  43
  44 #define QEMU_PCI_EXP_LNKCAP_MLS(speed)  (speed)
  45 #define QEMU_PCI_EXP_LNKSTA_CLS         QEMU_PCI_EXP_LNKCAP_MLS
  46
  47 typedef enum PCIExpLinkWidth {
  48     QEMU_PCI_EXP_LNK_X1 = 1,
  49     QEMU_PCI_EXP_LNK_X2 = 2,
  50     QEMU_PCI_EXP_LNK_X4 = 4,
  51     QEMU_PCI_EXP_LNK_X8 = 8,
  52     QEMU_PCI_EXP_LNK_X12 = 12,
  53     QEMU_PCI_EXP_LNK_X16 = 16,
  54     QEMU_PCI_EXP_LNK_X32 = 32,
  55 } PCIExpLinkWidth;
  56
  57 #define PCI_EXP_LNK_MLW_SHIFT           ctz32(PCI_EXP_LNKCAP_MLW)
  58 #define QEMU_PCI_EXP_LNKCAP_MLW(width)  (width << PCI_EXP_LNK_MLW_SHIFT)
  59 #define QEMU_PCI_EXP_LNKSTA_NLW         QEMU_PCI_EXP_LNKCAP_MLW
  60
  61 /* PCI_EXP_LINKCAP */
  62 #define PCI_EXP_LNKCAP_ASPMS_SHIFT      ctz32(PCI_EXP_LNKCAP_ASPMS)
  63 #define PCI_EXP_LNKCAP_ASPMS_0S         (1 << PCI_EXP_LNKCAP_ASPMS_SHIFT)
  64
  65 #define PCI_EXP_LNKCAP_PN_SHIFT         ctz32(PCI_EXP_LNKCAP_PN)
  66
  67 #define PCI_EXP_SLTCAP_PSN_SHIFT        ctz32(PCI_EXP_SLTCAP_PSN)
  68
  69 #define PCI_EXP_SLTCTL_SUPPORTED        \
  70             (PCI_EXP_SLTCTL_ABPE |      \
  71              PCI_EXP_SLTCTL_PDCE |      \
  72              PCI_EXP_SLTCTL_CCIE |      \
  73              PCI_EXP_SLTCTL_HPIE |      \
  74              PCI_EXP_SLTCTL_AIC |       \
  75              PCI_EXP_SLTCTL_PCC |       \
  76              PCI_EXP_SLTCTL_EIC)
  77
  78 #define PCI_EXP_DEVCAP2_EFF             0x100000
  79 #define PCI_EXP_DEVCAP2_EETLPP          0x200000
  80
  81 #define PCI_EXP_DEVCTL2_EETLPPB         0x8000
  82
  83 /* ARI */
  84 #define PCI_ARI_VER                     1
  85 #define PCI_ARI_SIZEOF                  8
  86
  87 /* AER */
  88 #define PCI_ERR_VER                     2
  89 #define PCI_ERR_SIZEOF                  0x48
  90
  91 #define PCI_ERR_UNC_SDN                 0x00000020      /* surprise down */
  92 #define PCI_ERR_UNC_ACSV                0x00200000      /* ACS Violation */
  93 #define PCI_ERR_UNC_INTN                0x00400000      /* Internal Error */
  94 #define PCI_ERR_UNC_MCBTLP              0x00800000      /* MC Blcoked TLP */
  95 #define PCI_ERR_UNC_ATOP_EBLOCKED       0x01000000      /* atomic op egress blocked */
  96 #define PCI_ERR_UNC_TLP_PRF_BLOCKED     0x02000000      /* TLP Prefix Blocked */
  97 #define PCI_ERR_COR_ADV_NONFATAL        0x00002000      /* Advisory Non-Fatal */
  98 #define PCI_ERR_COR_INTERNAL            0x00004000      /* Corrected Internal */
  99 #define PCI_ERR_COR_HL_OVERFLOW         0x00008000      /* Header Long Overflow */
 100 #define PCI_ERR_CAP_FEP_MASK            0x0000001f
 101 #define PCI_ERR_CAP_MHRC                0x00000200
 102 #define PCI_ERR_CAP_MHRE                0x00000400
 103 #define PCI_ERR_CAP_TLP                 0x00000800
 104
 105 #define PCI_ERR_HEADER_LOG_SIZE         16
 106 #define PCI_ERR_TLP_PREFIX_LOG          0x38
 107 #define PCI_ERR_TLP_PREFIX_LOG_SIZE     16
 108
 109 #define PCI_SEC_STATUS_RCV_SYSTEM_ERROR         0x4000
 110
 111 /* aer root error command/status */
 112 #define PCI_ERR_ROOT_CMD_EN_MASK        (PCI_ERR_ROOT_CMD_COR_EN |      \
 113                                          PCI_ERR_ROOT_CMD_NONFATAL_EN | \
 114                                          PCI_ERR_ROOT_CMD_FATAL_EN)
 115
 116 #define PCI_ERR_ROOT_IRQ_MAX            32
 117 #define PCI_ERR_ROOT_IRQ                0xf8000000
 118 #define PCI_ERR_ROOT_IRQ_SHIFT          ctz32(PCI_ERR_ROOT_IRQ)
 119 #define PCI_ERR_ROOT_STATUS_REPORT_MASK (PCI_ERR_ROOT_COR_RCV |         \
 120                                          PCI_ERR_ROOT_MULTI_COR_RCV |   \
 121                                          PCI_ERR_ROOT_UNCOR_RCV |       \
 122                                          PCI_ERR_ROOT_MULTI_UNCOR_RCV | \
 123                                          PCI_ERR_ROOT_FIRST_FATAL |     \
 124                                          PCI_ERR_ROOT_NONFATAL_RCV |    \
 125                                          PCI_ERR_ROOT_FATAL_RCV)
 126
 127 #define PCI_ERR_UNC_SUPPORTED           (PCI_ERR_UNC_DLP |              \
 128                                          PCI_ERR_UNC_SDN |              \
 129                                          PCI_ERR_UNC_POISON_TLP |       \
 130                                          PCI_ERR_UNC_FCP |              \
 131                                          PCI_ERR_UNC_COMP_TIME |        \
 132                                          PCI_ERR_UNC_COMP_ABORT |       \
 133                                          PCI_ERR_UNC_UNX_COMP |         \
 134                                          PCI_ERR_UNC_RX_OVER |          \
 135                                          PCI_ERR_UNC_MALF_TLP |         \
 136                                          PCI_ERR_UNC_ECRC |             \
 137                                          PCI_ERR_UNC_UNSUP |            \
 138                                          PCI_ERR_UNC_ACSV |             \
 139                                          PCI_ERR_UNC_INTN |             \
 140                                          PCI_ERR_UNC_MCBTLP |           \
 141                                          PCI_ERR_UNC_ATOP_EBLOCKED |    \
 142                                          PCI_ERR_UNC_TLP_PRF_BLOCKED)
 143
 144 #define PCI_ERR_UNC_MASK_DEFAULT        (PCI_ERR_UNC_INTN | \
 145                                          PCI_ERR_UNC_TLP_PRF_BLOCKED)
 146
 147 #define PCI_ERR_UNC_SEVERITY_DEFAULT    (PCI_ERR_UNC_DLP |              \
 148                                          PCI_ERR_UNC_SDN |              \
 149                                          PCI_ERR_UNC_FCP |              \
 150                                          PCI_ERR_UNC_RX_OVER |          \
 151                                          PCI_ERR_UNC_MALF_TLP |         \
 152                                          PCI_ERR_UNC_INTN)
 153
 154 #define PCI_ERR_COR_SUPPORTED           (PCI_ERR_COR_RCVR |             \
 155                                          PCI_ERR_COR_BAD_TLP |          \
 156                                          PCI_ERR_COR_BAD_DLLP |         \
 157                                          PCI_ERR_COR_REP_ROLL |         \
 158                                          PCI_ERR_COR_REP_TIMER |        \
 159                                          PCI_ERR_COR_ADV_NONFATAL |     \
 160                                          PCI_ERR_COR_INTERNAL |         \
 161                                          PCI_ERR_COR_HL_OVERFLOW)
 162
 163 #define PCI_ERR_COR_MASK_DEFAULT        (PCI_ERR_COR_ADV_NONFATAL |     \
 164                                          PCI_ERR_COR_INTERNAL |         \
 165                                          PCI_ERR_COR_HL_OVERFLOW)
 166
 167 /* ACS */
 168 #define PCI_ACS_VER                     0x1
 169 #define PCI_ACS_SIZEOF                  8
 170
 171 /* DOE Capability Register Fields */
 172 #define PCI_DOE_VER                     0x1
 173 #define PCI_DOE_SIZEOF                  24
 174
 175 #endif /* QEMU_PCIE_REGS_H */