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libqtest: Inline g_assert_no_errno()
[qemu/armbru.git] / hw / block / nvme.c
blobfc7dacb816c8cb61c075d2537b0618e0b0c6d9d1
1 /*
2 * QEMU NVM Express Controller
3 *
4 * Copyright (c) 2012, Intel Corporation
5 *
6 * Written by Keith Busch <keith.busch@intel.com>
7 *
8 * This code is licensed under the GNU GPL v2 or later.
9 */
10
11 /**
12 * Reference Specs: http://www.nvmexpress.org, 1.2, 1.1, 1.0e
13 *
14 * http://www.nvmexpress.org/resources/
15 */
16
17 /**
18 * Usage: add options:
19 * -drive file=<file>,if=none,id=<drive_id>
20 * -device nvme,drive=<drive_id>,serial=<serial>,id=<id[optional]>, \
21 * cmb_size_mb=<cmb_size_mb[optional]>, \
22 * num_queues=<N[optional]>
23 *
24 * Note cmb_size_mb denotes size of CMB in MB. CMB is assumed to be at
25 * offset 0 in BAR2 and supports only WDS, RDS and SQS for now.
26 */
27
28 #include "qemu/osdep.h"
29 #include "qemu/units.h"
30 #include "hw/block/block.h"
31 #include "hw/hw.h"
32 #include "hw/pci/msix.h"
33 #include "hw/pci/pci.h"
34 #include "sysemu/sysemu.h"
35 #include "qapi/error.h"
36 #include "qapi/visitor.h"
37 #include "sysemu/block-backend.h"
38
39 #include "qemu/log.h"
40 #include "qemu/cutils.h"
41 #include "trace.h"
42 #include "nvme.h"
43
44 #define NVME_GUEST_ERR(trace, fmt, ...) \
45 do { \
46 (trace_##trace)(__VA_ARGS__); \
47 qemu_log_mask(LOG_GUEST_ERROR, #trace \
48 " in %s: " fmt "\n", __func__, ## __VA_ARGS__); \
49 } while (0)
50
51 static void nvme_process_sq(void *opaque);
52
53 static void nvme_addr_read(NvmeCtrl *n, hwaddr addr, void *buf, int size)
54 {
55 if (n->cmbsz && addr >= n->ctrl_mem.addr &&
56 addr < (n->ctrl_mem.addr + int128_get64(n->ctrl_mem.size))) {
57 memcpy(buf, (void *)&n->cmbuf[addr - n->ctrl_mem.addr], size);
58 } else {
59 pci_dma_read(&n->parent_obj, addr, buf, size);
60 }
61 }
62
63 static int nvme_check_sqid(NvmeCtrl *n, uint16_t sqid)
64 {
65 return sqid < n->num_queues && n->sq[sqid] != NULL ? 0 : -1;
66 }
67
68 static int nvme_check_cqid(NvmeCtrl *n, uint16_t cqid)
69 {
70 return cqid < n->num_queues && n->cq[cqid] != NULL ? 0 : -1;
71 }
72
73 static void nvme_inc_cq_tail(NvmeCQueue *cq)
74 {
75 cq->tail++;
76 if (cq->tail >= cq->size) {
77 cq->tail = 0;
78 cq->phase = !cq->phase;
79 }
80 }
81
82 static void nvme_inc_sq_head(NvmeSQueue *sq)
83 {
84 sq->head = (sq->head + 1) % sq->size;
85 }
86
87 static uint8_t nvme_cq_full(NvmeCQueue *cq)
88 {
89 return (cq->tail + 1) % cq->size == cq->head;
90 }
91
92 static uint8_t nvme_sq_empty(NvmeSQueue *sq)
93 {
94 return sq->head == sq->tail;
95 }
96
97 static void nvme_irq_check(NvmeCtrl *n)
98 {
99 if (msix_enabled(&(n->parent_obj))) {
100 return;
101 }
102 if (~n->bar.intms & n->irq_status) {
103 pci_irq_assert(&n->parent_obj);
104 } else {
105 pci_irq_deassert(&n->parent_obj);
106 }
107 }
108
109 static void nvme_irq_assert(NvmeCtrl *n, NvmeCQueue *cq)
110 {
111 if (cq->irq_enabled) {
112 if (msix_enabled(&(n->parent_obj))) {
113 trace_nvme_irq_msix(cq->vector);
114 msix_notify(&(n->parent_obj), cq->vector);
115 } else {
116 trace_nvme_irq_pin();
117 assert(cq->cqid < 64);
118 n->irq_status |= 1 << cq->cqid;
119 nvme_irq_check(n);
120 }
121 } else {
122 trace_nvme_irq_masked();
123 }
124 }
125
126 static void nvme_irq_deassert(NvmeCtrl *n, NvmeCQueue *cq)
127 {
128 if (cq->irq_enabled) {
129 if (msix_enabled(&(n->parent_obj))) {
130 return;
131 } else {
132 assert(cq->cqid < 64);
133 n->irq_status &= ~(1 << cq->cqid);
134 nvme_irq_check(n);
135 }
136 }
137 }
138
139 static uint16_t nvme_map_prp(QEMUSGList *qsg, QEMUIOVector *iov, uint64_t prp1,
140 uint64_t prp2, uint32_t len, NvmeCtrl *n)
141 {
142 hwaddr trans_len = n->page_size - (prp1 % n->page_size);
143 trans_len = MIN(len, trans_len);
144 int num_prps = (len >> n->page_bits) + 1;
145
146 if (unlikely(!prp1)) {
147 trace_nvme_err_invalid_prp();
148 return NVME_INVALID_FIELD | NVME_DNR;
149 } else if (n->cmbsz && prp1 >= n->ctrl_mem.addr &&
150 prp1 < n->ctrl_mem.addr + int128_get64(n->ctrl_mem.size)) {
151 qsg->nsg = 0;
152 qemu_iovec_init(iov, num_prps);
153 qemu_iovec_add(iov, (void *)&n->cmbuf[prp1 - n->ctrl_mem.addr], trans_len);
154 } else {
155 pci_dma_sglist_init(qsg, &n->parent_obj, num_prps);
156 qemu_sglist_add(qsg, prp1, trans_len);
157 }
158 len -= trans_len;
159 if (len) {
160 if (unlikely(!prp2)) {
161 trace_nvme_err_invalid_prp2_missing();
162 goto unmap;
163 }
164 if (len > n->page_size) {
165 uint64_t prp_list[n->max_prp_ents];
166 uint32_t nents, prp_trans;
167 int i = 0;
168
169 nents = (len + n->page_size - 1) >> n->page_bits;
170 prp_trans = MIN(n->max_prp_ents, nents) * sizeof(uint64_t);
171 nvme_addr_read(n, prp2, (void *)prp_list, prp_trans);
172 while (len != 0) {
173 uint64_t prp_ent = le64_to_cpu(prp_list[i]);
174
175 if (i == n->max_prp_ents - 1 && len > n->page_size) {
176 if (unlikely(!prp_ent || prp_ent & (n->page_size - 1))) {
177 trace_nvme_err_invalid_prplist_ent(prp_ent);
178 goto unmap;
179 }
180
181 i = 0;
182 nents = (len + n->page_size - 1) >> n->page_bits;
183 prp_trans = MIN(n->max_prp_ents, nents) * sizeof(uint64_t);
184 nvme_addr_read(n, prp_ent, (void *)prp_list,
185 prp_trans);
186 prp_ent = le64_to_cpu(prp_list[i]);
187 }
188
189 if (unlikely(!prp_ent || prp_ent & (n->page_size - 1))) {
190 trace_nvme_err_invalid_prplist_ent(prp_ent);
191 goto unmap;
192 }
193
194 trans_len = MIN(len, n->page_size);
195 if (qsg->nsg){
196 qemu_sglist_add(qsg, prp_ent, trans_len);
197 } else {
198 qemu_iovec_add(iov, (void *)&n->cmbuf[prp_ent - n->ctrl_mem.addr], trans_len);
199 }
200 len -= trans_len;
201 i++;
202 }
203 } else {
204 if (unlikely(prp2 & (n->page_size - 1))) {
205 trace_nvme_err_invalid_prp2_align(prp2);
206 goto unmap;
207 }
208 if (qsg->nsg) {
209 qemu_sglist_add(qsg, prp2, len);
210 } else {
211 qemu_iovec_add(iov, (void *)&n->cmbuf[prp2 - n->ctrl_mem.addr], trans_len);
212 }
213 }
214 }
215 return NVME_SUCCESS;
216
217 unmap:
218 qemu_sglist_destroy(qsg);
219 return NVME_INVALID_FIELD | NVME_DNR;
220 }
221
222 static uint16_t nvme_dma_read_prp(NvmeCtrl *n, uint8_t *ptr, uint32_t len,
223 uint64_t prp1, uint64_t prp2)
224 {
225 QEMUSGList qsg;
226 QEMUIOVector iov;
227 uint16_t status = NVME_SUCCESS;
228
229 trace_nvme_dma_read(prp1, prp2);
230
231 if (nvme_map_prp(&qsg, &iov, prp1, prp2, len, n)) {
232 return NVME_INVALID_FIELD | NVME_DNR;
233 }
234 if (qsg.nsg > 0) {
235 if (unlikely(dma_buf_read(ptr, len, &qsg))) {
236 trace_nvme_err_invalid_dma();
237 status = NVME_INVALID_FIELD | NVME_DNR;
238 }
239 qemu_sglist_destroy(&qsg);
240 } else {
241 if (unlikely(qemu_iovec_to_buf(&iov, 0, ptr, len) != len)) {
242 trace_nvme_err_invalid_dma();
243 status = NVME_INVALID_FIELD | NVME_DNR;
244 }
245 qemu_iovec_destroy(&iov);
246 }
247 return status;
248 }
249
250 static void nvme_post_cqes(void *opaque)
251 {
252 NvmeCQueue *cq = opaque;
253 NvmeCtrl *n = cq->ctrl;
254 NvmeRequest *req, *next;
255
256 QTAILQ_FOREACH_SAFE(req, &cq->req_list, entry, next) {
257 NvmeSQueue *sq;
258 hwaddr addr;
259
260 if (nvme_cq_full(cq)) {
261 break;
262 }
263
264 QTAILQ_REMOVE(&cq->req_list, req, entry);
265 sq = req->sq;
266 req->cqe.status = cpu_to_le16((req->status << 1) | cq->phase);
267 req->cqe.sq_id = cpu_to_le16(sq->sqid);
268 req->cqe.sq_head = cpu_to_le16(sq->head);
269 addr = cq->dma_addr + cq->tail * n->cqe_size;
270 nvme_inc_cq_tail(cq);
271 pci_dma_write(&n->parent_obj, addr, (void *)&req->cqe,
272 sizeof(req->cqe));
273 QTAILQ_INSERT_TAIL(&sq->req_list, req, entry);
274 }
275 nvme_irq_assert(n, cq);
276 }
277
278 static void nvme_enqueue_req_completion(NvmeCQueue *cq, NvmeRequest *req)
279 {
280 assert(cq->cqid == req->sq->cqid);
281 QTAILQ_REMOVE(&req->sq->out_req_list, req, entry);
282 QTAILQ_INSERT_TAIL(&cq->req_list, req, entry);
283 timer_mod(cq->timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + 500);
284 }
285
286 static void nvme_rw_cb(void *opaque, int ret)
287 {
288 NvmeRequest *req = opaque;
289 NvmeSQueue *sq = req->sq;
290 NvmeCtrl *n = sq->ctrl;
291 NvmeCQueue *cq = n->cq[sq->cqid];
292
293 if (!ret) {
294 block_acct_done(blk_get_stats(n->conf.blk), &req->acct);
295 req->status = NVME_SUCCESS;
296 } else {
297 block_acct_failed(blk_get_stats(n->conf.blk), &req->acct);
298 req->status = NVME_INTERNAL_DEV_ERROR;
299 }
300 if (req->has_sg) {
301 qemu_sglist_destroy(&req->qsg);
302 }
303 nvme_enqueue_req_completion(cq, req);
304 }
305
306 static uint16_t nvme_flush(NvmeCtrl *n, NvmeNamespace *ns, NvmeCmd *cmd,
307 NvmeRequest *req)
308 {
309 req->has_sg = false;
310 block_acct_start(blk_get_stats(n->conf.blk), &req->acct, 0,
311 BLOCK_ACCT_FLUSH);
312 req->aiocb = blk_aio_flush(n->conf.blk, nvme_rw_cb, req);
313
314 return NVME_NO_COMPLETE;
315 }
316
317 static uint16_t nvme_write_zeros(NvmeCtrl *n, NvmeNamespace *ns, NvmeCmd *cmd,
318 NvmeRequest *req)
319 {
320 NvmeRwCmd *rw = (NvmeRwCmd *)cmd;
321 const uint8_t lba_index = NVME_ID_NS_FLBAS_INDEX(ns->id_ns.flbas);
322 const uint8_t data_shift = ns->id_ns.lbaf[lba_index].ds;
323 uint64_t slba = le64_to_cpu(rw->slba);
324 uint32_t nlb = le16_to_cpu(rw->nlb) + 1;
325 uint64_t aio_slba = slba << (data_shift - BDRV_SECTOR_BITS);
326 uint32_t aio_nlb = nlb << (data_shift - BDRV_SECTOR_BITS);
327
328 if (unlikely(slba + nlb > ns->id_ns.nsze)) {
329 trace_nvme_err_invalid_lba_range(slba, nlb, ns->id_ns.nsze);
330 return NVME_LBA_RANGE | NVME_DNR;
331 }
332
333 req->has_sg = false;
334 block_acct_start(blk_get_stats(n->conf.blk), &req->acct, 0,
335 BLOCK_ACCT_WRITE);
336 req->aiocb = blk_aio_pwrite_zeroes(n->conf.blk, aio_slba, aio_nlb,
337 BDRV_REQ_MAY_UNMAP, nvme_rw_cb, req);
338 return NVME_NO_COMPLETE;
339 }
340
341 static uint16_t nvme_rw(NvmeCtrl *n, NvmeNamespace *ns, NvmeCmd *cmd,
342 NvmeRequest *req)
343 {
344 NvmeRwCmd *rw = (NvmeRwCmd *)cmd;
345 uint32_t nlb = le32_to_cpu(rw->nlb) + 1;
346 uint64_t slba = le64_to_cpu(rw->slba);
347 uint64_t prp1 = le64_to_cpu(rw->prp1);
348 uint64_t prp2 = le64_to_cpu(rw->prp2);
349
350 uint8_t lba_index = NVME_ID_NS_FLBAS_INDEX(ns->id_ns.flbas);
351 uint8_t data_shift = ns->id_ns.lbaf[lba_index].ds;
352 uint64_t data_size = (uint64_t)nlb << data_shift;
353 uint64_t data_offset = slba << data_shift;
354 int is_write = rw->opcode == NVME_CMD_WRITE ? 1 : 0;
355 enum BlockAcctType acct = is_write ? BLOCK_ACCT_WRITE : BLOCK_ACCT_READ;
356
357 trace_nvme_rw(is_write ? "write" : "read", nlb, data_size, slba);
358
359 if (unlikely((slba + nlb) > ns->id_ns.nsze)) {
360 block_acct_invalid(blk_get_stats(n->conf.blk), acct);
361 trace_nvme_err_invalid_lba_range(slba, nlb, ns->id_ns.nsze);
362 return NVME_LBA_RANGE | NVME_DNR;
363 }
364
365 if (nvme_map_prp(&req->qsg, &req->iov, prp1, prp2, data_size, n)) {
366 block_acct_invalid(blk_get_stats(n->conf.blk), acct);
367 return NVME_INVALID_FIELD | NVME_DNR;
368 }
369
370 dma_acct_start(n->conf.blk, &req->acct, &req->qsg, acct);
371 if (req->qsg.nsg > 0) {
372 req->has_sg = true;
373 req->aiocb = is_write ?
374 dma_blk_write(n->conf.blk, &req->qsg, data_offset, BDRV_SECTOR_SIZE,
375 nvme_rw_cb, req) :
376 dma_blk_read(n->conf.blk, &req->qsg, data_offset, BDRV_SECTOR_SIZE,
377 nvme_rw_cb, req);
378 } else {
379 req->has_sg = false;
380 req->aiocb = is_write ?
381 blk_aio_pwritev(n->conf.blk, data_offset, &req->iov, 0, nvme_rw_cb,
382 req) :
383 blk_aio_preadv(n->conf.blk, data_offset, &req->iov, 0, nvme_rw_cb,
384 req);
385 }
386
387 return NVME_NO_COMPLETE;
388 }
389
390 static uint16_t nvme_io_cmd(NvmeCtrl *n, NvmeCmd *cmd, NvmeRequest *req)
391 {
392 NvmeNamespace *ns;
393 uint32_t nsid = le32_to_cpu(cmd->nsid);
394
395 if (unlikely(nsid == 0 || nsid > n->num_namespaces)) {
396 trace_nvme_err_invalid_ns(nsid, n->num_namespaces);
397 return NVME_INVALID_NSID | NVME_DNR;
398 }
399
400 ns = &n->namespaces[nsid - 1];
401 switch (cmd->opcode) {
402 case NVME_CMD_FLUSH:
403 return nvme_flush(n, ns, cmd, req);
404 case NVME_CMD_WRITE_ZEROS:
405 return nvme_write_zeros(n, ns, cmd, req);
406 case NVME_CMD_WRITE:
407 case NVME_CMD_READ:
408 return nvme_rw(n, ns, cmd, req);
409 default:
410 trace_nvme_err_invalid_opc(cmd->opcode);
411 return NVME_INVALID_OPCODE | NVME_DNR;
412 }
413 }
414
415 static void nvme_free_sq(NvmeSQueue *sq, NvmeCtrl *n)
416 {
417 n->sq[sq->sqid] = NULL;
418 timer_del(sq->timer);
419 timer_free(sq->timer);
420 g_free(sq->io_req);
421 if (sq->sqid) {
422 g_free(sq);
423 }
424 }
425
426 static uint16_t nvme_del_sq(NvmeCtrl *n, NvmeCmd *cmd)
427 {
428 NvmeDeleteQ *c = (NvmeDeleteQ *)cmd;
429 NvmeRequest *req, *next;
430 NvmeSQueue *sq;
431 NvmeCQueue *cq;
432 uint16_t qid = le16_to_cpu(c->qid);
433
434 if (unlikely(!qid || nvme_check_sqid(n, qid))) {
435 trace_nvme_err_invalid_del_sq(qid);
436 return NVME_INVALID_QID | NVME_DNR;
437 }
438
439 trace_nvme_del_sq(qid);
440
441 sq = n->sq[qid];
442 while (!QTAILQ_EMPTY(&sq->out_req_list)) {
443 req = QTAILQ_FIRST(&sq->out_req_list);
444 assert(req->aiocb);
445 blk_aio_cancel(req->aiocb);
446 }
447 if (!nvme_check_cqid(n, sq->cqid)) {
448 cq = n->cq[sq->cqid];
449 QTAILQ_REMOVE(&cq->sq_list, sq, entry);
450
451 nvme_post_cqes(cq);
452 QTAILQ_FOREACH_SAFE(req, &cq->req_list, entry, next) {
453 if (req->sq == sq) {
454 QTAILQ_REMOVE(&cq->req_list, req, entry);
455 QTAILQ_INSERT_TAIL(&sq->req_list, req, entry);
456 }
457 }
458 }
459
460 nvme_free_sq(sq, n);
461 return NVME_SUCCESS;
462 }
463
464 static void nvme_init_sq(NvmeSQueue *sq, NvmeCtrl *n, uint64_t dma_addr,
465 uint16_t sqid, uint16_t cqid, uint16_t size)
466 {
467 int i;
468 NvmeCQueue *cq;
469
470 sq->ctrl = n;
471 sq->dma_addr = dma_addr;
472 sq->sqid = sqid;
473 sq->size = size;
474 sq->cqid = cqid;
475 sq->head = sq->tail = 0;
476 sq->io_req = g_new(NvmeRequest, sq->size);
477
478 QTAILQ_INIT(&sq->req_list);
479 QTAILQ_INIT(&sq->out_req_list);
480 for (i = 0; i < sq->size; i++) {
481 sq->io_req[i].sq = sq;
482 QTAILQ_INSERT_TAIL(&(sq->req_list), &sq->io_req[i], entry);
483 }
484 sq->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, nvme_process_sq, sq);
485
486 assert(n->cq[cqid]);
487 cq = n->cq[cqid];
488 QTAILQ_INSERT_TAIL(&(cq->sq_list), sq, entry);
489 n->sq[sqid] = sq;
490 }
491
492 static uint16_t nvme_create_sq(NvmeCtrl *n, NvmeCmd *cmd)
493 {
494 NvmeSQueue *sq;
495 NvmeCreateSq *c = (NvmeCreateSq *)cmd;
496
497 uint16_t cqid = le16_to_cpu(c->cqid);
498 uint16_t sqid = le16_to_cpu(c->sqid);
499 uint16_t qsize = le16_to_cpu(c->qsize);
500 uint16_t qflags = le16_to_cpu(c->sq_flags);
501 uint64_t prp1 = le64_to_cpu(c->prp1);
502
503 trace_nvme_create_sq(prp1, sqid, cqid, qsize, qflags);
504
505 if (unlikely(!cqid || nvme_check_cqid(n, cqid))) {
506 trace_nvme_err_invalid_create_sq_cqid(cqid);
507 return NVME_INVALID_CQID | NVME_DNR;
508 }
509 if (unlikely(!sqid || !nvme_check_sqid(n, sqid))) {
510 trace_nvme_err_invalid_create_sq_sqid(sqid);
511 return NVME_INVALID_QID | NVME_DNR;
512 }
513 if (unlikely(!qsize || qsize > NVME_CAP_MQES(n->bar.cap))) {
514 trace_nvme_err_invalid_create_sq_size(qsize);
515 return NVME_MAX_QSIZE_EXCEEDED | NVME_DNR;
516 }
517 if (unlikely(!prp1 || prp1 & (n->page_size - 1))) {
518 trace_nvme_err_invalid_create_sq_addr(prp1);
519 return NVME_INVALID_FIELD | NVME_DNR;
520 }
521 if (unlikely(!(NVME_SQ_FLAGS_PC(qflags)))) {
522 trace_nvme_err_invalid_create_sq_qflags(NVME_SQ_FLAGS_PC(qflags));
523 return NVME_INVALID_FIELD | NVME_DNR;
524 }
525 sq = g_malloc0(sizeof(*sq));
526 nvme_init_sq(sq, n, prp1, sqid, cqid, qsize + 1);
527 return NVME_SUCCESS;
528 }
529
530 static void nvme_free_cq(NvmeCQueue *cq, NvmeCtrl *n)
531 {
532 n->cq[cq->cqid] = NULL;
533 timer_del(cq->timer);
534 timer_free(cq->timer);
535 msix_vector_unuse(&n->parent_obj, cq->vector);
536 if (cq->cqid) {
537 g_free(cq);
538 }
539 }
540
541 static uint16_t nvme_del_cq(NvmeCtrl *n, NvmeCmd *cmd)
542 {
543 NvmeDeleteQ *c = (NvmeDeleteQ *)cmd;
544 NvmeCQueue *cq;
545 uint16_t qid = le16_to_cpu(c->qid);
546
547 if (unlikely(!qid || nvme_check_cqid(n, qid))) {
548 trace_nvme_err_invalid_del_cq_cqid(qid);
549 return NVME_INVALID_CQID | NVME_DNR;
550 }
551
552 cq = n->cq[qid];
553 if (unlikely(!QTAILQ_EMPTY(&cq->sq_list))) {
554 trace_nvme_err_invalid_del_cq_notempty(qid);
555 return NVME_INVALID_QUEUE_DEL;
556 }
557 trace_nvme_del_cq(qid);
558 nvme_free_cq(cq, n);
559 return NVME_SUCCESS;
560 }
561
562 static void nvme_init_cq(NvmeCQueue *cq, NvmeCtrl *n, uint64_t dma_addr,
563 uint16_t cqid, uint16_t vector, uint16_t size, uint16_t irq_enabled)
564 {
565 cq->ctrl = n;
566 cq->cqid = cqid;
567 cq->size = size;
568 cq->dma_addr = dma_addr;
569 cq->phase = 1;
570 cq->irq_enabled = irq_enabled;
571 cq->vector = vector;
572 cq->head = cq->tail = 0;
573 QTAILQ_INIT(&cq->req_list);
574 QTAILQ_INIT(&cq->sq_list);
575 msix_vector_use(&n->parent_obj, cq->vector);
576 n->cq[cqid] = cq;
577 cq->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, nvme_post_cqes, cq);
578 }
579
580 static uint16_t nvme_create_cq(NvmeCtrl *n, NvmeCmd *cmd)
581 {
582 NvmeCQueue *cq;
583 NvmeCreateCq *c = (NvmeCreateCq *)cmd;
584 uint16_t cqid = le16_to_cpu(c->cqid);
585 uint16_t vector = le16_to_cpu(c->irq_vector);
586 uint16_t qsize = le16_to_cpu(c->qsize);
587 uint16_t qflags = le16_to_cpu(c->cq_flags);
588 uint64_t prp1 = le64_to_cpu(c->prp1);
589
590 trace_nvme_create_cq(prp1, cqid, vector, qsize, qflags,
591 NVME_CQ_FLAGS_IEN(qflags) != 0);
592
593 if (unlikely(!cqid || !nvme_check_cqid(n, cqid))) {
594 trace_nvme_err_invalid_create_cq_cqid(cqid);
595 return NVME_INVALID_CQID | NVME_DNR;
596 }
597 if (unlikely(!qsize || qsize > NVME_CAP_MQES(n->bar.cap))) {
598 trace_nvme_err_invalid_create_cq_size(qsize);
599 return NVME_MAX_QSIZE_EXCEEDED | NVME_DNR;
600 }
601 if (unlikely(!prp1)) {
602 trace_nvme_err_invalid_create_cq_addr(prp1);
603 return NVME_INVALID_FIELD | NVME_DNR;
604 }
605 if (unlikely(vector > n->num_queues)) {
606 trace_nvme_err_invalid_create_cq_vector(vector);
607 return NVME_INVALID_IRQ_VECTOR | NVME_DNR;
608 }
609 if (unlikely(!(NVME_CQ_FLAGS_PC(qflags)))) {
610 trace_nvme_err_invalid_create_cq_qflags(NVME_CQ_FLAGS_PC(qflags));
611 return NVME_INVALID_FIELD | NVME_DNR;
612 }
613
614 cq = g_malloc0(sizeof(*cq));
615 nvme_init_cq(cq, n, prp1, cqid, vector, qsize + 1,
616 NVME_CQ_FLAGS_IEN(qflags));
617 return NVME_SUCCESS;
618 }
619
620 static uint16_t nvme_identify_ctrl(NvmeCtrl *n, NvmeIdentify *c)
621 {
622 uint64_t prp1 = le64_to_cpu(c->prp1);
623 uint64_t prp2 = le64_to_cpu(c->prp2);
624
625 trace_nvme_identify_ctrl();
626
627 return nvme_dma_read_prp(n, (uint8_t *)&n->id_ctrl, sizeof(n->id_ctrl),
628 prp1, prp2);
629 }
630
631 static uint16_t nvme_identify_ns(NvmeCtrl *n, NvmeIdentify *c)
632 {
633 NvmeNamespace *ns;
634 uint32_t nsid = le32_to_cpu(c->nsid);
635 uint64_t prp1 = le64_to_cpu(c->prp1);
636 uint64_t prp2 = le64_to_cpu(c->prp2);
637
638 trace_nvme_identify_ns(nsid);
639
640 if (unlikely(nsid == 0 || nsid > n->num_namespaces)) {
641 trace_nvme_err_invalid_ns(nsid, n->num_namespaces);
642 return NVME_INVALID_NSID | NVME_DNR;
643 }
644
645 ns = &n->namespaces[nsid - 1];
646
647 return nvme_dma_read_prp(n, (uint8_t *)&ns->id_ns, sizeof(ns->id_ns),
648 prp1, prp2);
649 }
650
651 static uint16_t nvme_identify_nslist(NvmeCtrl *n, NvmeIdentify *c)
652 {
653 static const int data_len = 4 * KiB;
654 uint32_t min_nsid = le32_to_cpu(c->nsid);
655 uint64_t prp1 = le64_to_cpu(c->prp1);
656 uint64_t prp2 = le64_to_cpu(c->prp2);
657 uint32_t *list;
658 uint16_t ret;
659 int i, j = 0;
660
661 trace_nvme_identify_nslist(min_nsid);
662
663 list = g_malloc0(data_len);
664 for (i = 0; i < n->num_namespaces; i++) {
665 if (i < min_nsid) {
666 continue;
667 }
668 list[j++] = cpu_to_le32(i + 1);
669 if (j == data_len / sizeof(uint32_t)) {
670 break;
671 }
672 }
673 ret = nvme_dma_read_prp(n, (uint8_t *)list, data_len, prp1, prp2);
674 g_free(list);
675 return ret;
676 }
677
678
679 static uint16_t nvme_identify(NvmeCtrl *n, NvmeCmd *cmd)
680 {
681 NvmeIdentify *c = (NvmeIdentify *)cmd;
682
683 switch (le32_to_cpu(c->cns)) {
684 case 0x00:
685 return nvme_identify_ns(n, c);
686 case 0x01:
687 return nvme_identify_ctrl(n, c);
688 case 0x02:
689 return nvme_identify_nslist(n, c);
690 default:
691 trace_nvme_err_invalid_identify_cns(le32_to_cpu(c->cns));
692 return NVME_INVALID_FIELD | NVME_DNR;
693 }
694 }
695
696 static uint16_t nvme_get_feature(NvmeCtrl *n, NvmeCmd *cmd, NvmeRequest *req)
697 {
698 uint32_t dw10 = le32_to_cpu(cmd->cdw10);
699 uint32_t result;
700
701 switch (dw10) {
702 case NVME_VOLATILE_WRITE_CACHE:
703 result = blk_enable_write_cache(n->conf.blk);
704 trace_nvme_getfeat_vwcache(result ? "enabled" : "disabled");
705 break;
706 case NVME_NUMBER_OF_QUEUES:
707 result = cpu_to_le32((n->num_queues - 2) | ((n->num_queues - 2) << 16));
708 trace_nvme_getfeat_numq(result);
709 break;
710 default:
711 trace_nvme_err_invalid_getfeat(dw10);
712 return NVME_INVALID_FIELD | NVME_DNR;
713 }
714
715 req->cqe.result = result;
716 return NVME_SUCCESS;
717 }
718
719 static uint16_t nvme_set_feature(NvmeCtrl *n, NvmeCmd *cmd, NvmeRequest *req)
720 {
721 uint32_t dw10 = le32_to_cpu(cmd->cdw10);
722 uint32_t dw11 = le32_to_cpu(cmd->cdw11);
723
724 switch (dw10) {
725 case NVME_VOLATILE_WRITE_CACHE:
726 blk_set_enable_write_cache(n->conf.blk, dw11 & 1);
727 break;
728 case NVME_NUMBER_OF_QUEUES:
729 trace_nvme_setfeat_numq((dw11 & 0xFFFF) + 1,
730 ((dw11 >> 16) & 0xFFFF) + 1,
731 n->num_queues - 1, n->num_queues - 1);
732 req->cqe.result =
733 cpu_to_le32((n->num_queues - 2) | ((n->num_queues - 2) << 16));
734 break;
735 default:
736 trace_nvme_err_invalid_setfeat(dw10);
737 return NVME_INVALID_FIELD | NVME_DNR;
738 }
739 return NVME_SUCCESS;
740 }
741
742 static uint16_t nvme_admin_cmd(NvmeCtrl *n, NvmeCmd *cmd, NvmeRequest *req)
743 {
744 switch (cmd->opcode) {
745 case NVME_ADM_CMD_DELETE_SQ:
746 return nvme_del_sq(n, cmd);
747 case NVME_ADM_CMD_CREATE_SQ:
748 return nvme_create_sq(n, cmd);
749 case NVME_ADM_CMD_DELETE_CQ:
750 return nvme_del_cq(n, cmd);
751 case NVME_ADM_CMD_CREATE_CQ:
752 return nvme_create_cq(n, cmd);
753 case NVME_ADM_CMD_IDENTIFY:
754 return nvme_identify(n, cmd);
755 case NVME_ADM_CMD_SET_FEATURES:
756 return nvme_set_feature(n, cmd, req);
757 case NVME_ADM_CMD_GET_FEATURES:
758 return nvme_get_feature(n, cmd, req);
759 default:
760 trace_nvme_err_invalid_admin_opc(cmd->opcode);
761 return NVME_INVALID_OPCODE | NVME_DNR;
762 }
763 }
764
765 static void nvme_process_sq(void *opaque)
766 {
767 NvmeSQueue *sq = opaque;
768 NvmeCtrl *n = sq->ctrl;
769 NvmeCQueue *cq = n->cq[sq->cqid];
770
771 uint16_t status;
772 hwaddr addr;
773 NvmeCmd cmd;
774 NvmeRequest *req;
775
776 while (!(nvme_sq_empty(sq) || QTAILQ_EMPTY(&sq->req_list))) {
777 addr = sq->dma_addr + sq->head * n->sqe_size;
778 nvme_addr_read(n, addr, (void *)&cmd, sizeof(cmd));
779 nvme_inc_sq_head(sq);
780
781 req = QTAILQ_FIRST(&sq->req_list);
782 QTAILQ_REMOVE(&sq->req_list, req, entry);
783 QTAILQ_INSERT_TAIL(&sq->out_req_list, req, entry);
784 memset(&req->cqe, 0, sizeof(req->cqe));
785 req->cqe.cid = cmd.cid;
786
787 status = sq->sqid ? nvme_io_cmd(n, &cmd, req) :
788 nvme_admin_cmd(n, &cmd, req);
789 if (status != NVME_NO_COMPLETE) {
790 req->status = status;
791 nvme_enqueue_req_completion(cq, req);
792 }
793 }
794 }
795
796 static void nvme_clear_ctrl(NvmeCtrl *n)
797 {
798 int i;
799
800 for (i = 0; i < n->num_queues; i++) {
801 if (n->sq[i] != NULL) {
802 nvme_free_sq(n->sq[i], n);
803 }
804 }
805 for (i = 0; i < n->num_queues; i++) {
806 if (n->cq[i] != NULL) {
807 nvme_free_cq(n->cq[i], n);
808 }
809 }
810
811 blk_flush(n->conf.blk);
812 n->bar.cc = 0;
813 }
814
815 static int nvme_start_ctrl(NvmeCtrl *n)
816 {
817 uint32_t page_bits = NVME_CC_MPS(n->bar.cc) + 12;
818 uint32_t page_size = 1 << page_bits;
819
820 if (unlikely(n->cq[0])) {
821 trace_nvme_err_startfail_cq();
822 return -1;
823 }
824 if (unlikely(n->sq[0])) {
825 trace_nvme_err_startfail_sq();
826 return -1;
827 }
828 if (unlikely(!n->bar.asq)) {
829 trace_nvme_err_startfail_nbarasq();
830 return -1;
831 }
832 if (unlikely(!n->bar.acq)) {
833 trace_nvme_err_startfail_nbaracq();
834 return -1;
835 }
836 if (unlikely(n->bar.asq & (page_size - 1))) {
837 trace_nvme_err_startfail_asq_misaligned(n->bar.asq);
838 return -1;
839 }
840 if (unlikely(n->bar.acq & (page_size - 1))) {
841 trace_nvme_err_startfail_acq_misaligned(n->bar.acq);
842 return -1;
843 }
844 if (unlikely(NVME_CC_MPS(n->bar.cc) <
845 NVME_CAP_MPSMIN(n->bar.cap))) {
846 trace_nvme_err_startfail_page_too_small(
847 NVME_CC_MPS(n->bar.cc),
848 NVME_CAP_MPSMIN(n->bar.cap));
849 return -1;
850 }
851 if (unlikely(NVME_CC_MPS(n->bar.cc) >
852 NVME_CAP_MPSMAX(n->bar.cap))) {
853 trace_nvme_err_startfail_page_too_large(
854 NVME_CC_MPS(n->bar.cc),
855 NVME_CAP_MPSMAX(n->bar.cap));
856 return -1;
857 }
858 if (unlikely(NVME_CC_IOCQES(n->bar.cc) <
859 NVME_CTRL_CQES_MIN(n->id_ctrl.cqes))) {
860 trace_nvme_err_startfail_cqent_too_small(
861 NVME_CC_IOCQES(n->bar.cc),
862 NVME_CTRL_CQES_MIN(n->bar.cap));
863 return -1;
864 }
865 if (unlikely(NVME_CC_IOCQES(n->bar.cc) >
866 NVME_CTRL_CQES_MAX(n->id_ctrl.cqes))) {
867 trace_nvme_err_startfail_cqent_too_large(
868 NVME_CC_IOCQES(n->bar.cc),
869 NVME_CTRL_CQES_MAX(n->bar.cap));
870 return -1;
871 }
872 if (unlikely(NVME_CC_IOSQES(n->bar.cc) <
873 NVME_CTRL_SQES_MIN(n->id_ctrl.sqes))) {
874 trace_nvme_err_startfail_sqent_too_small(
875 NVME_CC_IOSQES(n->bar.cc),
876 NVME_CTRL_SQES_MIN(n->bar.cap));
877 return -1;
878 }
879 if (unlikely(NVME_CC_IOSQES(n->bar.cc) >
880 NVME_CTRL_SQES_MAX(n->id_ctrl.sqes))) {
881 trace_nvme_err_startfail_sqent_too_large(
882 NVME_CC_IOSQES(n->bar.cc),
883 NVME_CTRL_SQES_MAX(n->bar.cap));
884 return -1;
885 }
886 if (unlikely(!NVME_AQA_ASQS(n->bar.aqa))) {
887 trace_nvme_err_startfail_asqent_sz_zero();
888 return -1;
889 }
890 if (unlikely(!NVME_AQA_ACQS(n->bar.aqa))) {
891 trace_nvme_err_startfail_acqent_sz_zero();
892 return -1;
893 }
894
895 n->page_bits = page_bits;
896 n->page_size = page_size;
897 n->max_prp_ents = n->page_size / sizeof(uint64_t);
898 n->cqe_size = 1 << NVME_CC_IOCQES(n->bar.cc);
899 n->sqe_size = 1 << NVME_CC_IOSQES(n->bar.cc);
900 nvme_init_cq(&n->admin_cq, n, n->bar.acq, 0, 0,
901 NVME_AQA_ACQS(n->bar.aqa) + 1, 1);
902 nvme_init_sq(&n->admin_sq, n, n->bar.asq, 0, 0,
903 NVME_AQA_ASQS(n->bar.aqa) + 1);
904
905 return 0;
906 }
907
908 static void nvme_write_bar(NvmeCtrl *n, hwaddr offset, uint64_t data,
909 unsigned size)
910 {
911 if (unlikely(offset & (sizeof(uint32_t) - 1))) {
912 NVME_GUEST_ERR(nvme_ub_mmiowr_misaligned32,
913 "MMIO write not 32-bit aligned,"
914 " offset=0x%"PRIx64"", offset);
915 /* should be ignored, fall through for now */
916 }
917
918 if (unlikely(size < sizeof(uint32_t))) {
919 NVME_GUEST_ERR(nvme_ub_mmiowr_toosmall,
920 "MMIO write smaller than 32-bits,"
921 " offset=0x%"PRIx64", size=%u",
922 offset, size);
923 /* should be ignored, fall through for now */
924 }
925
926 switch (offset) {
927 case 0xc: /* INTMS */
928 if (unlikely(msix_enabled(&(n->parent_obj)))) {
929 NVME_GUEST_ERR(nvme_ub_mmiowr_intmask_with_msix,
930 "undefined access to interrupt mask set"
931 " when MSI-X is enabled");
932 /* should be ignored, fall through for now */
933 }
934 n->bar.intms |= data & 0xffffffff;
935 n->bar.intmc = n->bar.intms;
936 trace_nvme_mmio_intm_set(data & 0xffffffff,
937 n->bar.intmc);
938 nvme_irq_check(n);
939 break;
940 case 0x10: /* INTMC */
941 if (unlikely(msix_enabled(&(n->parent_obj)))) {
942 NVME_GUEST_ERR(nvme_ub_mmiowr_intmask_with_msix,
943 "undefined access to interrupt mask clr"
944 " when MSI-X is enabled");
945 /* should be ignored, fall through for now */
946 }
947 n->bar.intms &= ~(data & 0xffffffff);
948 n->bar.intmc = n->bar.intms;
949 trace_nvme_mmio_intm_clr(data & 0xffffffff,
950 n->bar.intmc);
951 nvme_irq_check(n);
952 break;
953 case 0x14: /* CC */
954 trace_nvme_mmio_cfg(data & 0xffffffff);
955 /* Windows first sends data, then sends enable bit */
956 if (!NVME_CC_EN(data) && !NVME_CC_EN(n->bar.cc) &&
957 !NVME_CC_SHN(data) && !NVME_CC_SHN(n->bar.cc))
958 {
959 n->bar.cc = data;
960 }
961
962 if (NVME_CC_EN(data) && !NVME_CC_EN(n->bar.cc)) {
963 n->bar.cc = data;
964 if (unlikely(nvme_start_ctrl(n))) {
965 trace_nvme_err_startfail();
966 n->bar.csts = NVME_CSTS_FAILED;
967 } else {
968 trace_nvme_mmio_start_success();
969 n->bar.csts = NVME_CSTS_READY;
970 }
971 } else if (!NVME_CC_EN(data) && NVME_CC_EN(n->bar.cc)) {
972 trace_nvme_mmio_stopped();
973 nvme_clear_ctrl(n);
974 n->bar.csts &= ~NVME_CSTS_READY;
975 }
976 if (NVME_CC_SHN(data) && !(NVME_CC_SHN(n->bar.cc))) {
977 trace_nvme_mmio_shutdown_set();
978 nvme_clear_ctrl(n);
979 n->bar.cc = data;
980 n->bar.csts |= NVME_CSTS_SHST_COMPLETE;
981 } else if (!NVME_CC_SHN(data) && NVME_CC_SHN(n->bar.cc)) {
982 trace_nvme_mmio_shutdown_cleared();
983 n->bar.csts &= ~NVME_CSTS_SHST_COMPLETE;
984 n->bar.cc = data;
985 }
986 break;
987 case 0x1C: /* CSTS */
988 if (data & (1 << 4)) {
989 NVME_GUEST_ERR(nvme_ub_mmiowr_ssreset_w1c_unsupported,
990 "attempted to W1C CSTS.NSSRO"
991 " but CAP.NSSRS is zero (not supported)");
992 } else if (data != 0) {
993 NVME_GUEST_ERR(nvme_ub_mmiowr_ro_csts,
994 "attempted to set a read only bit"
995 " of controller status");
996 }
997 break;
998 case 0x20: /* NSSR */
999 if (data == 0x4E564D65) {
1000 trace_nvme_ub_mmiowr_ssreset_unsupported();
1001 } else {
1002 /* The spec says that writes of other values have no effect */
1003 return;
1004 }
1005 break;
1006 case 0x24: /* AQA */
1007 n->bar.aqa = data & 0xffffffff;
1008 trace_nvme_mmio_aqattr(data & 0xffffffff);
1009 break;
1010 case 0x28: /* ASQ */
1011 n->bar.asq = data;
1012 trace_nvme_mmio_asqaddr(data);
1013 break;
1014 case 0x2c: /* ASQ hi */
1015 n->bar.asq |= data << 32;
1016 trace_nvme_mmio_asqaddr_hi(data, n->bar.asq);
1017 break;
1018 case 0x30: /* ACQ */
1019 trace_nvme_mmio_acqaddr(data);
1020 n->bar.acq = data;
1021 break;
1022 case 0x34: /* ACQ hi */
1023 n->bar.acq |= data << 32;
1024 trace_nvme_mmio_acqaddr_hi(data, n->bar.acq);
1025 break;
1026 case 0x38: /* CMBLOC */
1027 NVME_GUEST_ERR(nvme_ub_mmiowr_cmbloc_reserved,
1028 "invalid write to reserved CMBLOC"
1029 " when CMBSZ is zero, ignored");
1030 return;
1031 case 0x3C: /* CMBSZ */
1032 NVME_GUEST_ERR(nvme_ub_mmiowr_cmbsz_readonly,
1033 "invalid write to read only CMBSZ, ignored");
1034 return;
1035 default:
1036 NVME_GUEST_ERR(nvme_ub_mmiowr_invalid,
1037 "invalid MMIO write,"
1038 " offset=0x%"PRIx64", data=%"PRIx64"",
1039 offset, data);
1040 break;
1041 }
1042 }
1043
1044 static uint64_t nvme_mmio_read(void *opaque, hwaddr addr, unsigned size)
1045 {
1046 NvmeCtrl *n = (NvmeCtrl *)opaque;
1047 uint8_t *ptr = (uint8_t *)&n->bar;
1048 uint64_t val = 0;
1049
1050 if (unlikely(addr & (sizeof(uint32_t) - 1))) {
1051 NVME_GUEST_ERR(nvme_ub_mmiord_misaligned32,
1052 "MMIO read not 32-bit aligned,"
1053 " offset=0x%"PRIx64"", addr);
1054 /* should RAZ, fall through for now */
1055 } else if (unlikely(size < sizeof(uint32_t))) {
1056 NVME_GUEST_ERR(nvme_ub_mmiord_toosmall,
1057 "MMIO read smaller than 32-bits,"
1058 " offset=0x%"PRIx64"", addr);
1059 /* should RAZ, fall through for now */
1060 }
1061
1062 if (addr < sizeof(n->bar)) {
1063 memcpy(&val, ptr + addr, size);
1064 } else {
1065 NVME_GUEST_ERR(nvme_ub_mmiord_invalid_ofs,
1066 "MMIO read beyond last register,"
1067 " offset=0x%"PRIx64", returning 0", addr);
1068 }
1069
1070 return val;
1071 }
1072
1073 static void nvme_process_db(NvmeCtrl *n, hwaddr addr, int val)
1074 {
1075 uint32_t qid;
1076
1077 if (unlikely(addr & ((1 << 2) - 1))) {
1078 NVME_GUEST_ERR(nvme_ub_db_wr_misaligned,
1079 "doorbell write not 32-bit aligned,"
1080 " offset=0x%"PRIx64", ignoring", addr);
1081 return;
1082 }
1083
1084 if (((addr - 0x1000) >> 2) & 1) {
1085 /* Completion queue doorbell write */
1086
1087 uint16_t new_head = val & 0xffff;
1088 int start_sqs;
1089 NvmeCQueue *cq;
1090
1091 qid = (addr - (0x1000 + (1 << 2))) >> 3;
1092 if (unlikely(nvme_check_cqid(n, qid))) {
1093 NVME_GUEST_ERR(nvme_ub_db_wr_invalid_cq,
1094 "completion queue doorbell write"
1095 " for nonexistent queue,"
1096 " sqid=%"PRIu32", ignoring", qid);
1097 return;
1098 }
1099
1100 cq = n->cq[qid];
1101 if (unlikely(new_head >= cq->size)) {
1102 NVME_GUEST_ERR(nvme_ub_db_wr_invalid_cqhead,
1103 "completion queue doorbell write value"
1104 " beyond queue size, sqid=%"PRIu32","
1105 " new_head=%"PRIu16", ignoring",
1106 qid, new_head);
1107 return;
1108 }
1109
1110 start_sqs = nvme_cq_full(cq) ? 1 : 0;
1111 cq->head = new_head;
1112 if (start_sqs) {
1113 NvmeSQueue *sq;
1114 QTAILQ_FOREACH(sq, &cq->sq_list, entry) {
1115 timer_mod(sq->timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + 500);
1116 }
1117 timer_mod(cq->timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + 500);
1118 }
1119
1120 if (cq->tail == cq->head) {
1121 nvme_irq_deassert(n, cq);
1122 }
1123 } else {
1124 /* Submission queue doorbell write */
1125
1126 uint16_t new_tail = val & 0xffff;
1127 NvmeSQueue *sq;
1128
1129 qid = (addr - 0x1000) >> 3;
1130 if (unlikely(nvme_check_sqid(n, qid))) {
1131 NVME_GUEST_ERR(nvme_ub_db_wr_invalid_sq,
1132 "submission queue doorbell write"
1133 " for nonexistent queue,"
1134 " sqid=%"PRIu32", ignoring", qid);
1135 return;
1136 }
1137
1138 sq = n->sq[qid];
1139 if (unlikely(new_tail >= sq->size)) {
1140 NVME_GUEST_ERR(nvme_ub_db_wr_invalid_sqtail,
1141 "submission queue doorbell write value"
1142 " beyond queue size, sqid=%"PRIu32","
1143 " new_tail=%"PRIu16", ignoring",
1144 qid, new_tail);
1145 return;
1146 }
1147
1148 sq->tail = new_tail;
1149 timer_mod(sq->timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + 500);
1150 }
1151 }
1152
1153 static void nvme_mmio_write(void *opaque, hwaddr addr, uint64_t data,
1154 unsigned size)
1155 {
1156 NvmeCtrl *n = (NvmeCtrl *)opaque;
1157 if (addr < sizeof(n->bar)) {
1158 nvme_write_bar(n, addr, data, size);
1159 } else if (addr >= 0x1000) {
1160 nvme_process_db(n, addr, data);
1161 }
1162 }
1163
1164 static const MemoryRegionOps nvme_mmio_ops = {
1165 .read = nvme_mmio_read,
1166 .write = nvme_mmio_write,
1167 .endianness = DEVICE_LITTLE_ENDIAN,
1168 .impl = {
1169 .min_access_size = 2,
1170 .max_access_size = 8,
1171 },
1172 };
1173
1174 static void nvme_cmb_write(void *opaque, hwaddr addr, uint64_t data,
1175 unsigned size)
1176 {
1177 NvmeCtrl *n = (NvmeCtrl *)opaque;
1178 memcpy(&n->cmbuf[addr], &data, size);
1179 }
1180
1181 static uint64_t nvme_cmb_read(void *opaque, hwaddr addr, unsigned size)
1182 {
1183 uint64_t val;
1184 NvmeCtrl *n = (NvmeCtrl *)opaque;
1185
1186 memcpy(&val, &n->cmbuf[addr], size);
1187 return val;
1188 }
1189
1190 static const MemoryRegionOps nvme_cmb_ops = {
1191 .read = nvme_cmb_read,
1192 .write = nvme_cmb_write,
1193 .endianness = DEVICE_LITTLE_ENDIAN,
1194 .impl = {
1195 .min_access_size = 2,
1196 .max_access_size = 8,
1197 },
1198 };
1199
1200 static void nvme_realize(PCIDevice *pci_dev, Error **errp)
1201 {
1202 NvmeCtrl *n = NVME(pci_dev);
1203 NvmeIdCtrl *id = &n->id_ctrl;
1204
1205 int i;
1206 int64_t bs_size;
1207 uint8_t *pci_conf;
1208
1209 if (!n->conf.blk) {
1210 error_setg(errp, "drive property not set");
1211 return;
1212 }
1213
1214 bs_size = blk_getlength(n->conf.blk);
1215 if (bs_size < 0) {
1216 error_setg(errp, "could not get backing file size");
1217 return;
1218 }
1219
1220 if (!n->serial) {
1221 error_setg(errp, "serial property not set");
1222 return;
1223 }
1224 blkconf_blocksizes(&n->conf);
1225 if (!blkconf_apply_backend_options(&n->conf, blk_is_read_only(n->conf.blk),
1226 false, errp)) {
1227 return;
1228 }
1229
1230 pci_conf = pci_dev->config;
1231 pci_conf[PCI_INTERRUPT_PIN] = 1;
1232 pci_config_set_prog_interface(pci_dev->config, 0x2);
1233 pci_config_set_class(pci_dev->config, PCI_CLASS_STORAGE_EXPRESS);
1234 pcie_endpoint_cap_init(&n->parent_obj, 0x80);
1235
1236 n->num_namespaces = 1;
1237 n->reg_size = pow2ceil(0x1004 + 2 * (n->num_queues + 1) * 4);
1238 n->ns_size = bs_size / (uint64_t)n->num_namespaces;
1239
1240 n->namespaces = g_new0(NvmeNamespace, n->num_namespaces);
1241 n->sq = g_new0(NvmeSQueue *, n->num_queues);
1242 n->cq = g_new0(NvmeCQueue *, n->num_queues);
1243
1244 memory_region_init_io(&n->iomem, OBJECT(n), &nvme_mmio_ops, n,
1245 "nvme", n->reg_size);
1246 pci_register_bar(&n->parent_obj, 0,
1247 PCI_BASE_ADDRESS_SPACE_MEMORY | PCI_BASE_ADDRESS_MEM_TYPE_64,
1248 &n->iomem);
1249 msix_init_exclusive_bar(&n->parent_obj, n->num_queues, 4, NULL);
1250
1251 id->vid = cpu_to_le16(pci_get_word(pci_conf + PCI_VENDOR_ID));
1252 id->ssvid = cpu_to_le16(pci_get_word(pci_conf + PCI_SUBSYSTEM_VENDOR_ID));
1253 strpadcpy((char *)id->mn, sizeof(id->mn), "QEMU NVMe Ctrl", ' ');
1254 strpadcpy((char *)id->fr, sizeof(id->fr), "1.0", ' ');
1255 strpadcpy((char *)id->sn, sizeof(id->sn), n->serial, ' ');
1256 id->rab = 6;
1257 id->ieee[0] = 0x00;
1258 id->ieee[1] = 0x02;
1259 id->ieee[2] = 0xb3;
1260 id->oacs = cpu_to_le16(0);
1261 id->frmw = 7 << 1;
1262 id->lpa = 1 << 0;
1263 id->sqes = (0x6 << 4) | 0x6;
1264 id->cqes = (0x4 << 4) | 0x4;
1265 id->nn = cpu_to_le32(n->num_namespaces);
1266 id->oncs = cpu_to_le16(NVME_ONCS_WRITE_ZEROS);
1267 id->psd[0].mp = cpu_to_le16(0x9c4);
1268 id->psd[0].enlat = cpu_to_le32(0x10);
1269 id->psd[0].exlat = cpu_to_le32(0x4);
1270 if (blk_enable_write_cache(n->conf.blk)) {
1271 id->vwc = 1;
1272 }
1273
1274 n->bar.cap = 0;
1275 NVME_CAP_SET_MQES(n->bar.cap, 0x7ff);
1276 NVME_CAP_SET_CQR(n->bar.cap, 1);
1277 NVME_CAP_SET_AMS(n->bar.cap, 1);
1278 NVME_CAP_SET_TO(n->bar.cap, 0xf);
1279 NVME_CAP_SET_CSS(n->bar.cap, 1);
1280 NVME_CAP_SET_MPSMAX(n->bar.cap, 4);
1281
1282 n->bar.vs = 0x00010200;
1283 n->bar.intmc = n->bar.intms = 0;
1284
1285 if (n->cmb_size_mb) {
1286
1287 NVME_CMBLOC_SET_BIR(n->bar.cmbloc, 2);
1288 NVME_CMBLOC_SET_OFST(n->bar.cmbloc, 0);
1289
1290 NVME_CMBSZ_SET_SQS(n->bar.cmbsz, 1);
1291 NVME_CMBSZ_SET_CQS(n->bar.cmbsz, 0);
1292 NVME_CMBSZ_SET_LISTS(n->bar.cmbsz, 0);
1293 NVME_CMBSZ_SET_RDS(n->bar.cmbsz, 1);
1294 NVME_CMBSZ_SET_WDS(n->bar.cmbsz, 1);
1295 NVME_CMBSZ_SET_SZU(n->bar.cmbsz, 2); /* MBs */
1296 NVME_CMBSZ_SET_SZ(n->bar.cmbsz, n->cmb_size_mb);
1297
1298 n->cmbloc = n->bar.cmbloc;
1299 n->cmbsz = n->bar.cmbsz;
1300
1301 n->cmbuf = g_malloc0(NVME_CMBSZ_GETSIZE(n->bar.cmbsz));
1302 memory_region_init_io(&n->ctrl_mem, OBJECT(n), &nvme_cmb_ops, n,
1303 "nvme-cmb", NVME_CMBSZ_GETSIZE(n->bar.cmbsz));
1304 pci_register_bar(&n->parent_obj, NVME_CMBLOC_BIR(n->bar.cmbloc),
1305 PCI_BASE_ADDRESS_SPACE_MEMORY | PCI_BASE_ADDRESS_MEM_TYPE_64 |
1306 PCI_BASE_ADDRESS_MEM_PREFETCH, &n->ctrl_mem);
1307
1308 }
1309
1310 for (i = 0; i < n->num_namespaces; i++) {
1311 NvmeNamespace *ns = &n->namespaces[i];
1312 NvmeIdNs *id_ns = &ns->id_ns;
1313 id_ns->nsfeat = 0;
1314 id_ns->nlbaf = 0;
1315 id_ns->flbas = 0;
1316 id_ns->mc = 0;
1317 id_ns->dpc = 0;
1318 id_ns->dps = 0;
1319 id_ns->lbaf[0].ds = BDRV_SECTOR_BITS;
1320 id_ns->ncap = id_ns->nuse = id_ns->nsze =
1321 cpu_to_le64(n->ns_size >>
1322 id_ns->lbaf[NVME_ID_NS_FLBAS_INDEX(ns->id_ns.flbas)].ds);
1323 }
1324 }
1325
1326 static void nvme_exit(PCIDevice *pci_dev)
1327 {
1328 NvmeCtrl *n = NVME(pci_dev);
1329
1330 nvme_clear_ctrl(n);
1331 g_free(n->namespaces);
1332 g_free(n->cq);
1333 g_free(n->sq);
1334 if (n->cmbsz) {
1335 memory_region_unref(&n->ctrl_mem);
1336 }
1337
1338 msix_uninit_exclusive_bar(pci_dev);
1339 }
1340
1341 static Property nvme_props[] = {
1342 DEFINE_BLOCK_PROPERTIES(NvmeCtrl, conf),
1343 DEFINE_PROP_STRING("serial", NvmeCtrl, serial),
1344 DEFINE_PROP_UINT32("cmb_size_mb", NvmeCtrl, cmb_size_mb, 0),
1345 DEFINE_PROP_UINT32("num_queues", NvmeCtrl, num_queues, 64),
1346 DEFINE_PROP_END_OF_LIST(),
1347 };
1348
1349 static const VMStateDescription nvme_vmstate = {
1350 .name = "nvme",
1351 .unmigratable = 1,
1352 };
1353
1354 static void nvme_class_init(ObjectClass *oc, void *data)
1355 {
1356 DeviceClass *dc = DEVICE_CLASS(oc);
1357 PCIDeviceClass *pc = PCI_DEVICE_CLASS(oc);
1358
1359 pc->realize = nvme_realize;
1360 pc->exit = nvme_exit;
1361 pc->class_id = PCI_CLASS_STORAGE_EXPRESS;
1362 pc->vendor_id = PCI_VENDOR_ID_INTEL;
1363 pc->device_id = 0x5845;
1364 pc->revision = 2;
1365
1366 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
1367 dc->desc = "Non-Volatile Memory Express";
1368 dc->props = nvme_props;
1369 dc->vmsd = &nvme_vmstate;
1370 }
1371
1372 static void nvme_instance_init(Object *obj)
1373 {
1374 NvmeCtrl *s = NVME(obj);
1375
1376 device_add_bootindex_property(obj, &s->conf.bootindex,
1377 "bootindex", "/namespace@1,0",
1378 DEVICE(obj), &error_abort);
1379 }
1380
1381 static const TypeInfo nvme_info = {
1382 .name = "nvme",
1383 .parent = TYPE_PCI_DEVICE,
1384 .instance_size = sizeof(NvmeCtrl),
1385 .class_init = nvme_class_init,
1386 .instance_init = nvme_instance_init,
1387 .interfaces = (InterfaceInfo[]) {
1388 { INTERFACE_PCIE_DEVICE },
1389 { }
1390 },
1391 };
1392
1393 static void nvme_register_types(void)
1394 {
1395 type_register_static(&nvme_info);
1396 }
1397
1398 type_init(nvme_register_types)
armbru's QEMU hackery