hw/arm/mps2.c

   1 /*
   2  * ARM V2M MPS2 board emulation.
   3  *
   4  * Copyright (c) 2017 Linaro Limited
   5  * Written by Peter Maydell
   6  *
   7  *  This program is free software; you can redistribute it and/or modify
   8  *  it under the terms of the GNU General Public License version 2 or
   9  *  (at your option) any later version.
  10  */
  11
  12 /* The MPS2 and MPS2+ dev boards are FPGA based (the 2+ has a bigger
  13  * FPGA but is otherwise the same as the 2). Since the CPU itself
  14  * and most of the devices are in the FPGA, the details of the board
  15  * as seen by the guest depend significantly on the FPGA image.
  16  * We model the following FPGA images:
  17  *  "mps2-an385" -- Cortex-M3 as documented in ARM Application Note AN385
  18  *  "mps2-an511" -- Cortex-M3 'DesignStart' as documented in AN511
  19  *
  20  * Links to the TRM for the board itself and to the various Application
  21  * Notes which document the FPGA images can be found here:
  22  *   https://developer.arm.com/products/system-design/development-boards/cortex-m-prototyping-system
  23  */
  24
  25 #include "qemu/osdep.h"
  26 #include "qemu/units.h"
  27 #include "qemu/cutils.h"
  28 #include "qapi/error.h"
  29 #include "qemu/error-report.h"
  30 #include "hw/arm/boot.h"
  31 #include "hw/arm/armv7m.h"
  32 #include "hw/or-irq.h"
  33 #include "hw/boards.h"
  34 #include "exec/address-spaces.h"
  35 #include "sysemu/sysemu.h"
  36 #include "hw/misc/unimp.h"
  37 #include "hw/char/cmsdk-apb-uart.h"
  38 #include "hw/timer/cmsdk-apb-timer.h"
  39 #include "hw/timer/cmsdk-apb-dualtimer.h"
  40 #include "hw/misc/mps2-scc.h"
  41 #include "hw/misc/mps2-fpgaio.h"
  42 #include "hw/ssi/pl022.h"
  43 #include "hw/i2c/arm_sbcon_i2c.h"
  44 #include "hw/net/lan9118.h"
  45 #include "net/net.h"
  46 #include "hw/watchdog/cmsdk-apb-watchdog.h"
  47
  48 typedef enum MPS2FPGAType {
  49     FPGA_AN385,
  50     FPGA_AN511,
  51 } MPS2FPGAType;
  52
  53 typedef struct {
  54     MachineClass parent;
  55     MPS2FPGAType fpga_type;
  56     uint32_t scc_id;
  57 } MPS2MachineClass;
  58
  59 typedef struct {
  60     MachineState parent;
  61
  62     ARMv7MState armv7m;
  63     MemoryRegion ssram1;
  64     MemoryRegion ssram1_m;
  65     MemoryRegion ssram23;
  66     MemoryRegion ssram23_m;
  67     MemoryRegion blockram;
  68     MemoryRegion blockram_m1;
  69     MemoryRegion blockram_m2;
  70     MemoryRegion blockram_m3;
  71     MemoryRegion sram;
  72     /* FPGA APB subsystem */
  73     MPS2SCC scc;
  74     MPS2FPGAIO fpgaio;
  75     /* CMSDK APB subsystem */
  76     CMSDKAPBDualTimer dualtimer;
  77     CMSDKAPBWatchdog watchdog;
  78 } MPS2MachineState;
  79
  80 #define TYPE_MPS2_MACHINE "mps2"
  81 #define TYPE_MPS2_AN385_MACHINE MACHINE_TYPE_NAME("mps2-an385")
  82 #define TYPE_MPS2_AN511_MACHINE MACHINE_TYPE_NAME("mps2-an511")
  83
  84 #define MPS2_MACHINE(obj)                                       \
  85     OBJECT_CHECK(MPS2MachineState, obj, TYPE_MPS2_MACHINE)
  86 #define MPS2_MACHINE_GET_CLASS(obj) \
  87     OBJECT_GET_CLASS(MPS2MachineClass, obj, TYPE_MPS2_MACHINE)
  88 #define MPS2_MACHINE_CLASS(klass) \
  89     OBJECT_CLASS_CHECK(MPS2MachineClass, klass, TYPE_MPS2_MACHINE)
  90
  91 /* Main SYSCLK frequency in Hz */
  92 #define SYSCLK_FRQ 25000000
  93
  94 /* Initialize the auxiliary RAM region @mr and map it into
  95  * the memory map at @base.
  96  */
  97 static void make_ram(MemoryRegion *mr, const char *name,
  98                      hwaddr base, hwaddr size)
  99 {
 100     memory_region_init_ram(mr, NULL, name, size, &error_fatal);
 101     memory_region_add_subregion(get_system_memory(), base, mr);
 102 }
 103
 104 /* Create an alias of an entire original MemoryRegion @orig
 105  * located at @base in the memory map.
 106  */
 107 static void make_ram_alias(MemoryRegion *mr, const char *name,
 108                            MemoryRegion *orig, hwaddr base)
 109 {
 110     memory_region_init_alias(mr, NULL, name, orig, 0,
 111                              memory_region_size(orig));
 112     memory_region_add_subregion(get_system_memory(), base, mr);
 113 }
 114
 115 static void mps2_common_init(MachineState *machine)
 116 {
 117     MPS2MachineState *mms = MPS2_MACHINE(machine);
 118     MPS2MachineClass *mmc = MPS2_MACHINE_GET_CLASS(machine);
 119     MemoryRegion *system_memory = get_system_memory();
 120     MachineClass *mc = MACHINE_GET_CLASS(machine);
 121     DeviceState *armv7m, *sccdev;
 122     int i;
 123
 124     if (strcmp(machine->cpu_type, mc->default_cpu_type) != 0) {
 125         error_report("This board can only be used with CPU %s",
 126                      mc->default_cpu_type);
 127         exit(1);
 128     }
 129
 130     if (machine->ram_size != mc->default_ram_size) {
 131         char *sz = size_to_str(mc->default_ram_size);
 132         error_report("Invalid RAM size, should be %s", sz);
 133         g_free(sz);
 134         exit(EXIT_FAILURE);
 135     }
 136
 137     /* The FPGA images have an odd combination of different RAMs,
 138      * because in hardware they are different implementations and
 139      * connected to different buses, giving varying performance/size
 140      * tradeoffs. For QEMU they're all just RAM, though. We arbitrarily
 141      * call the 16MB our "system memory", as it's the largest lump.
 142      *
 143      * Common to both boards:
 144      *  0x21000000..0x21ffffff : PSRAM (16MB)
 145      * AN385 only:
 146      *  0x00000000 .. 0x003fffff : ZBT SSRAM1
 147      *  0x00400000 .. 0x007fffff : mirror of ZBT SSRAM1
 148      *  0x20000000 .. 0x203fffff : ZBT SSRAM 2&3
 149      *  0x20400000 .. 0x207fffff : mirror of ZBT SSRAM 2&3
 150      *  0x01000000 .. 0x01003fff : block RAM (16K)
 151      *  0x01004000 .. 0x01007fff : mirror of above
 152      *  0x01008000 .. 0x0100bfff : mirror of above
 153      *  0x0100c000 .. 0x0100ffff : mirror of above
 154      * AN511 only:
 155      *  0x00000000 .. 0x0003ffff : FPGA block RAM
 156      *  0x00400000 .. 0x007fffff : ZBT SSRAM1
 157      *  0x20000000 .. 0x2001ffff : SRAM
 158      *  0x20400000 .. 0x207fffff : ZBT SSRAM 2&3
 159      *
 160      * The AN385 has a feature where the lowest 16K can be mapped
 161      * either to the bottom of the ZBT SSRAM1 or to the block RAM.
 162      * This is of no use for QEMU so we don't implement it (as if
 163      * zbt_boot_ctrl is always zero).
 164      */
 165     memory_region_add_subregion(system_memory, 0x21000000, machine->ram);
 166
 167     switch (mmc->fpga_type) {
 168     case FPGA_AN385:
 169         make_ram(&mms->ssram1, "mps.ssram1", 0x0, 0x400000);
 170         make_ram_alias(&mms->ssram1_m, "mps.ssram1_m", &mms->ssram1, 0x400000);
 171         make_ram(&mms->ssram23, "mps.ssram23", 0x20000000, 0x400000);
 172         make_ram_alias(&mms->ssram23_m, "mps.ssram23_m",
 173                        &mms->ssram23, 0x20400000);
 174         make_ram(&mms->blockram, "mps.blockram", 0x01000000, 0x4000);
 175         make_ram_alias(&mms->blockram_m1, "mps.blockram_m1",
 176                        &mms->blockram, 0x01004000);
 177         make_ram_alias(&mms->blockram_m2, "mps.blockram_m2",
 178                        &mms->blockram, 0x01008000);
 179         make_ram_alias(&mms->blockram_m3, "mps.blockram_m3",
 180                        &mms->blockram, 0x0100c000);
 181         break;
 182     case FPGA_AN511:
 183         make_ram(&mms->blockram, "mps.blockram", 0x0, 0x40000);
 184         make_ram(&mms->ssram1, "mps.ssram1", 0x00400000, 0x00800000);
 185         make_ram(&mms->sram, "mps.sram", 0x20000000, 0x20000);
 186         make_ram(&mms->ssram23, "mps.ssram23", 0x20400000, 0x400000);
 187         break;
 188     default:
 189         g_assert_not_reached();
 190     }
 191
 192     object_initialize_child(OBJECT(mms), "armv7m", &mms->armv7m, TYPE_ARMV7M);
 193     armv7m = DEVICE(&mms->armv7m);
 194     switch (mmc->fpga_type) {
 195     case FPGA_AN385:
 196         qdev_prop_set_uint32(armv7m, "num-irq", 32);
 197         break;
 198     case FPGA_AN511:
 199         qdev_prop_set_uint32(armv7m, "num-irq", 64);
 200         break;
 201     default:
 202         g_assert_not_reached();
 203     }
 204     qdev_prop_set_string(armv7m, "cpu-type", machine->cpu_type);
 205     qdev_prop_set_bit(armv7m, "enable-bitband", true);
 206     object_property_set_link(OBJECT(&mms->armv7m), "memory",
 207                              OBJECT(system_memory), &error_abort);
 208     sysbus_realize(SYS_BUS_DEVICE(&mms->armv7m), &error_fatal);
 209
 210     create_unimplemented_device("zbtsmram mirror", 0x00400000, 0x00400000);
 211     create_unimplemented_device("RESERVED 1", 0x00800000, 0x00800000);
 212     create_unimplemented_device("Block RAM", 0x01000000, 0x00010000);
 213     create_unimplemented_device("RESERVED 2", 0x01010000, 0x1EFF0000);
 214     create_unimplemented_device("RESERVED 3", 0x20800000, 0x00800000);
 215     create_unimplemented_device("PSRAM", 0x21000000, 0x01000000);
 216     /* These three ranges all cover multiple devices; we may implement
 217      * some of them below (in which case the real device takes precedence
 218      * over the unimplemented-region mapping).
 219      */
 220     create_unimplemented_device("CMSDK APB peripheral region @0x40000000",
 221                                 0x40000000, 0x00010000);
 222     create_unimplemented_device("CMSDK AHB peripheral region @0x40010000",
 223                                 0x40010000, 0x00010000);
 224     create_unimplemented_device("Extra peripheral region @0x40020000",
 225                                 0x40020000, 0x00010000);
 226
 227     create_unimplemented_device("RESERVED 4", 0x40030000, 0x001D0000);
 228     create_unimplemented_device("VGA", 0x41000000, 0x0200000);
 229
 230     switch (mmc->fpga_type) {
 231     case FPGA_AN385:
 232     {
 233         /* The overflow IRQs for UARTs 0, 1 and 2 are ORed together.
 234          * Overflow for UARTs 4 and 5 doesn't trigger any interrupt.
 235          */
 236         Object *orgate;
 237         DeviceState *orgate_dev;
 238
 239         orgate = object_new(TYPE_OR_IRQ);
 240         object_property_set_int(orgate, "num-lines", 6, &error_fatal);
 241         qdev_realize(DEVICE(orgate), NULL, &error_fatal);
 242         orgate_dev = DEVICE(orgate);
 243         qdev_connect_gpio_out(orgate_dev, 0, qdev_get_gpio_in(armv7m, 12));
 244
 245         for (i = 0; i < 5; i++) {
 246             static const hwaddr uartbase[] = {0x40004000, 0x40005000,
 247                                               0x40006000, 0x40007000,
 248                                               0x40009000};
 249             /* RX irq number; TX irq is always one greater */
 250             static const int uartirq[] = {0, 2, 4, 18, 20};
 251             qemu_irq txovrint = NULL, rxovrint = NULL;
 252
 253             if (i < 3) {
 254                 txovrint = qdev_get_gpio_in(orgate_dev, i * 2);
 255                 rxovrint = qdev_get_gpio_in(orgate_dev, i * 2 + 1);
 256             }
 257
 258             cmsdk_apb_uart_create(uartbase[i],
 259                                   qdev_get_gpio_in(armv7m, uartirq[i] + 1),
 260                                   qdev_get_gpio_in(armv7m, uartirq[i]),
 261                                   txovrint, rxovrint,
 262                                   NULL,
 263                                   serial_hd(i), SYSCLK_FRQ);
 264         }
 265         break;
 266     }
 267     case FPGA_AN511:
 268     {
 269         /* The overflow IRQs for all UARTs are ORed together.
 270          * Tx and Rx IRQs for each UART are ORed together.
 271          */
 272         Object *orgate;
 273         DeviceState *orgate_dev;
 274
 275         orgate = object_new(TYPE_OR_IRQ);
 276         object_property_set_int(orgate, "num-lines", 10, &error_fatal);
 277         qdev_realize(DEVICE(orgate), NULL, &error_fatal);
 278         orgate_dev = DEVICE(orgate);
 279         qdev_connect_gpio_out(orgate_dev, 0, qdev_get_gpio_in(armv7m, 12));
 280
 281         for (i = 0; i < 5; i++) {
 282             /* system irq numbers for the combined tx/rx for each UART */
 283             static const int uart_txrx_irqno[] = {0, 2, 45, 46, 56};
 284             static const hwaddr uartbase[] = {0x40004000, 0x40005000,
 285                                               0x4002c000, 0x4002d000,
 286                                               0x4002e000};
 287             Object *txrx_orgate;
 288             DeviceState *txrx_orgate_dev;
 289
 290             txrx_orgate = object_new(TYPE_OR_IRQ);
 291             object_property_set_int(txrx_orgate, "num-lines", 2, &error_fatal);
 292             qdev_realize(DEVICE(txrx_orgate), NULL, &error_fatal);
 293             txrx_orgate_dev = DEVICE(txrx_orgate);
 294             qdev_connect_gpio_out(txrx_orgate_dev, 0,
 295                                   qdev_get_gpio_in(armv7m, uart_txrx_irqno[i]));
 296             cmsdk_apb_uart_create(uartbase[i],
 297                                   qdev_get_gpio_in(txrx_orgate_dev, 0),
 298                                   qdev_get_gpio_in(txrx_orgate_dev, 1),
 299                                   qdev_get_gpio_in(orgate_dev, i * 2),
 300                                   qdev_get_gpio_in(orgate_dev, i * 2 + 1),
 301                                   NULL,
 302                                   serial_hd(i), SYSCLK_FRQ);
 303         }
 304         break;
 305     }
 306     default:
 307         g_assert_not_reached();
 308     }
 309     for (i = 0; i < 4; i++) {
 310         static const hwaddr gpiobase[] = {0x40010000, 0x40011000,
 311                                           0x40012000, 0x40013000};
 312         create_unimplemented_device("cmsdk-ahb-gpio", gpiobase[i], 0x1000);
 313     }
 314
 315     /* CMSDK APB subsystem */
 316     cmsdk_apb_timer_create(0x40000000, qdev_get_gpio_in(armv7m, 8), SYSCLK_FRQ);
 317     cmsdk_apb_timer_create(0x40001000, qdev_get_gpio_in(armv7m, 9), SYSCLK_FRQ);
 318     object_initialize_child(OBJECT(mms), "dualtimer", &mms->dualtimer,
 319                             TYPE_CMSDK_APB_DUALTIMER);
 320     qdev_prop_set_uint32(DEVICE(&mms->dualtimer), "pclk-frq", SYSCLK_FRQ);
 321     sysbus_realize(SYS_BUS_DEVICE(&mms->dualtimer), &error_fatal);
 322     sysbus_connect_irq(SYS_BUS_DEVICE(&mms->dualtimer), 0,
 323                        qdev_get_gpio_in(armv7m, 10));
 324     sysbus_mmio_map(SYS_BUS_DEVICE(&mms->dualtimer), 0, 0x40002000);
 325     object_initialize_child(OBJECT(mms), "watchdog", &mms->watchdog,
 326                             TYPE_CMSDK_APB_WATCHDOG);
 327     qdev_prop_set_uint32(DEVICE(&mms->watchdog), "wdogclk-frq", SYSCLK_FRQ);
 328     sysbus_realize(SYS_BUS_DEVICE(&mms->watchdog), &error_fatal);
 329     sysbus_connect_irq(SYS_BUS_DEVICE(&mms->watchdog), 0,
 330                        qdev_get_gpio_in_named(armv7m, "NMI", 0));
 331     sysbus_mmio_map(SYS_BUS_DEVICE(&mms->watchdog), 0, 0x40008000);
 332
 333     /* FPGA APB subsystem */
 334     object_initialize_child(OBJECT(mms), "scc", &mms->scc, TYPE_MPS2_SCC);
 335     sccdev = DEVICE(&mms->scc);
 336     qdev_prop_set_uint32(sccdev, "scc-cfg4", 0x2);
 337     qdev_prop_set_uint32(sccdev, "scc-aid", 0x00200008);
 338     qdev_prop_set_uint32(sccdev, "scc-id", mmc->scc_id);
 339     sysbus_realize(SYS_BUS_DEVICE(&mms->scc), &error_fatal);
 340     sysbus_mmio_map(SYS_BUS_DEVICE(sccdev), 0, 0x4002f000);
 341     object_initialize_child(OBJECT(mms), "fpgaio",
 342                             &mms->fpgaio, TYPE_MPS2_FPGAIO);
 343     qdev_prop_set_uint32(DEVICE(&mms->fpgaio), "prescale-clk", 25000000);
 344     sysbus_realize(SYS_BUS_DEVICE(&mms->fpgaio), &error_fatal);
 345     sysbus_mmio_map(SYS_BUS_DEVICE(&mms->fpgaio), 0, 0x40028000);
 346     sysbus_create_simple(TYPE_PL022, 0x40025000,        /* External ADC */
 347                          qdev_get_gpio_in(armv7m, 22));
 348     for (i = 0; i < 2; i++) {
 349         static const int spi_irqno[] = {11, 24};
 350         static const hwaddr spibase[] = {0x40020000,    /* APB */
 351                                          0x40021000,    /* LCD */
 352                                          0x40026000,    /* Shield0 */
 353                                          0x40027000};   /* Shield1 */
 354         DeviceState *orgate_dev;
 355         Object *orgate;
 356         int j;
 357
 358         orgate = object_new(TYPE_OR_IRQ);
 359         object_property_set_int(orgate, "num-lines", 2, &error_fatal);
 360         orgate_dev = DEVICE(orgate);
 361         qdev_realize(orgate_dev, NULL, &error_fatal);
 362         qdev_connect_gpio_out(orgate_dev, 0,
 363                               qdev_get_gpio_in(armv7m, spi_irqno[i]));
 364         for (j = 0; j < 2; j++) {
 365             sysbus_create_simple(TYPE_PL022, spibase[2 * i + j],
 366                                  qdev_get_gpio_in(orgate_dev, j));
 367         }
 368     }
 369     for (i = 0; i < 4; i++) {
 370         static const hwaddr i2cbase[] = {0x40022000,    /* Touch */
 371                                          0x40023000,    /* Audio */
 372                                          0x40029000,    /* Shield0 */
 373                                          0x4002a000};   /* Shield1 */
 374         sysbus_create_simple(TYPE_ARM_SBCON_I2C, i2cbase[i], NULL);
 375     }
 376     create_unimplemented_device("i2s", 0x40024000, 0x400);
 377
 378     /* In hardware this is a LAN9220; the LAN9118 is software compatible
 379      * except that it doesn't support the checksum-offload feature.
 380      */
 381     lan9118_init(&nd_table[0], 0x40200000,
 382                  qdev_get_gpio_in(armv7m,
 383                                   mmc->fpga_type == FPGA_AN385 ? 13 : 47));
 384
 385     system_clock_scale = NANOSECONDS_PER_SECOND / SYSCLK_FRQ;
 386
 387     armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename,
 388                        0x400000);
 389 }
 390
 391 static void mps2_class_init(ObjectClass *oc, void *data)
 392 {
 393     MachineClass *mc = MACHINE_CLASS(oc);
 394
 395     mc->init = mps2_common_init;
 396     mc->max_cpus = 1;
 397     mc->default_ram_size = 16 * MiB;
 398     mc->default_ram_id = "mps.ram";
 399 }
 400
 401 static void mps2_an385_class_init(ObjectClass *oc, void *data)
 402 {
 403     MachineClass *mc = MACHINE_CLASS(oc);
 404     MPS2MachineClass *mmc = MPS2_MACHINE_CLASS(oc);
 405
 406     mc->desc = "ARM MPS2 with AN385 FPGA image for Cortex-M3";
 407     mmc->fpga_type = FPGA_AN385;
 408     mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m3");
 409     mmc->scc_id = 0x41043850;
 410 }
 411
 412 static void mps2_an511_class_init(ObjectClass *oc, void *data)
 413 {
 414     MachineClass *mc = MACHINE_CLASS(oc);
 415     MPS2MachineClass *mmc = MPS2_MACHINE_CLASS(oc);
 416
 417     mc->desc = "ARM MPS2 with AN511 DesignStart FPGA image for Cortex-M3";
 418     mmc->fpga_type = FPGA_AN511;
 419     mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m3");
 420     mmc->scc_id = 0x41045110;
 421 }
 422
 423 static const TypeInfo mps2_info = {
 424     .name = TYPE_MPS2_MACHINE,
 425     .parent = TYPE_MACHINE,
 426     .abstract = true,
 427     .instance_size = sizeof(MPS2MachineState),
 428     .class_size = sizeof(MPS2MachineClass),
 429     .class_init = mps2_class_init,
 430 };
 431
 432 static const TypeInfo mps2_an385_info = {
 433     .name = TYPE_MPS2_AN385_MACHINE,
 434     .parent = TYPE_MPS2_MACHINE,
 435     .class_init = mps2_an385_class_init,
 436 };
 437
 438 static const TypeInfo mps2_an511_info = {
 439     .name = TYPE_MPS2_AN511_MACHINE,
 440     .parent = TYPE_MPS2_MACHINE,
 441     .class_init = mps2_an511_class_init,
 442 };
 443
 444 static void mps2_machine_init(void)
 445 {
 446     type_register_static(&mps2_info);
 447     type_register_static(&mps2_an385_info);
 448     type_register_static(&mps2_an511_info);
 449 }
 450
 451 type_init(mps2_machine_init);