hw/misc/macio/gpio.c

   1 /*
   2  * PowerMac NewWorld MacIO GPIO emulation
   3  *
   4  * Copyright (c) 2016 Benjamin Herrenschmidt
   5  * Copyright (c) 2018 Mark Cave-Ayland
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a copy
   8  * of this software and associated documentation files (the "Software"), to deal
   9  * in the Software without restriction, including without limitation the rights
  10  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  11  * copies of the Software, and to permit persons to whom the Software is
  12  * furnished to do so, subject to the following conditions:
  13  *
  14  * The above copyright notice and this permission notice shall be included in
  15  * all copies or substantial portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  23  * THE SOFTWARE.
  24  */
  25
  26 #include "qemu/osdep.h"
  27 #include "hw/ppc/mac.h"
  28 #include "hw/qdev-properties.h"
  29 #include "migration/vmstate.h"
  30 #include "hw/misc/macio/macio.h"
  31 #include "hw/misc/macio/gpio.h"
  32 #include "hw/nmi.h"
  33 #include "qemu/log.h"
  34 #include "qemu/module.h"
  35 #include "trace.h"
  36
  37
  38 void macio_set_gpio(MacIOGPIOState *s, uint32_t gpio, bool state)
  39 {
  40     uint8_t new_reg;
  41
  42     trace_macio_set_gpio(gpio, state);
  43
  44     if (s->gpio_regs[gpio] & 4) {
  45         qemu_log_mask(LOG_GUEST_ERROR,
  46                       "GPIO: Setting GPIO %d while it's an output\n", gpio);
  47     }
  48
  49     new_reg = s->gpio_regs[gpio] & ~2;
  50     if (state) {
  51         new_reg |= 2;
  52     }
  53
  54     if (new_reg == s->gpio_regs[gpio]) {
  55         return;
  56     }
  57
  58     s->gpio_regs[gpio] = new_reg;
  59
  60     /* This is will work until we fix the binding between MacIO and
  61      * the MPIC properly so we can route all GPIOs and avoid going
  62      * via the top level platform code.
  63      *
  64      * Note that we probably need to get access to the MPIC config to
  65      * decode polarity since qemu always use "raise" regardless.
  66      *
  67      * For now, we hard wire known GPIOs
  68      */
  69
  70     switch (gpio) {
  71     case 1:
  72         /* Level low */
  73         if (!state) {
  74             trace_macio_gpio_irq_assert(gpio);
  75             qemu_irq_raise(s->gpio_extirqs[gpio]);
  76         } else {
  77             trace_macio_gpio_irq_deassert(gpio);
  78             qemu_irq_lower(s->gpio_extirqs[gpio]);
  79         }
  80         break;
  81
  82     case 9:
  83         /* Edge, triggered by NMI below */
  84         if (state) {
  85             trace_macio_gpio_irq_assert(gpio);
  86             qemu_irq_raise(s->gpio_extirqs[gpio]);
  87         } else {
  88             trace_macio_gpio_irq_deassert(gpio);
  89             qemu_irq_lower(s->gpio_extirqs[gpio]);
  90         }
  91         break;
  92
  93     default:
  94         qemu_log_mask(LOG_UNIMP, "GPIO: setting unimplemented GPIO %d", gpio);
  95     }
  96 }
  97
  98 static void macio_gpio_write(void *opaque, hwaddr addr, uint64_t value,
  99                              unsigned size)
 100 {
 101     MacIOGPIOState *s = opaque;
 102     uint8_t ibit;
 103
 104     trace_macio_gpio_write(addr, value);
 105
 106     /* Levels regs are read-only */
 107     if (addr < 8) {
 108         return;
 109     }
 110
 111     addr -= 8;
 112     if (addr < 36) {
 113         value &= ~2;
 114
 115         if (value & 4) {
 116             ibit = (value & 1) << 1;
 117         } else {
 118             ibit = s->gpio_regs[addr] & 2;
 119         }
 120
 121         s->gpio_regs[addr] = value | ibit;
 122     }
 123 }
 124
 125 static uint64_t macio_gpio_read(void *opaque, hwaddr addr, unsigned size)
 126 {
 127     MacIOGPIOState *s = opaque;
 128     uint64_t val = 0;
 129
 130     /* Levels regs */
 131     if (addr < 8) {
 132         val = s->gpio_levels[addr];
 133     } else {
 134         addr -= 8;
 135
 136         if (addr < 36) {
 137             val = s->gpio_regs[addr];
 138         }
 139     }
 140
 141     trace_macio_gpio_write(addr, val);
 142     return val;
 143 }
 144
 145 static const MemoryRegionOps macio_gpio_ops = {
 146     .read = macio_gpio_read,
 147     .write = macio_gpio_write,
 148     .endianness = DEVICE_LITTLE_ENDIAN,
 149     .impl = {
 150         .min_access_size = 1,
 151         .max_access_size = 1,
 152     },
 153 };
 154
 155 static void macio_gpio_realize(DeviceState *dev, Error **errp)
 156 {
 157     MacIOGPIOState *s = MACIO_GPIO(dev);
 158
 159     s->gpio_extirqs[1] = qdev_get_gpio_in(DEVICE(s->pic),
 160                                           NEWWORLD_EXTING_GPIO1);
 161     s->gpio_extirqs[9] = qdev_get_gpio_in(DEVICE(s->pic),
 162                                           NEWWORLD_EXTING_GPIO9);
 163 }
 164
 165 static void macio_gpio_init(Object *obj)
 166 {
 167     SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
 168     MacIOGPIOState *s = MACIO_GPIO(obj);
 169
 170     object_property_add_link(obj, "pic", TYPE_OPENPIC,
 171                              (Object **) &s->pic,
 172                              qdev_prop_allow_set_link_before_realize,
 173                              0);
 174
 175     memory_region_init_io(&s->gpiomem, OBJECT(s), &macio_gpio_ops, obj,
 176                           "gpio", 0x30);
 177     sysbus_init_mmio(sbd, &s->gpiomem);
 178 }
 179
 180 static const VMStateDescription vmstate_macio_gpio = {
 181     .name = "macio_gpio",
 182     .version_id = 0,
 183     .minimum_version_id = 0,
 184     .fields = (VMStateField[]) {
 185         VMSTATE_UINT8_ARRAY(gpio_levels, MacIOGPIOState, 8),
 186         VMSTATE_UINT8_ARRAY(gpio_regs, MacIOGPIOState, 36),
 187         VMSTATE_END_OF_LIST()
 188     }
 189 };
 190
 191 static void macio_gpio_reset(DeviceState *dev)
 192 {
 193     MacIOGPIOState *s = MACIO_GPIO(dev);
 194
 195     /* GPIO 1 is up by default */
 196     macio_set_gpio(s, 1, true);
 197 }
 198
 199 static void macio_gpio_nmi(NMIState *n, int cpu_index, Error **errp)
 200 {
 201     macio_set_gpio(MACIO_GPIO(n), 9, true);
 202     macio_set_gpio(MACIO_GPIO(n), 9, false);
 203 }
 204
 205 static void macio_gpio_class_init(ObjectClass *oc, void *data)
 206 {
 207     DeviceClass *dc = DEVICE_CLASS(oc);
 208     NMIClass *nc = NMI_CLASS(oc);
 209
 210     dc->realize = macio_gpio_realize;
 211     dc->reset = macio_gpio_reset;
 212     dc->vmsd = &vmstate_macio_gpio;
 213     nc->nmi_monitor_handler = macio_gpio_nmi;
 214 }
 215
 216 static const TypeInfo macio_gpio_init_info = {
 217     .name          = TYPE_MACIO_GPIO,
 218     .parent        = TYPE_SYS_BUS_DEVICE,
 219     .instance_size = sizeof(MacIOGPIOState),
 220     .instance_init = macio_gpio_init,
 221     .class_init    = macio_gpio_class_init,
 222     .interfaces = (InterfaceInfo[]) {
 223         { TYPE_NMI },
 224         { }
 225     },
 226 };
 227
 228 static void macio_gpio_register_types(void)
 229 {
 230     type_register_static(&macio_gpio_init_info);
 231 }
 232
 233 type_init(macio_gpio_register_types)