include/hw/intc/bcm2836_control.h

   1 /*
   2  * Raspberry Pi emulation (c) 2012 Gregory Estrade
   3  * Upstreaming code cleanup [including bcm2835_*] (c) 2013 Jan Petrous
   4  *
   5  * Rasperry Pi 2 emulation and refactoring Copyright (c) 2015, Microsoft
   6  * Written by Andrew Baumann
   7  *
   8  * This code is licensed under the GNU GPLv2 and later.
   9  */
  10
  11 #ifndef BCM2836_CONTROL_H
  12 #define BCM2836_CONTROL_H
  13
  14 #include "hw/sysbus.h"
  15
  16 /* 4 mailboxes per core, for 16 total */
  17 #define BCM2836_NCORES 4
  18 #define BCM2836_MBPERCORE 4
  19
  20 #define TYPE_BCM2836_CONTROL "bcm2836-control"
  21 #define BCM2836_CONTROL(obj) \
  22     OBJECT_CHECK(BCM2836ControlState, (obj), TYPE_BCM2836_CONTROL)
  23
  24 typedef struct BCM2836ControlState {
  25     /*< private >*/
  26     SysBusDevice busdev;
  27     /*< public >*/
  28     MemoryRegion iomem;
  29
  30     /* mailbox state */
  31     uint32_t mailboxes[BCM2836_NCORES * BCM2836_MBPERCORE];
  32
  33     /* interrupt routing/control registers */
  34     uint8_t route_gpu_irq, route_gpu_fiq;
  35     uint32_t timercontrol[BCM2836_NCORES];
  36     uint32_t mailboxcontrol[BCM2836_NCORES];
  37
  38     /* interrupt status regs (derived from input pins; not visible to user) */
  39     bool gpu_irq, gpu_fiq;
  40     uint8_t timerirqs[BCM2836_NCORES];
  41
  42     /* interrupt source registers, post-routing (also input-derived; visible) */
  43     uint32_t irqsrc[BCM2836_NCORES];
  44     uint32_t fiqsrc[BCM2836_NCORES];
  45
  46     /* outputs to CPU cores */
  47     qemu_irq irq[BCM2836_NCORES];
  48     qemu_irq fiq[BCM2836_NCORES];
  49 } BCM2836ControlState;
  50
  51 #endif