include/hw/ssi/aspeed_smc.h

   1 /*
   2  * ASPEED AST2400 SMC Controller (SPI Flash Only)
   3  *
   4  * Copyright (C) 2016 IBM Corp.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #ifndef ASPEED_SMC_H
  26 #define ASPEED_SMC_H
  27
  28 #include "hw/ssi/ssi.h"
  29
  30 typedef struct AspeedSegments {
  31     hwaddr addr;
  32     uint32_t size;
  33 } AspeedSegments;
  34
  35 struct AspeedSMCState;
  36 typedef struct AspeedSMCController {
  37     const char *name;
  38     uint8_t r_conf;
  39     uint8_t r_ce_ctrl;
  40     uint8_t r_ctrl0;
  41     uint8_t r_timings;
  42     uint8_t conf_enable_w0;
  43     uint8_t max_slaves;
  44     const AspeedSegments *segments;
  45     hwaddr flash_window_base;
  46     uint32_t flash_window_size;
  47     bool has_dma;
  48     uint32_t nregs;
  49 } AspeedSMCController;
  50
  51 typedef struct AspeedSMCFlash {
  52     struct AspeedSMCState *controller;
  53
  54     uint8_t id;
  55     uint32_t size;
  56
  57     MemoryRegion mmio;
  58     DeviceState *flash;
  59 } AspeedSMCFlash;
  60
  61 #define TYPE_ASPEED_SMC "aspeed.smc"
  62 #define ASPEED_SMC(obj) OBJECT_CHECK(AspeedSMCState, (obj), TYPE_ASPEED_SMC)
  63 #define ASPEED_SMC_CLASS(klass) \
  64      OBJECT_CLASS_CHECK(AspeedSMCClass, (klass), TYPE_ASPEED_SMC)
  65 #define ASPEED_SMC_GET_CLASS(obj) \
  66      OBJECT_GET_CLASS(AspeedSMCClass, (obj), TYPE_ASPEED_SMC)
  67
  68 typedef struct  AspeedSMCClass {
  69     SysBusDevice parent_obj;
  70     const AspeedSMCController *ctrl;
  71 }  AspeedSMCClass;
  72
  73 #define ASPEED_SMC_R_MAX        (0x100 / 4)
  74
  75 typedef struct AspeedSMCState {
  76     SysBusDevice parent_obj;
  77
  78     const AspeedSMCController *ctrl;
  79
  80     MemoryRegion mmio;
  81     MemoryRegion mmio_flash;
  82
  83     qemu_irq irq;
  84     int irqline;
  85
  86     uint32_t num_cs;
  87     qemu_irq *cs_lines;
  88
  89     SSIBus *spi;
  90
  91     uint32_t regs[ASPEED_SMC_R_MAX];
  92
  93     /* depends on the controller type */
  94     uint8_t r_conf;
  95     uint8_t r_ce_ctrl;
  96     uint8_t r_ctrl0;
  97     uint8_t r_timings;
  98     uint8_t conf_enable_w0;
  99
 100     AspeedSMCFlash *flashes;
 101 } AspeedSMCState;
 102
 103 #endif /* ASPEED_SMC_H */