hw/i386/pc.c

   1 /*
   2  * QEMU PC System Emulator
   3  *
   4  * Copyright (c) 2003-2004 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #include "qemu/osdep.h"
  26 #include "qemu/units.h"
  27 #include "hw/hw.h"
  28 #include "hw/i386/pc.h"
  29 #include "hw/char/serial.h"
  30 #include "hw/char/parallel.h"
  31 #include "hw/i386/apic.h"
  32 #include "hw/i386/topology.h"
  33 #include "sysemu/cpus.h"
  34 #include "hw/block/fdc.h"
  35 #include "hw/ide.h"
  36 #include "hw/pci/pci.h"
  37 #include "hw/pci/pci_bus.h"
  38 #include "hw/nvram/fw_cfg.h"
  39 #include "hw/timer/hpet.h"
  40 #include "hw/smbios/smbios.h"
  41 #include "hw/loader.h"
  42 #include "elf.h"
  43 #include "multiboot.h"
  44 #include "hw/timer/mc146818rtc.h"
  45 #include "hw/dma/i8257.h"
  46 #include "hw/timer/i8254.h"
  47 #include "hw/input/i8042.h"
  48 #include "hw/audio/pcspk.h"
  49 #include "hw/pci/msi.h"
  50 #include "hw/sysbus.h"
  51 #include "sysemu/sysemu.h"
  52 #include "sysemu/numa.h"
  53 #include "sysemu/kvm.h"
  54 #include "sysemu/qtest.h"
  55 #include "kvm_i386.h"
  56 #include "hw/xen/xen.h"
  57 #include "ui/qemu-spice.h"
  58 #include "exec/memory.h"
  59 #include "exec/address-spaces.h"
  60 #include "sysemu/arch_init.h"
  61 #include "qemu/bitmap.h"
  62 #include "qemu/config-file.h"
  63 #include "qemu/error-report.h"
  64 #include "qemu/option.h"
  65 #include "hw/acpi/acpi.h"
  66 #include "hw/acpi/cpu_hotplug.h"
  67 #include "hw/boards.h"
  68 #include "acpi-build.h"
  69 #include "hw/mem/pc-dimm.h"
  70 #include "qapi/error.h"
  71 #include "qapi/qapi-visit-common.h"
  72 #include "qapi/visitor.h"
  73 #include "qom/cpu.h"
  74 #include "hw/nmi.h"
  75 #include "hw/i386/intel_iommu.h"
  76 #include "hw/net/ne2000-isa.h"
  77
  78 /* debug PC/ISA interrupts */
  79 //#define DEBUG_IRQ
  80
  81 #ifdef DEBUG_IRQ
  82 #define DPRINTF(fmt, ...)                                       \
  83     do { printf("CPUIRQ: " fmt , ## __VA_ARGS__); } while (0)
  84 #else
  85 #define DPRINTF(fmt, ...)
  86 #endif
  87
  88 #define FW_CFG_ACPI_TABLES (FW_CFG_ARCH_LOCAL + 0)
  89 #define FW_CFG_SMBIOS_ENTRIES (FW_CFG_ARCH_LOCAL + 1)
  90 #define FW_CFG_IRQ0_OVERRIDE (FW_CFG_ARCH_LOCAL + 2)
  91 #define FW_CFG_E820_TABLE (FW_CFG_ARCH_LOCAL + 3)
  92 #define FW_CFG_HPET (FW_CFG_ARCH_LOCAL + 4)
  93
  94 #define E820_NR_ENTRIES         16
  95
  96 struct e820_entry {
  97     uint64_t address;
  98     uint64_t length;
  99     uint32_t type;
 100 } QEMU_PACKED __attribute((__aligned__(4)));
 101
 102 struct e820_table {
 103     uint32_t count;
 104     struct e820_entry entry[E820_NR_ENTRIES];
 105 } QEMU_PACKED __attribute((__aligned__(4)));
 106
 107 static struct e820_table e820_reserve;
 108 static struct e820_entry *e820_table;
 109 static unsigned e820_entries;
 110 struct hpet_fw_config hpet_cfg = {.count = UINT8_MAX};
 111
 112 void gsi_handler(void *opaque, int n, int level)
 113 {
 114     GSIState *s = opaque;
 115
 116     DPRINTF("pc: %s GSI %d\n", level ? "raising" : "lowering", n);
 117     if (n < ISA_NUM_IRQS) {
 118         qemu_set_irq(s->i8259_irq[n], level);
 119     }
 120     qemu_set_irq(s->ioapic_irq[n], level);
 121 }
 122
 123 static void ioport80_write(void *opaque, hwaddr addr, uint64_t data,
 124                            unsigned size)
 125 {
 126 }
 127
 128 static uint64_t ioport80_read(void *opaque, hwaddr addr, unsigned size)
 129 {
 130     return 0xffffffffffffffffULL;
 131 }
 132
 133 /* MSDOS compatibility mode FPU exception support */
 134 static qemu_irq ferr_irq;
 135
 136 void pc_register_ferr_irq(qemu_irq irq)
 137 {
 138     ferr_irq = irq;
 139 }
 140
 141 /* XXX: add IGNNE support */
 142 void cpu_set_ferr(CPUX86State *s)
 143 {
 144     qemu_irq_raise(ferr_irq);
 145 }
 146
 147 static void ioportF0_write(void *opaque, hwaddr addr, uint64_t data,
 148                            unsigned size)
 149 {
 150     qemu_irq_lower(ferr_irq);
 151 }
 152
 153 static uint64_t ioportF0_read(void *opaque, hwaddr addr, unsigned size)
 154 {
 155     return 0xffffffffffffffffULL;
 156 }
 157
 158 /* TSC handling */
 159 uint64_t cpu_get_tsc(CPUX86State *env)
 160 {
 161     return cpu_get_ticks();
 162 }
 163
 164 /* IRQ handling */
 165 int cpu_get_pic_interrupt(CPUX86State *env)
 166 {
 167     X86CPU *cpu = x86_env_get_cpu(env);
 168     int intno;
 169
 170     if (!kvm_irqchip_in_kernel()) {
 171         intno = apic_get_interrupt(cpu->apic_state);
 172         if (intno >= 0) {
 173             return intno;
 174         }
 175         /* read the irq from the PIC */
 176         if (!apic_accept_pic_intr(cpu->apic_state)) {
 177             return -1;
 178         }
 179     }
 180
 181     intno = pic_read_irq(isa_pic);
 182     return intno;
 183 }
 184
 185 static void pic_irq_request(void *opaque, int irq, int level)
 186 {
 187     CPUState *cs = first_cpu;
 188     X86CPU *cpu = X86_CPU(cs);
 189
 190     DPRINTF("pic_irqs: %s irq %d\n", level? "raise" : "lower", irq);
 191     if (cpu->apic_state && !kvm_irqchip_in_kernel()) {
 192         CPU_FOREACH(cs) {
 193             cpu = X86_CPU(cs);
 194             if (apic_accept_pic_intr(cpu->apic_state)) {
 195                 apic_deliver_pic_intr(cpu->apic_state, level);
 196             }
 197         }
 198     } else {
 199         if (level) {
 200             cpu_interrupt(cs, CPU_INTERRUPT_HARD);
 201         } else {
 202             cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
 203         }
 204     }
 205 }
 206
 207 /* PC cmos mappings */
 208
 209 #define REG_EQUIPMENT_BYTE          0x14
 210
 211 int cmos_get_fd_drive_type(FloppyDriveType fd0)
 212 {
 213     int val;
 214
 215     switch (fd0) {
 216     case FLOPPY_DRIVE_TYPE_144:
 217         /* 1.44 Mb 3"5 drive */
 218         val = 4;
 219         break;
 220     case FLOPPY_DRIVE_TYPE_288:
 221         /* 2.88 Mb 3"5 drive */
 222         val = 5;
 223         break;
 224     case FLOPPY_DRIVE_TYPE_120:
 225         /* 1.2 Mb 5"5 drive */
 226         val = 2;
 227         break;
 228     case FLOPPY_DRIVE_TYPE_NONE:
 229     default:
 230         val = 0;
 231         break;
 232     }
 233     return val;
 234 }
 235
 236 static void cmos_init_hd(ISADevice *s, int type_ofs, int info_ofs,
 237                          int16_t cylinders, int8_t heads, int8_t sectors)
 238 {
 239     rtc_set_memory(s, type_ofs, 47);
 240     rtc_set_memory(s, info_ofs, cylinders);
 241     rtc_set_memory(s, info_ofs + 1, cylinders >> 8);
 242     rtc_set_memory(s, info_ofs + 2, heads);
 243     rtc_set_memory(s, info_ofs + 3, 0xff);
 244     rtc_set_memory(s, info_ofs + 4, 0xff);
 245     rtc_set_memory(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3));
 246     rtc_set_memory(s, info_ofs + 6, cylinders);
 247     rtc_set_memory(s, info_ofs + 7, cylinders >> 8);
 248     rtc_set_memory(s, info_ofs + 8, sectors);
 249 }
 250
 251 /* convert boot_device letter to something recognizable by the bios */
 252 static int boot_device2nibble(char boot_device)
 253 {
 254     switch(boot_device) {
 255     case 'a':
 256     case 'b':
 257         return 0x01; /* floppy boot */
 258     case 'c':
 259         return 0x02; /* hard drive boot */
 260     case 'd':
 261         return 0x03; /* CD-ROM boot */
 262     case 'n':
 263         return 0x04; /* Network boot */
 264     }
 265     return 0;
 266 }
 267
 268 static void set_boot_dev(ISADevice *s, const char *boot_device, Error **errp)
 269 {
 270 #define PC_MAX_BOOT_DEVICES 3
 271     int nbds, bds[3] = { 0, };
 272     int i;
 273
 274     nbds = strlen(boot_device);
 275     if (nbds > PC_MAX_BOOT_DEVICES) {
 276         error_setg(errp, "Too many boot devices for PC");
 277         return;
 278     }
 279     for (i = 0; i < nbds; i++) {
 280         bds[i] = boot_device2nibble(boot_device[i]);
 281         if (bds[i] == 0) {
 282             error_setg(errp, "Invalid boot device for PC: '%c'",
 283                        boot_device[i]);
 284             return;
 285         }
 286     }
 287     rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]);
 288     rtc_set_memory(s, 0x38, (bds[2] << 4) | (fd_bootchk ? 0x0 : 0x1));
 289 }
 290
 291 static void pc_boot_set(void *opaque, const char *boot_device, Error **errp)
 292 {
 293     set_boot_dev(opaque, boot_device, errp);
 294 }
 295
 296 static void pc_cmos_init_floppy(ISADevice *rtc_state, ISADevice *floppy)
 297 {
 298     int val, nb, i;
 299     FloppyDriveType fd_type[2] = { FLOPPY_DRIVE_TYPE_NONE,
 300                                    FLOPPY_DRIVE_TYPE_NONE };
 301
 302     /* floppy type */
 303     if (floppy) {
 304         for (i = 0; i < 2; i++) {
 305             fd_type[i] = isa_fdc_get_drive_type(floppy, i);
 306         }
 307     }
 308     val = (cmos_get_fd_drive_type(fd_type[0]) << 4) |
 309         cmos_get_fd_drive_type(fd_type[1]);
 310     rtc_set_memory(rtc_state, 0x10, val);
 311
 312     val = rtc_get_memory(rtc_state, REG_EQUIPMENT_BYTE);
 313     nb = 0;
 314     if (fd_type[0] != FLOPPY_DRIVE_TYPE_NONE) {
 315         nb++;
 316     }
 317     if (fd_type[1] != FLOPPY_DRIVE_TYPE_NONE) {
 318         nb++;
 319     }
 320     switch (nb) {
 321     case 0:
 322         break;
 323     case 1:
 324         val |= 0x01; /* 1 drive, ready for boot */
 325         break;
 326     case 2:
 327         val |= 0x41; /* 2 drives, ready for boot */
 328         break;
 329     }
 330     rtc_set_memory(rtc_state, REG_EQUIPMENT_BYTE, val);
 331 }
 332
 333 typedef struct pc_cmos_init_late_arg {
 334     ISADevice *rtc_state;
 335     BusState *idebus[2];
 336 } pc_cmos_init_late_arg;
 337
 338 typedef struct check_fdc_state {
 339     ISADevice *floppy;
 340     bool multiple;
 341 } CheckFdcState;
 342
 343 static int check_fdc(Object *obj, void *opaque)
 344 {
 345     CheckFdcState *state = opaque;
 346     Object *fdc;
 347     uint32_t iobase;
 348     Error *local_err = NULL;
 349
 350     fdc = object_dynamic_cast(obj, TYPE_ISA_FDC);
 351     if (!fdc) {
 352         return 0;
 353     }
 354
 355     iobase = object_property_get_uint(obj, "iobase", &local_err);
 356     if (local_err || iobase != 0x3f0) {
 357         error_free(local_err);
 358         return 0;
 359     }
 360
 361     if (state->floppy) {
 362         state->multiple = true;
 363     } else {
 364         state->floppy = ISA_DEVICE(obj);
 365     }
 366     return 0;
 367 }
 368
 369 static const char * const fdc_container_path[] = {
 370     "/unattached", "/peripheral", "/peripheral-anon"
 371 };
 372
 373 /*
 374  * Locate the FDC at IO address 0x3f0, in order to configure the CMOS registers
 375  * and ACPI objects.
 376  */
 377 ISADevice *pc_find_fdc0(void)
 378 {
 379     int i;
 380     Object *container;
 381     CheckFdcState state = { 0 };
 382
 383     for (i = 0; i < ARRAY_SIZE(fdc_container_path); i++) {
 384         container = container_get(qdev_get_machine(), fdc_container_path[i]);
 385         object_child_foreach(container, check_fdc, &state);
 386     }
 387
 388     if (state.multiple) {
 389         warn_report("multiple floppy disk controllers with "
 390                     "iobase=0x3f0 have been found");
 391         error_printf("the one being picked for CMOS setup might not reflect "
 392                      "your intent");
 393     }
 394
 395     return state.floppy;
 396 }
 397
 398 static void pc_cmos_init_late(void *opaque)
 399 {
 400     pc_cmos_init_late_arg *arg = opaque;
 401     ISADevice *s = arg->rtc_state;
 402     int16_t cylinders;
 403     int8_t heads, sectors;
 404     int val;
 405     int i, trans;
 406
 407     val = 0;
 408     if (arg->idebus[0] && ide_get_geometry(arg->idebus[0], 0,
 409                                            &cylinders, &heads, &sectors) >= 0) {
 410         cmos_init_hd(s, 0x19, 0x1b, cylinders, heads, sectors);
 411         val |= 0xf0;
 412     }
 413     if (arg->idebus[0] && ide_get_geometry(arg->idebus[0], 1,
 414                                            &cylinders, &heads, &sectors) >= 0) {
 415         cmos_init_hd(s, 0x1a, 0x24, cylinders, heads, sectors);
 416         val |= 0x0f;
 417     }
 418     rtc_set_memory(s, 0x12, val);
 419
 420     val = 0;
 421     for (i = 0; i < 4; i++) {
 422         /* NOTE: ide_get_geometry() returns the physical
 423            geometry.  It is always such that: 1 <= sects <= 63, 1
 424            <= heads <= 16, 1 <= cylinders <= 16383. The BIOS
 425            geometry can be different if a translation is done. */
 426         if (arg->idebus[i / 2] &&
 427             ide_get_geometry(arg->idebus[i / 2], i % 2,
 428                              &cylinders, &heads, &sectors) >= 0) {
 429             trans = ide_get_bios_chs_trans(arg->idebus[i / 2], i % 2) - 1;
 430             assert((trans & ~3) == 0);
 431             val |= trans << (i * 2);
 432         }
 433     }
 434     rtc_set_memory(s, 0x39, val);
 435
 436     pc_cmos_init_floppy(s, pc_find_fdc0());
 437
 438     qemu_unregister_reset(pc_cmos_init_late, opaque);
 439 }
 440
 441 void pc_cmos_init(PCMachineState *pcms,
 442                   BusState *idebus0, BusState *idebus1,
 443                   ISADevice *s)
 444 {
 445     int val;
 446     static pc_cmos_init_late_arg arg;
 447
 448     /* various important CMOS locations needed by PC/Bochs bios */
 449
 450     /* memory size */
 451     /* base memory (first MiB) */
 452     val = MIN(pcms->below_4g_mem_size / KiB, 640);
 453     rtc_set_memory(s, 0x15, val);
 454     rtc_set_memory(s, 0x16, val >> 8);
 455     /* extended memory (next 64MiB) */
 456     if (pcms->below_4g_mem_size > 1 * MiB) {
 457         val = (pcms->below_4g_mem_size - 1 * MiB) / KiB;
 458     } else {
 459         val = 0;
 460     }
 461     if (val > 65535)
 462         val = 65535;
 463     rtc_set_memory(s, 0x17, val);
 464     rtc_set_memory(s, 0x18, val >> 8);
 465     rtc_set_memory(s, 0x30, val);
 466     rtc_set_memory(s, 0x31, val >> 8);
 467     /* memory between 16MiB and 4GiB */
 468     if (pcms->below_4g_mem_size > 16 * MiB) {
 469         val = (pcms->below_4g_mem_size - 16 * MiB) / (64 * KiB);
 470     } else {
 471         val = 0;
 472     }
 473     if (val > 65535)
 474         val = 65535;
 475     rtc_set_memory(s, 0x34, val);
 476     rtc_set_memory(s, 0x35, val >> 8);
 477     /* memory above 4GiB */
 478     val = pcms->above_4g_mem_size / 65536;
 479     rtc_set_memory(s, 0x5b, val);
 480     rtc_set_memory(s, 0x5c, val >> 8);
 481     rtc_set_memory(s, 0x5d, val >> 16);
 482
 483     object_property_add_link(OBJECT(pcms), "rtc_state",
 484                              TYPE_ISA_DEVICE,
 485                              (Object **)&pcms->rtc,
 486                              object_property_allow_set_link,
 487                              OBJ_PROP_LINK_STRONG, &error_abort);
 488     object_property_set_link(OBJECT(pcms), OBJECT(s),
 489                              "rtc_state", &error_abort);
 490
 491     set_boot_dev(s, MACHINE(pcms)->boot_order, &error_fatal);
 492
 493     val = 0;
 494     val |= 0x02; /* FPU is there */
 495     val |= 0x04; /* PS/2 mouse installed */
 496     rtc_set_memory(s, REG_EQUIPMENT_BYTE, val);
 497
 498     /* hard drives and FDC */
 499     arg.rtc_state = s;
 500     arg.idebus[0] = idebus0;
 501     arg.idebus[1] = idebus1;
 502     qemu_register_reset(pc_cmos_init_late, &arg);
 503 }
 504
 505 #define TYPE_PORT92 "port92"
 506 #define PORT92(obj) OBJECT_CHECK(Port92State, (obj), TYPE_PORT92)
 507
 508 /* port 92 stuff: could be split off */
 509 typedef struct Port92State {
 510     ISADevice parent_obj;
 511
 512     MemoryRegion io;
 513     uint8_t outport;
 514     qemu_irq a20_out;
 515 } Port92State;
 516
 517 static void port92_write(void *opaque, hwaddr addr, uint64_t val,
 518                          unsigned size)
 519 {
 520     Port92State *s = opaque;
 521     int oldval = s->outport;
 522
 523     DPRINTF("port92: write 0x%02" PRIx64 "\n", val);
 524     s->outport = val;
 525     qemu_set_irq(s->a20_out, (val >> 1) & 1);
 526     if ((val & 1) && !(oldval & 1)) {
 527         qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
 528     }
 529 }
 530
 531 static uint64_t port92_read(void *opaque, hwaddr addr,
 532                             unsigned size)
 533 {
 534     Port92State *s = opaque;
 535     uint32_t ret;
 536
 537     ret = s->outport;
 538     DPRINTF("port92: read 0x%02x\n", ret);
 539     return ret;
 540 }
 541
 542 static void port92_init(ISADevice *dev, qemu_irq a20_out)
 543 {
 544     qdev_connect_gpio_out_named(DEVICE(dev), PORT92_A20_LINE, 0, a20_out);
 545 }
 546
 547 static const VMStateDescription vmstate_port92_isa = {
 548     .name = "port92",
 549     .version_id = 1,
 550     .minimum_version_id = 1,
 551     .fields = (VMStateField[]) {
 552         VMSTATE_UINT8(outport, Port92State),
 553         VMSTATE_END_OF_LIST()
 554     }
 555 };
 556
 557 static void port92_reset(DeviceState *d)
 558 {
 559     Port92State *s = PORT92(d);
 560
 561     s->outport &= ~1;
 562 }
 563
 564 static const MemoryRegionOps port92_ops = {
 565     .read = port92_read,
 566     .write = port92_write,
 567     .impl = {
 568         .min_access_size = 1,
 569         .max_access_size = 1,
 570     },
 571     .endianness = DEVICE_LITTLE_ENDIAN,
 572 };
 573
 574 static void port92_initfn(Object *obj)
 575 {
 576     Port92State *s = PORT92(obj);
 577
 578     memory_region_init_io(&s->io, OBJECT(s), &port92_ops, s, "port92", 1);
 579
 580     s->outport = 0;
 581
 582     qdev_init_gpio_out_named(DEVICE(obj), &s->a20_out, PORT92_A20_LINE, 1);
 583 }
 584
 585 static void port92_realizefn(DeviceState *dev, Error **errp)
 586 {
 587     ISADevice *isadev = ISA_DEVICE(dev);
 588     Port92State *s = PORT92(dev);
 589
 590     isa_register_ioport(isadev, &s->io, 0x92);
 591 }
 592
 593 static void port92_class_initfn(ObjectClass *klass, void *data)
 594 {
 595     DeviceClass *dc = DEVICE_CLASS(klass);
 596
 597     dc->realize = port92_realizefn;
 598     dc->reset = port92_reset;
 599     dc->vmsd = &vmstate_port92_isa;
 600     /*
 601      * Reason: unlike ordinary ISA devices, this one needs additional
 602      * wiring: its A20 output line needs to be wired up by
 603      * port92_init().
 604      */
 605     dc->user_creatable = false;
 606 }
 607
 608 static const TypeInfo port92_info = {
 609     .name          = TYPE_PORT92,
 610     .parent        = TYPE_ISA_DEVICE,
 611     .instance_size = sizeof(Port92State),
 612     .instance_init = port92_initfn,
 613     .class_init    = port92_class_initfn,
 614 };
 615
 616 static void port92_register_types(void)
 617 {
 618     type_register_static(&port92_info);
 619 }
 620
 621 type_init(port92_register_types)
 622
 623 static void handle_a20_line_change(void *opaque, int irq, int level)
 624 {
 625     X86CPU *cpu = opaque;
 626
 627     /* XXX: send to all CPUs ? */
 628     /* XXX: add logic to handle multiple A20 line sources */
 629     x86_cpu_set_a20(cpu, level);
 630 }
 631
 632 int e820_add_entry(uint64_t address, uint64_t length, uint32_t type)
 633 {
 634     int index = le32_to_cpu(e820_reserve.count);
 635     struct e820_entry *entry;
 636
 637     if (type != E820_RAM) {
 638         /* old FW_CFG_E820_TABLE entry -- reservations only */
 639         if (index >= E820_NR_ENTRIES) {
 640             return -EBUSY;
 641         }
 642         entry = &e820_reserve.entry[index++];
 643
 644         entry->address = cpu_to_le64(address);
 645         entry->length = cpu_to_le64(length);
 646         entry->type = cpu_to_le32(type);
 647
 648         e820_reserve.count = cpu_to_le32(index);
 649     }
 650
 651     /* new "etc/e820" file -- include ram too */
 652     e820_table = g_renew(struct e820_entry, e820_table, e820_entries + 1);
 653     e820_table[e820_entries].address = cpu_to_le64(address);
 654     e820_table[e820_entries].length = cpu_to_le64(length);
 655     e820_table[e820_entries].type = cpu_to_le32(type);
 656     e820_entries++;
 657
 658     return e820_entries;
 659 }
 660
 661 int e820_get_num_entries(void)
 662 {
 663     return e820_entries;
 664 }
 665
 666 bool e820_get_entry(int idx, uint32_t type, uint64_t *address, uint64_t *length)
 667 {
 668     if (idx < e820_entries && e820_table[idx].type == cpu_to_le32(type)) {
 669         *address = le64_to_cpu(e820_table[idx].address);
 670         *length = le64_to_cpu(e820_table[idx].length);
 671         return true;
 672     }
 673     return false;
 674 }
 675
 676 /* Enables contiguous-apic-ID mode, for compatibility */
 677 static bool compat_apic_id_mode;
 678
 679 void enable_compat_apic_id_mode(void)
 680 {
 681     compat_apic_id_mode = true;
 682 }
 683
 684 /* Calculates initial APIC ID for a specific CPU index
 685  *
 686  * Currently we need to be able to calculate the APIC ID from the CPU index
 687  * alone (without requiring a CPU object), as the QEMU<->Seabios interfaces have
 688  * no concept of "CPU index", and the NUMA tables on fw_cfg need the APIC ID of
 689  * all CPUs up to max_cpus.
 690  */
 691 static uint32_t x86_cpu_apic_id_from_index(unsigned int cpu_index)
 692 {
 693     uint32_t correct_id;
 694     static bool warned;
 695
 696     correct_id = x86_apicid_from_cpu_idx(smp_cores, smp_threads, cpu_index);
 697     if (compat_apic_id_mode) {
 698         if (cpu_index != correct_id && !warned && !qtest_enabled()) {
 699             error_report("APIC IDs set in compatibility mode, "
 700                          "CPU topology won't match the configuration");
 701             warned = true;
 702         }
 703         return cpu_index;
 704     } else {
 705         return correct_id;
 706     }
 707 }
 708
 709 static void pc_build_smbios(PCMachineState *pcms)
 710 {
 711     uint8_t *smbios_tables, *smbios_anchor;
 712     size_t smbios_tables_len, smbios_anchor_len;
 713     struct smbios_phys_mem_area *mem_array;
 714     unsigned i, array_count;
 715     MachineState *ms = MACHINE(pcms);
 716     X86CPU *cpu = X86_CPU(ms->possible_cpus->cpus[0].cpu);
 717
 718     /* tell smbios about cpuid version and features */
 719     smbios_set_cpuid(cpu->env.cpuid_version, cpu->env.features[FEAT_1_EDX]);
 720
 721     smbios_tables = smbios_get_table_legacy(&smbios_tables_len);
 722     if (smbios_tables) {
 723         fw_cfg_add_bytes(pcms->fw_cfg, FW_CFG_SMBIOS_ENTRIES,
 724                          smbios_tables, smbios_tables_len);
 725     }
 726
 727     /* build the array of physical mem area from e820 table */
 728     mem_array = g_malloc0(sizeof(*mem_array) * e820_get_num_entries());
 729     for (i = 0, array_count = 0; i < e820_get_num_entries(); i++) {
 730         uint64_t addr, len;
 731
 732         if (e820_get_entry(i, E820_RAM, &addr, &len)) {
 733             mem_array[array_count].address = addr;
 734             mem_array[array_count].length = len;
 735             array_count++;
 736         }
 737     }
 738     smbios_get_tables(mem_array, array_count,
 739                       &smbios_tables, &smbios_tables_len,
 740                       &smbios_anchor, &smbios_anchor_len);
 741     g_free(mem_array);
 742
 743     if (smbios_anchor) {
 744         fw_cfg_add_file(pcms->fw_cfg, "etc/smbios/smbios-tables",
 745                         smbios_tables, smbios_tables_len);
 746         fw_cfg_add_file(pcms->fw_cfg, "etc/smbios/smbios-anchor",
 747                         smbios_anchor, smbios_anchor_len);
 748     }
 749 }
 750
 751 static FWCfgState *bochs_bios_init(AddressSpace *as, PCMachineState *pcms)
 752 {
 753     FWCfgState *fw_cfg;
 754     uint64_t *numa_fw_cfg;
 755     int i;
 756     const CPUArchIdList *cpus;
 757     MachineClass *mc = MACHINE_GET_CLASS(pcms);
 758
 759     fw_cfg = fw_cfg_init_io_dma(FW_CFG_IO_BASE, FW_CFG_IO_BASE + 4, as);
 760     fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, pcms->boot_cpus);
 761
 762     /* FW_CFG_MAX_CPUS is a bit confusing/problematic on x86:
 763      *
 764      * For machine types prior to 1.8, SeaBIOS needs FW_CFG_MAX_CPUS for
 765      * building MPTable, ACPI MADT, ACPI CPU hotplug and ACPI SRAT table,
 766      * that tables are based on xAPIC ID and QEMU<->SeaBIOS interface
 767      * for CPU hotplug also uses APIC ID and not "CPU index".
 768      * This means that FW_CFG_MAX_CPUS is not the "maximum number of CPUs",
 769      * but the "limit to the APIC ID values SeaBIOS may see".
 770      *
 771      * So for compatibility reasons with old BIOSes we are stuck with
 772      * "etc/max-cpus" actually being apic_id_limit
 773      */
 774     fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)pcms->apic_id_limit);
 775     fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
 776     fw_cfg_add_bytes(fw_cfg, FW_CFG_ACPI_TABLES,
 777                      acpi_tables, acpi_tables_len);
 778     fw_cfg_add_i32(fw_cfg, FW_CFG_IRQ0_OVERRIDE, kvm_allows_irq0_override());
 779
 780     fw_cfg_add_bytes(fw_cfg, FW_CFG_E820_TABLE,
 781                      &e820_reserve, sizeof(e820_reserve));
 782     fw_cfg_add_file(fw_cfg, "etc/e820", e820_table,
 783                     sizeof(struct e820_entry) * e820_entries);
 784
 785     fw_cfg_add_bytes(fw_cfg, FW_CFG_HPET, &hpet_cfg, sizeof(hpet_cfg));
 786     /* allocate memory for the NUMA channel: one (64bit) word for the number
 787      * of nodes, one word for each VCPU->node and one word for each node to
 788      * hold the amount of memory.
 789      */
 790     numa_fw_cfg = g_new0(uint64_t, 1 + pcms->apic_id_limit + nb_numa_nodes);
 791     numa_fw_cfg[0] = cpu_to_le64(nb_numa_nodes);
 792     cpus = mc->possible_cpu_arch_ids(MACHINE(pcms));
 793     for (i = 0; i < cpus->len; i++) {
 794         unsigned int apic_id = cpus->cpus[i].arch_id;
 795         assert(apic_id < pcms->apic_id_limit);
 796         numa_fw_cfg[apic_id + 1] = cpu_to_le64(cpus->cpus[i].props.node_id);
 797     }
 798     for (i = 0; i < nb_numa_nodes; i++) {
 799         numa_fw_cfg[pcms->apic_id_limit + 1 + i] =
 800             cpu_to_le64(numa_info[i].node_mem);
 801     }
 802     fw_cfg_add_bytes(fw_cfg, FW_CFG_NUMA, numa_fw_cfg,
 803                      (1 + pcms->apic_id_limit + nb_numa_nodes) *
 804                      sizeof(*numa_fw_cfg));
 805
 806     return fw_cfg;
 807 }
 808
 809 static long get_file_size(FILE *f)
 810 {
 811     long where, size;
 812
 813     /* XXX: on Unix systems, using fstat() probably makes more sense */
 814
 815     where = ftell(f);
 816     fseek(f, 0, SEEK_END);
 817     size = ftell(f);
 818     fseek(f, where, SEEK_SET);
 819
 820     return size;
 821 }
 822
 823 /* setup_data types */
 824 #define SETUP_NONE     0
 825 #define SETUP_E820_EXT 1
 826 #define SETUP_DTB      2
 827 #define SETUP_PCI      3
 828 #define SETUP_EFI      4
 829
 830 struct setup_data {
 831     uint64_t next;
 832     uint32_t type;
 833     uint32_t len;
 834     uint8_t data[0];
 835 } __attribute__((packed));
 836
 837 static void load_linux(PCMachineState *pcms,
 838                        FWCfgState *fw_cfg)
 839 {
 840     uint16_t protocol;
 841     int setup_size, kernel_size, cmdline_size;
 842     int64_t initrd_size = 0;
 843     int dtb_size, setup_data_offset;
 844     uint32_t initrd_max;
 845     uint8_t header[8192], *setup, *kernel, *initrd_data;
 846     hwaddr real_addr, prot_addr, cmdline_addr, initrd_addr = 0;
 847     FILE *f;
 848     char *vmode;
 849     MachineState *machine = MACHINE(pcms);
 850     PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
 851     struct setup_data *setup_data;
 852     const char *kernel_filename = machine->kernel_filename;
 853     const char *initrd_filename = machine->initrd_filename;
 854     const char *dtb_filename = machine->dtb;
 855     const char *kernel_cmdline = machine->kernel_cmdline;
 856
 857     /* Align to 16 bytes as a paranoia measure */
 858     cmdline_size = (strlen(kernel_cmdline)+16) & ~15;
 859
 860     /* load the kernel header */
 861     f = fopen(kernel_filename, "rb");
 862     if (!f || !(kernel_size = get_file_size(f)) ||
 863         fread(header, 1, MIN(ARRAY_SIZE(header), kernel_size), f) !=
 864         MIN(ARRAY_SIZE(header), kernel_size)) {
 865         fprintf(stderr, "qemu: could not load kernel '%s': %s\n",
 866                 kernel_filename, strerror(errno));
 867         exit(1);
 868     }
 869
 870     /* kernel protocol version */
 871 #if 0
 872     fprintf(stderr, "header magic: %#x\n", ldl_p(header+0x202));
 873 #endif
 874     if (ldl_p(header+0x202) == 0x53726448) {
 875         protocol = lduw_p(header+0x206);
 876     } else {
 877         /* This looks like a multiboot kernel. If it is, let's stop
 878            treating it like a Linux kernel. */
 879         if (load_multiboot(fw_cfg, f, kernel_filename, initrd_filename,
 880                            kernel_cmdline, kernel_size, header)) {
 881             return;
 882         }
 883         protocol = 0;
 884     }
 885
 886     if (protocol < 0x200 || !(header[0x211] & 0x01)) {
 887         /* Low kernel */
 888         real_addr    = 0x90000;
 889         cmdline_addr = 0x9a000 - cmdline_size;
 890         prot_addr    = 0x10000;
 891     } else if (protocol < 0x202) {
 892         /* High but ancient kernel */
 893         real_addr    = 0x90000;
 894         cmdline_addr = 0x9a000 - cmdline_size;
 895         prot_addr    = 0x100000;
 896     } else {
 897         /* High and recent kernel */
 898         real_addr    = 0x10000;
 899         cmdline_addr = 0x20000;
 900         prot_addr    = 0x100000;
 901     }
 902
 903 #if 0
 904     fprintf(stderr,
 905             "qemu: real_addr     = 0x" TARGET_FMT_plx "\n"
 906             "qemu: cmdline_addr  = 0x" TARGET_FMT_plx "\n"
 907             "qemu: prot_addr     = 0x" TARGET_FMT_plx "\n",
 908             real_addr,
 909             cmdline_addr,
 910             prot_addr);
 911 #endif
 912
 913     /* highest address for loading the initrd */
 914     if (protocol >= 0x203) {
 915         initrd_max = ldl_p(header+0x22c);
 916     } else {
 917         initrd_max = 0x37ffffff;
 918     }
 919
 920     if (initrd_max >= pcms->below_4g_mem_size - pcmc->acpi_data_size) {
 921         initrd_max = pcms->below_4g_mem_size - pcmc->acpi_data_size - 1;
 922     }
 923
 924     fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_ADDR, cmdline_addr);
 925     fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, strlen(kernel_cmdline)+1);
 926     fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, kernel_cmdline);
 927
 928     if (protocol >= 0x202) {
 929         stl_p(header+0x228, cmdline_addr);
 930     } else {
 931         stw_p(header+0x20, 0xA33F);
 932         stw_p(header+0x22, cmdline_addr-real_addr);
 933     }
 934
 935     /* handle vga= parameter */
 936     vmode = strstr(kernel_cmdline, "vga=");
 937     if (vmode) {
 938         unsigned int video_mode;
 939         /* skip "vga=" */
 940         vmode += 4;
 941         if (!strncmp(vmode, "normal", 6)) {
 942             video_mode = 0xffff;
 943         } else if (!strncmp(vmode, "ext", 3)) {
 944             video_mode = 0xfffe;
 945         } else if (!strncmp(vmode, "ask", 3)) {
 946             video_mode = 0xfffd;
 947         } else {
 948             video_mode = strtol(vmode, NULL, 0);
 949         }
 950         stw_p(header+0x1fa, video_mode);
 951     }
 952
 953     /* loader type */
 954     /* High nybble = B reserved for QEMU; low nybble is revision number.
 955        If this code is substantially changed, you may want to consider
 956        incrementing the revision. */
 957     if (protocol >= 0x200) {
 958         header[0x210] = 0xB0;
 959     }
 960     /* heap */
 961     if (protocol >= 0x201) {
 962         header[0x211] |= 0x80;  /* CAN_USE_HEAP */
 963         stw_p(header+0x224, cmdline_addr-real_addr-0x200);
 964     }
 965
 966     /* load initrd */
 967     if (initrd_filename) {
 968         if (protocol < 0x200) {
 969             fprintf(stderr, "qemu: linux kernel too old to load a ram disk\n");
 970             exit(1);
 971         }
 972
 973         initrd_size = get_image_size(initrd_filename);
 974         if (initrd_size < 0) {
 975             fprintf(stderr, "qemu: error reading initrd %s: %s\n",
 976                     initrd_filename, strerror(errno));
 977             exit(1);
 978         } else if (initrd_size >= initrd_max) {
 979             fprintf(stderr, "qemu: initrd is too large, cannot support."
 980                     "(max: %"PRIu32", need %"PRId64")\n", initrd_max, initrd_size);
 981             exit(1);
 982         }
 983
 984         initrd_addr = (initrd_max-initrd_size) & ~4095;
 985
 986         initrd_data = g_malloc(initrd_size);
 987         load_image(initrd_filename, initrd_data);
 988
 989         fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr);
 990         fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size);
 991         fw_cfg_add_bytes(fw_cfg, FW_CFG_INITRD_DATA, initrd_data, initrd_size);
 992
 993         stl_p(header+0x218, initrd_addr);
 994         stl_p(header+0x21c, initrd_size);
 995     }
 996
 997     /* load kernel and setup */
 998     setup_size = header[0x1f1];
 999     if (setup_size == 0) {
1000         setup_size = 4;
1001     }
1002     setup_size = (setup_size+1)*512;
1003     if (setup_size > kernel_size) {
1004         fprintf(stderr, "qemu: invalid kernel header\n");
1005         exit(1);
1006     }
1007     kernel_size -= setup_size;
1008
1009     setup  = g_malloc(setup_size);
1010     kernel = g_malloc(kernel_size);
1011     fseek(f, 0, SEEK_SET);
1012     if (fread(setup, 1, setup_size, f) != setup_size) {
1013         fprintf(stderr, "fread() failed\n");
1014         exit(1);
1015     }
1016     if (fread(kernel, 1, kernel_size, f) != kernel_size) {
1017         fprintf(stderr, "fread() failed\n");
1018         exit(1);
1019     }
1020     fclose(f);
1021
1022     /* append dtb to kernel */
1023     if (dtb_filename) {
1024         if (protocol < 0x209) {
1025             fprintf(stderr, "qemu: Linux kernel too old to load a dtb\n");
1026             exit(1);
1027         }
1028
1029         dtb_size = get_image_size(dtb_filename);
1030         if (dtb_size <= 0) {
1031             fprintf(stderr, "qemu: error reading dtb %s: %s\n",
1032                     dtb_filename, strerror(errno));
1033             exit(1);
1034         }
1035
1036         setup_data_offset = QEMU_ALIGN_UP(kernel_size, 16);
1037         kernel_size = setup_data_offset + sizeof(struct setup_data) + dtb_size;
1038         kernel = g_realloc(kernel, kernel_size);
1039
1040         stq_p(header+0x250, prot_addr + setup_data_offset);
1041
1042         setup_data = (struct setup_data *)(kernel + setup_data_offset);
1043         setup_data->next = 0;
1044         setup_data->type = cpu_to_le32(SETUP_DTB);
1045         setup_data->len = cpu_to_le32(dtb_size);
1046
1047         load_image_size(dtb_filename, setup_data->data, dtb_size);
1048     }
1049
1050     memcpy(setup, header, MIN(sizeof(header), setup_size));
1051
1052     fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, prot_addr);
1053     fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
1054     fw_cfg_add_bytes(fw_cfg, FW_CFG_KERNEL_DATA, kernel, kernel_size);
1055
1056     fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_ADDR, real_addr);
1057     fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_SIZE, setup_size);
1058     fw_cfg_add_bytes(fw_cfg, FW_CFG_SETUP_DATA, setup, setup_size);
1059
1060     option_rom[nb_option_roms].bootindex = 0;
1061     option_rom[nb_option_roms].name = "linuxboot.bin";
1062     if (pcmc->linuxboot_dma_enabled && fw_cfg_dma_enabled(fw_cfg)) {
1063         option_rom[nb_option_roms].name = "linuxboot_dma.bin";
1064     }
1065     nb_option_roms++;
1066 }
1067
1068 #define NE2000_NB_MAX 6
1069
1070 static const int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360,
1071                                               0x280, 0x380 };
1072 static const int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 };
1073
1074 void pc_init_ne2k_isa(ISABus *bus, NICInfo *nd)
1075 {
1076     static int nb_ne2k = 0;
1077
1078     if (nb_ne2k == NE2000_NB_MAX)
1079         return;
1080     isa_ne2000_init(bus, ne2000_io[nb_ne2k],
1081                     ne2000_irq[nb_ne2k], nd);
1082     nb_ne2k++;
1083 }
1084
1085 DeviceState *cpu_get_current_apic(void)
1086 {
1087     if (current_cpu) {
1088         X86CPU *cpu = X86_CPU(current_cpu);
1089         return cpu->apic_state;
1090     } else {
1091         return NULL;
1092     }
1093 }
1094
1095 void pc_acpi_smi_interrupt(void *opaque, int irq, int level)
1096 {
1097     X86CPU *cpu = opaque;
1098
1099     if (level) {
1100         cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
1101     }
1102 }
1103
1104 static void pc_new_cpu(const char *typename, int64_t apic_id, Error **errp)
1105 {
1106     Object *cpu = NULL;
1107     Error *local_err = NULL;
1108
1109     cpu = object_new(typename);
1110
1111     object_property_set_uint(cpu, apic_id, "apic-id", &local_err);
1112     object_property_set_bool(cpu, true, "realized", &local_err);
1113
1114     object_unref(cpu);
1115     error_propagate(errp, local_err);
1116 }
1117
1118 void pc_hot_add_cpu(const int64_t id, Error **errp)
1119 {
1120     MachineState *ms = MACHINE(qdev_get_machine());
1121     int64_t apic_id = x86_cpu_apic_id_from_index(id);
1122     Error *local_err = NULL;
1123
1124     if (id < 0) {
1125         error_setg(errp, "Invalid CPU id: %" PRIi64, id);
1126         return;
1127     }
1128
1129     if (apic_id >= ACPI_CPU_HOTPLUG_ID_LIMIT) {
1130         error_setg(errp, "Unable to add CPU: %" PRIi64
1131                    ", resulting APIC ID (%" PRIi64 ") is too large",
1132                    id, apic_id);
1133         return;
1134     }
1135
1136     pc_new_cpu(ms->cpu_type, apic_id, &local_err);
1137     if (local_err) {
1138         error_propagate(errp, local_err);
1139         return;
1140     }
1141 }
1142
1143 void pc_cpus_init(PCMachineState *pcms)
1144 {
1145     int i;
1146     const CPUArchIdList *possible_cpus;
1147     MachineState *ms = MACHINE(pcms);
1148     MachineClass *mc = MACHINE_GET_CLASS(pcms);
1149
1150     /* Calculates the limit to CPU APIC ID values
1151      *
1152      * Limit for the APIC ID value, so that all
1153      * CPU APIC IDs are < pcms->apic_id_limit.
1154      *
1155      * This is used for FW_CFG_MAX_CPUS. See comments on bochs_bios_init().
1156      */
1157     pcms->apic_id_limit = x86_cpu_apic_id_from_index(max_cpus - 1) + 1;
1158     possible_cpus = mc->possible_cpu_arch_ids(ms);
1159     for (i = 0; i < smp_cpus; i++) {
1160         pc_new_cpu(possible_cpus->cpus[i].type, possible_cpus->cpus[i].arch_id,
1161                    &error_fatal);
1162     }
1163 }
1164
1165 static void pc_build_feature_control_file(PCMachineState *pcms)
1166 {
1167     MachineState *ms = MACHINE(pcms);
1168     X86CPU *cpu = X86_CPU(ms->possible_cpus->cpus[0].cpu);
1169     CPUX86State *env = &cpu->env;
1170     uint32_t unused, ecx, edx;
1171     uint64_t feature_control_bits = 0;
1172     uint64_t *val;
1173
1174     cpu_x86_cpuid(env, 1, 0, &unused, &unused, &ecx, &edx);
1175     if (ecx & CPUID_EXT_VMX) {
1176         feature_control_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
1177     }
1178
1179     if ((edx & (CPUID_EXT2_MCE | CPUID_EXT2_MCA)) ==
1180         (CPUID_EXT2_MCE | CPUID_EXT2_MCA) &&
1181         (env->mcg_cap & MCG_LMCE_P)) {
1182         feature_control_bits |= FEATURE_CONTROL_LMCE;
1183     }
1184
1185     if (!feature_control_bits) {
1186         return;
1187     }
1188
1189     val = g_malloc(sizeof(*val));
1190     *val = cpu_to_le64(feature_control_bits | FEATURE_CONTROL_LOCKED);
1191     fw_cfg_add_file(pcms->fw_cfg, "etc/msr_feature_control", val, sizeof(*val));
1192 }
1193
1194 static void rtc_set_cpus_count(ISADevice *rtc, uint16_t cpus_count)
1195 {
1196     if (cpus_count > 0xff) {
1197         /* If the number of CPUs can't be represented in 8 bits, the
1198          * BIOS must use "FW_CFG_NB_CPUS". Set RTC field to 0 just
1199          * to make old BIOSes fail more predictably.
1200          */
1201         rtc_set_memory(rtc, 0x5f, 0);
1202     } else {
1203         rtc_set_memory(rtc, 0x5f, cpus_count - 1);
1204     }
1205 }
1206
1207 static
1208 void pc_machine_done(Notifier *notifier, void *data)
1209 {
1210     PCMachineState *pcms = container_of(notifier,
1211                                         PCMachineState, machine_done);
1212     PCIBus *bus = pcms->bus;
1213
1214     /* set the number of CPUs */
1215     rtc_set_cpus_count(pcms->rtc, pcms->boot_cpus);
1216
1217     if (bus) {
1218         int extra_hosts = 0;
1219
1220         QLIST_FOREACH(bus, &bus->child, sibling) {
1221             /* look for expander root buses */
1222             if (pci_bus_is_root(bus)) {
1223                 extra_hosts++;
1224             }
1225         }
1226         if (extra_hosts && pcms->fw_cfg) {
1227             uint64_t *val = g_malloc(sizeof(*val));
1228             *val = cpu_to_le64(extra_hosts);
1229             fw_cfg_add_file(pcms->fw_cfg,
1230                     "etc/extra-pci-roots", val, sizeof(*val));
1231         }
1232     }
1233
1234     acpi_setup();
1235     if (pcms->fw_cfg) {
1236         pc_build_smbios(pcms);
1237         pc_build_feature_control_file(pcms);
1238         /* update FW_CFG_NB_CPUS to account for -device added CPUs */
1239         fw_cfg_modify_i16(pcms->fw_cfg, FW_CFG_NB_CPUS, pcms->boot_cpus);
1240     }
1241
1242     if (pcms->apic_id_limit > 255 && !xen_enabled()) {
1243         IntelIOMMUState *iommu = INTEL_IOMMU_DEVICE(x86_iommu_get_default());
1244
1245         if (!iommu || !iommu->x86_iommu.intr_supported ||
1246             iommu->intr_eim != ON_OFF_AUTO_ON) {
1247             error_report("current -smp configuration requires "
1248                          "Extended Interrupt Mode enabled. "
1249                          "You can add an IOMMU using: "
1250                          "-device intel-iommu,intremap=on,eim=on");
1251             exit(EXIT_FAILURE);
1252         }
1253     }
1254 }
1255
1256 void pc_guest_info_init(PCMachineState *pcms)
1257 {
1258     int i;
1259
1260     pcms->apic_xrupt_override = kvm_allows_irq0_override();
1261     pcms->numa_nodes = nb_numa_nodes;
1262     pcms->node_mem = g_malloc0(pcms->numa_nodes *
1263                                     sizeof *pcms->node_mem);
1264     for (i = 0; i < nb_numa_nodes; i++) {
1265         pcms->node_mem[i] = numa_info[i].node_mem;
1266     }
1267
1268     pcms->machine_done.notify = pc_machine_done;
1269     qemu_add_machine_init_done_notifier(&pcms->machine_done);
1270 }
1271
1272 /* setup pci memory address space mapping into system address space */
1273 void pc_pci_as_mapping_init(Object *owner, MemoryRegion *system_memory,
1274                             MemoryRegion *pci_address_space)
1275 {
1276     /* Set to lower priority than RAM */
1277     memory_region_add_subregion_overlap(system_memory, 0x0,
1278                                         pci_address_space, -1);
1279 }
1280
1281 void pc_acpi_init(const char *default_dsdt)
1282 {
1283     char *filename;
1284
1285     if (acpi_tables != NULL) {
1286         /* manually set via -acpitable, leave it alone */
1287         return;
1288     }
1289
1290     filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, default_dsdt);
1291     if (filename == NULL) {
1292         warn_report("failed to find %s", default_dsdt);
1293     } else {
1294         QemuOpts *opts = qemu_opts_create(qemu_find_opts("acpi"), NULL, 0,
1295                                           &error_abort);
1296         Error *err = NULL;
1297
1298         qemu_opt_set(opts, "file", filename, &error_abort);
1299
1300         acpi_table_add_builtin(opts, &err);
1301         if (err) {
1302             warn_reportf_err(err, "failed to load %s: ", filename);
1303         }
1304         g_free(filename);
1305     }
1306 }
1307
1308 void xen_load_linux(PCMachineState *pcms)
1309 {
1310     int i;
1311     FWCfgState *fw_cfg;
1312
1313     assert(MACHINE(pcms)->kernel_filename != NULL);
1314
1315     fw_cfg = fw_cfg_init_io(FW_CFG_IO_BASE);
1316     fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, pcms->boot_cpus);
1317     rom_set_fw(fw_cfg);
1318
1319     load_linux(pcms, fw_cfg);
1320     for (i = 0; i < nb_option_roms; i++) {
1321         assert(!strcmp(option_rom[i].name, "linuxboot.bin") ||
1322                !strcmp(option_rom[i].name, "linuxboot_dma.bin") ||
1323                !strcmp(option_rom[i].name, "multiboot.bin"));
1324         rom_add_option(option_rom[i].name, option_rom[i].bootindex);
1325     }
1326     pcms->fw_cfg = fw_cfg;
1327 }
1328
1329 void pc_memory_init(PCMachineState *pcms,
1330                     MemoryRegion *system_memory,
1331                     MemoryRegion *rom_memory,
1332                     MemoryRegion **ram_memory)
1333 {
1334     int linux_boot, i;
1335     MemoryRegion *ram, *option_rom_mr;
1336     MemoryRegion *ram_below_4g, *ram_above_4g;
1337     FWCfgState *fw_cfg;
1338     MachineState *machine = MACHINE(pcms);
1339     PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
1340
1341     assert(machine->ram_size == pcms->below_4g_mem_size +
1342                                 pcms->above_4g_mem_size);
1343
1344     linux_boot = (machine->kernel_filename != NULL);
1345
1346     /* Allocate RAM.  We allocate it as a single memory region and use
1347      * aliases to address portions of it, mostly for backwards compatibility
1348      * with older qemus that used qemu_ram_alloc().
1349      */
1350     ram = g_malloc(sizeof(*ram));
1351     memory_region_allocate_system_memory(ram, NULL, "pc.ram",
1352                                          machine->ram_size);
1353     *ram_memory = ram;
1354     ram_below_4g = g_malloc(sizeof(*ram_below_4g));
1355     memory_region_init_alias(ram_below_4g, NULL, "ram-below-4g", ram,
1356                              0, pcms->below_4g_mem_size);
1357     memory_region_add_subregion(system_memory, 0, ram_below_4g);
1358     e820_add_entry(0, pcms->below_4g_mem_size, E820_RAM);
1359     if (pcms->above_4g_mem_size > 0) {
1360         ram_above_4g = g_malloc(sizeof(*ram_above_4g));
1361         memory_region_init_alias(ram_above_4g, NULL, "ram-above-4g", ram,
1362                                  pcms->below_4g_mem_size,
1363                                  pcms->above_4g_mem_size);
1364         memory_region_add_subregion(system_memory, 0x100000000ULL,
1365                                     ram_above_4g);
1366         e820_add_entry(0x100000000ULL, pcms->above_4g_mem_size, E820_RAM);
1367     }
1368
1369     if (!pcmc->has_reserved_memory &&
1370         (machine->ram_slots ||
1371          (machine->maxram_size > machine->ram_size))) {
1372         MachineClass *mc = MACHINE_GET_CLASS(machine);
1373
1374         error_report("\"-memory 'slots|maxmem'\" is not supported by: %s",
1375                      mc->name);
1376         exit(EXIT_FAILURE);
1377     }
1378
1379     /* always allocate the device memory information */
1380     machine->device_memory = g_malloc0(sizeof(*machine->device_memory));
1381
1382     /* initialize device memory address space */
1383     if (pcmc->has_reserved_memory &&
1384         (machine->ram_size < machine->maxram_size)) {
1385         ram_addr_t device_mem_size = machine->maxram_size - machine->ram_size;
1386
1387         if (machine->ram_slots > ACPI_MAX_RAM_SLOTS) {
1388             error_report("unsupported amount of memory slots: %"PRIu64,
1389                          machine->ram_slots);
1390             exit(EXIT_FAILURE);
1391         }
1392
1393         if (QEMU_ALIGN_UP(machine->maxram_size,
1394                           TARGET_PAGE_SIZE) != machine->maxram_size) {
1395             error_report("maximum memory size must by aligned to multiple of "
1396                          "%d bytes", TARGET_PAGE_SIZE);
1397             exit(EXIT_FAILURE);
1398         }
1399
1400         machine->device_memory->base =
1401             ROUND_UP(0x100000000ULL + pcms->above_4g_mem_size, 1 * GiB);
1402
1403         if (pcmc->enforce_aligned_dimm) {
1404             /* size device region assuming 1G page max alignment per slot */
1405             device_mem_size += (1 * GiB) * machine->ram_slots;
1406         }
1407
1408         if ((machine->device_memory->base + device_mem_size) <
1409             device_mem_size) {
1410             error_report("unsupported amount of maximum memory: " RAM_ADDR_FMT,
1411                          machine->maxram_size);
1412             exit(EXIT_FAILURE);
1413         }
1414
1415         memory_region_init(&machine->device_memory->mr, OBJECT(pcms),
1416                            "device-memory", device_mem_size);
1417         memory_region_add_subregion(system_memory, machine->device_memory->base,
1418                                     &machine->device_memory->mr);
1419     }
1420
1421     /* Initialize PC system firmware */
1422     pc_system_firmware_init(rom_memory, !pcmc->pci_enabled);
1423
1424     option_rom_mr = g_malloc(sizeof(*option_rom_mr));
1425     memory_region_init_ram(option_rom_mr, NULL, "pc.rom", PC_ROM_SIZE,
1426                            &error_fatal);
1427     if (pcmc->pci_enabled) {
1428         memory_region_set_readonly(option_rom_mr, true);
1429     }
1430     memory_region_add_subregion_overlap(rom_memory,
1431                                         PC_ROM_MIN_VGA,
1432                                         option_rom_mr,
1433                                         1);
1434
1435     fw_cfg = bochs_bios_init(&address_space_memory, pcms);
1436
1437     rom_set_fw(fw_cfg);
1438
1439     if (pcmc->has_reserved_memory && machine->device_memory->base) {
1440         uint64_t *val = g_malloc(sizeof(*val));
1441         PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
1442         uint64_t res_mem_end = machine->device_memory->base;
1443
1444         if (!pcmc->broken_reserved_end) {
1445             res_mem_end += memory_region_size(&machine->device_memory->mr);
1446         }
1447         *val = cpu_to_le64(ROUND_UP(res_mem_end, 1 * GiB));
1448         fw_cfg_add_file(fw_cfg, "etc/reserved-memory-end", val, sizeof(*val));
1449     }
1450
1451     if (linux_boot) {
1452         load_linux(pcms, fw_cfg);
1453     }
1454
1455     for (i = 0; i < nb_option_roms; i++) {
1456         rom_add_option(option_rom[i].name, option_rom[i].bootindex);
1457     }
1458     pcms->fw_cfg = fw_cfg;
1459
1460     /* Init default IOAPIC address space */
1461     pcms->ioapic_as = &address_space_memory;
1462 }
1463
1464 /*
1465  * The 64bit pci hole starts after "above 4G RAM" and
1466  * potentially the space reserved for memory hotplug.
1467  */
1468 uint64_t pc_pci_hole64_start(void)
1469 {
1470     PCMachineState *pcms = PC_MACHINE(qdev_get_machine());
1471     PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
1472     MachineState *ms = MACHINE(pcms);
1473     uint64_t hole64_start = 0;
1474
1475     if (pcmc->has_reserved_memory && ms->device_memory->base) {
1476         hole64_start = ms->device_memory->base;
1477         if (!pcmc->broken_reserved_end) {
1478             hole64_start += memory_region_size(&ms->device_memory->mr);
1479         }
1480     } else {
1481         hole64_start = 0x100000000ULL + pcms->above_4g_mem_size;
1482     }
1483
1484     return ROUND_UP(hole64_start, 1 * GiB);
1485 }
1486
1487 qemu_irq pc_allocate_cpu_irq(void)
1488 {
1489     return qemu_allocate_irq(pic_irq_request, NULL, 0);
1490 }
1491
1492 DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus)
1493 {
1494     DeviceState *dev = NULL;
1495
1496     rom_set_order_override(FW_CFG_ORDER_OVERRIDE_VGA);
1497     if (pci_bus) {
1498         PCIDevice *pcidev = pci_vga_init(pci_bus);
1499         dev = pcidev ? &pcidev->qdev : NULL;
1500     } else if (isa_bus) {
1501         ISADevice *isadev = isa_vga_init(isa_bus);
1502         dev = isadev ? DEVICE(isadev) : NULL;
1503     }
1504     rom_reset_order_override();
1505     return dev;
1506 }
1507
1508 static const MemoryRegionOps ioport80_io_ops = {
1509     .write = ioport80_write,
1510     .read = ioport80_read,
1511     .endianness = DEVICE_NATIVE_ENDIAN,
1512     .impl = {
1513         .min_access_size = 1,
1514         .max_access_size = 1,
1515     },
1516 };
1517
1518 static const MemoryRegionOps ioportF0_io_ops = {
1519     .write = ioportF0_write,
1520     .read = ioportF0_read,
1521     .endianness = DEVICE_NATIVE_ENDIAN,
1522     .impl = {
1523         .min_access_size = 1,
1524         .max_access_size = 1,
1525     },
1526 };
1527
1528 static void pc_superio_init(ISABus *isa_bus, bool create_fdctrl, bool no_vmport)
1529 {
1530     int i;
1531     DriveInfo *fd[MAX_FD];
1532     qemu_irq *a20_line;
1533     ISADevice *i8042, *port92, *vmmouse;
1534
1535     serial_hds_isa_init(isa_bus, 0, MAX_ISA_SERIAL_PORTS);
1536     parallel_hds_isa_init(isa_bus, MAX_PARALLEL_PORTS);
1537
1538     for (i = 0; i < MAX_FD; i++) {
1539         fd[i] = drive_get(IF_FLOPPY, 0, i);
1540         create_fdctrl |= !!fd[i];
1541     }
1542     if (create_fdctrl) {
1543         fdctrl_init_isa(isa_bus, fd);
1544     }
1545
1546     i8042 = isa_create_simple(isa_bus, "i8042");
1547     if (!no_vmport) {
1548         vmport_init(isa_bus);
1549         vmmouse = isa_try_create(isa_bus, "vmmouse");
1550     } else {
1551         vmmouse = NULL;
1552     }
1553     if (vmmouse) {
1554         DeviceState *dev = DEVICE(vmmouse);
1555         qdev_prop_set_ptr(dev, "ps2_mouse", i8042);
1556         qdev_init_nofail(dev);
1557     }
1558     port92 = isa_create_simple(isa_bus, "port92");
1559
1560     a20_line = qemu_allocate_irqs(handle_a20_line_change, first_cpu, 2);
1561     i8042_setup_a20_line(i8042, a20_line[0]);
1562     port92_init(port92, a20_line[1]);
1563     g_free(a20_line);
1564 }
1565
1566 void pc_basic_device_init(ISABus *isa_bus, qemu_irq *gsi,
1567                           ISADevice **rtc_state,
1568                           bool create_fdctrl,
1569                           bool no_vmport,
1570                           bool has_pit,
1571                           uint32_t hpet_irqs)
1572 {
1573     int i;
1574     DeviceState *hpet = NULL;
1575     int pit_isa_irq = 0;
1576     qemu_irq pit_alt_irq = NULL;
1577     qemu_irq rtc_irq = NULL;
1578     ISADevice *pit = NULL;
1579     MemoryRegion *ioport80_io = g_new(MemoryRegion, 1);
1580     MemoryRegion *ioportF0_io = g_new(MemoryRegion, 1);
1581
1582     memory_region_init_io(ioport80_io, NULL, &ioport80_io_ops, NULL, "ioport80", 1);
1583     memory_region_add_subregion(isa_bus->address_space_io, 0x80, ioport80_io);
1584
1585     memory_region_init_io(ioportF0_io, NULL, &ioportF0_io_ops, NULL, "ioportF0", 1);
1586     memory_region_add_subregion(isa_bus->address_space_io, 0xf0, ioportF0_io);
1587
1588     /*
1589      * Check if an HPET shall be created.
1590      *
1591      * Without KVM_CAP_PIT_STATE2, we cannot switch off the in-kernel PIT
1592      * when the HPET wants to take over. Thus we have to disable the latter.
1593      */
1594     if (!no_hpet && (!kvm_irqchip_in_kernel() || kvm_has_pit_state2())) {
1595         /* In order to set property, here not using sysbus_try_create_simple */
1596         hpet = qdev_try_create(NULL, TYPE_HPET);
1597         if (hpet) {
1598             /* For pc-piix-*, hpet's intcap is always IRQ2. For pc-q35-1.7
1599              * and earlier, use IRQ2 for compat. Otherwise, use IRQ16~23,
1600              * IRQ8 and IRQ2.
1601              */
1602             uint8_t compat = object_property_get_uint(OBJECT(hpet),
1603                     HPET_INTCAP, NULL);
1604             if (!compat) {
1605                 qdev_prop_set_uint32(hpet, HPET_INTCAP, hpet_irqs);
1606             }
1607             qdev_init_nofail(hpet);
1608             sysbus_mmio_map(SYS_BUS_DEVICE(hpet), 0, HPET_BASE);
1609
1610             for (i = 0; i < GSI_NUM_PINS; i++) {
1611                 sysbus_connect_irq(SYS_BUS_DEVICE(hpet), i, gsi[i]);
1612             }
1613             pit_isa_irq = -1;
1614             pit_alt_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_PIT_INT);
1615             rtc_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_RTC_INT);
1616         }
1617     }
1618     *rtc_state = mc146818_rtc_init(isa_bus, 2000, rtc_irq);
1619
1620     qemu_register_boot_set(pc_boot_set, *rtc_state);
1621
1622     if (!xen_enabled() && has_pit) {
1623         if (kvm_pit_in_kernel()) {
1624             pit = kvm_pit_init(isa_bus, 0x40);
1625         } else {
1626             pit = i8254_pit_init(isa_bus, 0x40, pit_isa_irq, pit_alt_irq);
1627         }
1628         if (hpet) {
1629             /* connect PIT to output control line of the HPET */
1630             qdev_connect_gpio_out(hpet, 0, qdev_get_gpio_in(DEVICE(pit), 0));
1631         }
1632         pcspk_init(isa_bus, pit);
1633     }
1634
1635     i8257_dma_init(isa_bus, 0);
1636
1637     /* Super I/O */
1638     pc_superio_init(isa_bus, create_fdctrl, no_vmport);
1639 }
1640
1641 void pc_nic_init(PCMachineClass *pcmc, ISABus *isa_bus, PCIBus *pci_bus)
1642 {
1643     int i;
1644
1645     rom_set_order_override(FW_CFG_ORDER_OVERRIDE_NIC);
1646     for (i = 0; i < nb_nics; i++) {
1647         NICInfo *nd = &nd_table[i];
1648         const char *model = nd->model ? nd->model : pcmc->default_nic_model;
1649
1650         if (g_str_equal(model, "ne2k_isa")) {
1651             pc_init_ne2k_isa(isa_bus, nd);
1652         } else {
1653             pci_nic_init_nofail(nd, pci_bus, model, NULL);
1654         }
1655     }
1656     rom_reset_order_override();
1657 }
1658
1659 void ioapic_init_gsi(GSIState *gsi_state, const char *parent_name)
1660 {
1661     DeviceState *dev;
1662     SysBusDevice *d;
1663     unsigned int i;
1664
1665     if (kvm_ioapic_in_kernel()) {
1666         dev = qdev_create(NULL, "kvm-ioapic");
1667     } else {
1668         dev = qdev_create(NULL, "ioapic");
1669     }
1670     if (parent_name) {
1671         object_property_add_child(object_resolve_path(parent_name, NULL),
1672                                   "ioapic", OBJECT(dev), NULL);
1673     }
1674     qdev_init_nofail(dev);
1675     d = SYS_BUS_DEVICE(dev);
1676     sysbus_mmio_map(d, 0, IO_APIC_DEFAULT_ADDRESS);
1677
1678     for (i = 0; i < IOAPIC_NUM_PINS; i++) {
1679         gsi_state->ioapic_irq[i] = qdev_get_gpio_in(dev, i);
1680     }
1681 }
1682
1683 static void pc_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
1684                                Error **errp)
1685 {
1686     const PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1687     const PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
1688     const bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM);
1689     const uint64_t legacy_align = TARGET_PAGE_SIZE;
1690
1691     /*
1692      * When -no-acpi is used with Q35 machine type, no ACPI is built,
1693      * but pcms->acpi_dev is still created. Check !acpi_enabled in
1694      * addition to cover this case.
1695      */
1696     if (!pcms->acpi_dev || !acpi_enabled) {
1697         error_setg(errp,
1698                    "memory hotplug is not enabled: missing acpi device or acpi disabled");
1699         return;
1700     }
1701
1702     if (is_nvdimm && !pcms->acpi_nvdimm_state.is_enabled) {
1703         error_setg(errp, "nvdimm is not enabled: missing 'nvdimm' in '-M'");
1704         return;
1705     }
1706
1707     pc_dimm_pre_plug(dev, MACHINE(hotplug_dev),
1708                      pcmc->enforce_aligned_dimm ? NULL : &legacy_align, errp);
1709 }
1710
1711 static void pc_memory_plug(HotplugHandler *hotplug_dev,
1712                            DeviceState *dev, Error **errp)
1713 {
1714     HotplugHandlerClass *hhc;
1715     Error *local_err = NULL;
1716     PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1717     bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM);
1718
1719     pc_dimm_plug(dev, MACHINE(pcms), &local_err);
1720     if (local_err) {
1721         goto out;
1722     }
1723
1724     if (is_nvdimm) {
1725         nvdimm_plug(&pcms->acpi_nvdimm_state);
1726     }
1727
1728     hhc = HOTPLUG_HANDLER_GET_CLASS(pcms->acpi_dev);
1729     hhc->plug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &error_abort);
1730 out:
1731     error_propagate(errp, local_err);
1732 }
1733
1734 static void pc_memory_unplug_request(HotplugHandler *hotplug_dev,
1735                                      DeviceState *dev, Error **errp)
1736 {
1737     HotplugHandlerClass *hhc;
1738     Error *local_err = NULL;
1739     PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1740
1741     /*
1742      * When -no-acpi is used with Q35 machine type, no ACPI is built,
1743      * but pcms->acpi_dev is still created. Check !acpi_enabled in
1744      * addition to cover this case.
1745      */
1746     if (!pcms->acpi_dev || !acpi_enabled) {
1747         error_setg(&local_err,
1748                    "memory hotplug is not enabled: missing acpi device or acpi disabled");
1749         goto out;
1750     }
1751
1752     if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) {
1753         error_setg(&local_err,
1754                    "nvdimm device hot unplug is not supported yet.");
1755         goto out;
1756     }
1757
1758     hhc = HOTPLUG_HANDLER_GET_CLASS(pcms->acpi_dev);
1759     hhc->unplug_request(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err);
1760
1761 out:
1762     error_propagate(errp, local_err);
1763 }
1764
1765 static void pc_memory_unplug(HotplugHandler *hotplug_dev,
1766                              DeviceState *dev, Error **errp)
1767 {
1768     PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1769     HotplugHandlerClass *hhc;
1770     Error *local_err = NULL;
1771
1772     hhc = HOTPLUG_HANDLER_GET_CLASS(pcms->acpi_dev);
1773     hhc->unplug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err);
1774
1775     if (local_err) {
1776         goto out;
1777     }
1778
1779     pc_dimm_unplug(dev, MACHINE(pcms));
1780     object_unparent(OBJECT(dev));
1781
1782  out:
1783     error_propagate(errp, local_err);
1784 }
1785
1786 static int pc_apic_cmp(const void *a, const void *b)
1787 {
1788    CPUArchId *apic_a = (CPUArchId *)a;
1789    CPUArchId *apic_b = (CPUArchId *)b;
1790
1791    return apic_a->arch_id - apic_b->arch_id;
1792 }
1793
1794 /* returns pointer to CPUArchId descriptor that matches CPU's apic_id
1795  * in ms->possible_cpus->cpus, if ms->possible_cpus->cpus has no
1796  * entry corresponding to CPU's apic_id returns NULL.
1797  */
1798 static CPUArchId *pc_find_cpu_slot(MachineState *ms, uint32_t id, int *idx)
1799 {
1800     CPUArchId apic_id, *found_cpu;
1801
1802     apic_id.arch_id = id;
1803     found_cpu = bsearch(&apic_id, ms->possible_cpus->cpus,
1804         ms->possible_cpus->len, sizeof(*ms->possible_cpus->cpus),
1805         pc_apic_cmp);
1806     if (found_cpu && idx) {
1807         *idx = found_cpu - ms->possible_cpus->cpus;
1808     }
1809     return found_cpu;
1810 }
1811
1812 static void pc_cpu_plug(HotplugHandler *hotplug_dev,
1813                         DeviceState *dev, Error **errp)
1814 {
1815     CPUArchId *found_cpu;
1816     HotplugHandlerClass *hhc;
1817     Error *local_err = NULL;
1818     X86CPU *cpu = X86_CPU(dev);
1819     PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1820
1821     if (pcms->acpi_dev) {
1822         hhc = HOTPLUG_HANDLER_GET_CLASS(pcms->acpi_dev);
1823         hhc->plug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err);
1824         if (local_err) {
1825             goto out;
1826         }
1827     }
1828
1829     /* increment the number of CPUs */
1830     pcms->boot_cpus++;
1831     if (pcms->rtc) {
1832         rtc_set_cpus_count(pcms->rtc, pcms->boot_cpus);
1833     }
1834     if (pcms->fw_cfg) {
1835         fw_cfg_modify_i16(pcms->fw_cfg, FW_CFG_NB_CPUS, pcms->boot_cpus);
1836     }
1837
1838     found_cpu = pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, NULL);
1839     found_cpu->cpu = OBJECT(dev);
1840 out:
1841     error_propagate(errp, local_err);
1842 }
1843 static void pc_cpu_unplug_request_cb(HotplugHandler *hotplug_dev,
1844                                      DeviceState *dev, Error **errp)
1845 {
1846     int idx = -1;
1847     HotplugHandlerClass *hhc;
1848     Error *local_err = NULL;
1849     X86CPU *cpu = X86_CPU(dev);
1850     PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1851
1852     if (!pcms->acpi_dev) {
1853         error_setg(&local_err, "CPU hot unplug not supported without ACPI");
1854         goto out;
1855     }
1856
1857     pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, &idx);
1858     assert(idx != -1);
1859     if (idx == 0) {
1860         error_setg(&local_err, "Boot CPU is unpluggable");
1861         goto out;
1862     }
1863
1864     hhc = HOTPLUG_HANDLER_GET_CLASS(pcms->acpi_dev);
1865     hhc->unplug_request(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err);
1866
1867     if (local_err) {
1868         goto out;
1869     }
1870
1871  out:
1872     error_propagate(errp, local_err);
1873
1874 }
1875
1876 static void pc_cpu_unplug_cb(HotplugHandler *hotplug_dev,
1877                              DeviceState *dev, Error **errp)
1878 {
1879     CPUArchId *found_cpu;
1880     HotplugHandlerClass *hhc;
1881     Error *local_err = NULL;
1882     X86CPU *cpu = X86_CPU(dev);
1883     PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1884
1885     hhc = HOTPLUG_HANDLER_GET_CLASS(pcms->acpi_dev);
1886     hhc->unplug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err);
1887
1888     if (local_err) {
1889         goto out;
1890     }
1891
1892     found_cpu = pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, NULL);
1893     found_cpu->cpu = NULL;
1894     object_unparent(OBJECT(dev));
1895
1896     /* decrement the number of CPUs */
1897     pcms->boot_cpus--;
1898     /* Update the number of CPUs in CMOS */
1899     rtc_set_cpus_count(pcms->rtc, pcms->boot_cpus);
1900     fw_cfg_modify_i16(pcms->fw_cfg, FW_CFG_NB_CPUS, pcms->boot_cpus);
1901  out:
1902     error_propagate(errp, local_err);
1903 }
1904
1905 static void pc_cpu_pre_plug(HotplugHandler *hotplug_dev,
1906                             DeviceState *dev, Error **errp)
1907 {
1908     int idx;
1909     CPUState *cs;
1910     CPUArchId *cpu_slot;
1911     X86CPUTopoInfo topo;
1912     X86CPU *cpu = X86_CPU(dev);
1913     MachineState *ms = MACHINE(hotplug_dev);
1914     PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1915
1916     if(!object_dynamic_cast(OBJECT(cpu), ms->cpu_type)) {
1917         error_setg(errp, "Invalid CPU type, expected cpu type: '%s'",
1918                    ms->cpu_type);
1919         return;
1920     }
1921
1922     /* if APIC ID is not set, set it based on socket/core/thread properties */
1923     if (cpu->apic_id == UNASSIGNED_APIC_ID) {
1924         int max_socket = (max_cpus - 1) / smp_threads / smp_cores;
1925
1926         if (cpu->socket_id < 0) {
1927             error_setg(errp, "CPU socket-id is not set");
1928             return;
1929         } else if (cpu->socket_id > max_socket) {
1930             error_setg(errp, "Invalid CPU socket-id: %u must be in range 0:%u",
1931                        cpu->socket_id, max_socket);
1932             return;
1933         }
1934         if (cpu->core_id < 0) {
1935             error_setg(errp, "CPU core-id is not set");
1936             return;
1937         } else if (cpu->core_id > (smp_cores - 1)) {
1938             error_setg(errp, "Invalid CPU core-id: %u must be in range 0:%u",
1939                        cpu->core_id, smp_cores - 1);
1940             return;
1941         }
1942         if (cpu->thread_id < 0) {
1943             error_setg(errp, "CPU thread-id is not set");
1944             return;
1945         } else if (cpu->thread_id > (smp_threads - 1)) {
1946             error_setg(errp, "Invalid CPU thread-id: %u must be in range 0:%u",
1947                        cpu->thread_id, smp_threads - 1);
1948             return;
1949         }
1950
1951         topo.pkg_id = cpu->socket_id;
1952         topo.core_id = cpu->core_id;
1953         topo.smt_id = cpu->thread_id;
1954         cpu->apic_id = apicid_from_topo_ids(smp_cores, smp_threads, &topo);
1955     }
1956
1957     cpu_slot = pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, &idx);
1958     if (!cpu_slot) {
1959         MachineState *ms = MACHINE(pcms);
1960
1961         x86_topo_ids_from_apicid(cpu->apic_id, smp_cores, smp_threads, &topo);
1962         error_setg(errp, "Invalid CPU [socket: %u, core: %u, thread: %u] with"
1963                   " APIC ID %" PRIu32 ", valid index range 0:%d",
1964                    topo.pkg_id, topo.core_id, topo.smt_id, cpu->apic_id,
1965                    ms->possible_cpus->len - 1);
1966         return;
1967     }
1968
1969     if (cpu_slot->cpu) {
1970         error_setg(errp, "CPU[%d] with APIC ID %" PRIu32 " exists",
1971                    idx, cpu->apic_id);
1972         return;
1973     }
1974
1975     /* if 'address' properties socket-id/core-id/thread-id are not set, set them
1976      * so that machine_query_hotpluggable_cpus would show correct values
1977      */
1978     /* TODO: move socket_id/core_id/thread_id checks into x86_cpu_realizefn()
1979      * once -smp refactoring is complete and there will be CPU private
1980      * CPUState::nr_cores and CPUState::nr_threads fields instead of globals */
1981     x86_topo_ids_from_apicid(cpu->apic_id, smp_cores, smp_threads, &topo);
1982     if (cpu->socket_id != -1 && cpu->socket_id != topo.pkg_id) {
1983         error_setg(errp, "property socket-id: %u doesn't match set apic-id:"
1984             " 0x%x (socket-id: %u)", cpu->socket_id, cpu->apic_id, topo.pkg_id);
1985         return;
1986     }
1987     cpu->socket_id = topo.pkg_id;
1988
1989     if (cpu->core_id != -1 && cpu->core_id != topo.core_id) {
1990         error_setg(errp, "property core-id: %u doesn't match set apic-id:"
1991             " 0x%x (core-id: %u)", cpu->core_id, cpu->apic_id, topo.core_id);
1992         return;
1993     }
1994     cpu->core_id = topo.core_id;
1995
1996     if (cpu->thread_id != -1 && cpu->thread_id != topo.smt_id) {
1997         error_setg(errp, "property thread-id: %u doesn't match set apic-id:"
1998             " 0x%x (thread-id: %u)", cpu->thread_id, cpu->apic_id, topo.smt_id);
1999         return;
2000     }
2001     cpu->thread_id = topo.smt_id;
2002
2003     if (cpu->hyperv_vpindex && !kvm_hv_vpindex_settable()) {
2004         error_setg(errp, "kernel doesn't allow setting HyperV VP_INDEX");
2005         return;
2006     }
2007
2008     cs = CPU(cpu);
2009     cs->cpu_index = idx;
2010
2011     numa_cpu_pre_plug(cpu_slot, dev, errp);
2012 }
2013
2014 static void pc_machine_device_pre_plug_cb(HotplugHandler *hotplug_dev,
2015                                           DeviceState *dev, Error **errp)
2016 {
2017     if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
2018         pc_memory_pre_plug(hotplug_dev, dev, errp);
2019     } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
2020         pc_cpu_pre_plug(hotplug_dev, dev, errp);
2021     }
2022 }
2023
2024 static void pc_machine_device_plug_cb(HotplugHandler *hotplug_dev,
2025                                       DeviceState *dev, Error **errp)
2026 {
2027     if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
2028         pc_memory_plug(hotplug_dev, dev, errp);
2029     } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
2030         pc_cpu_plug(hotplug_dev, dev, errp);
2031     }
2032 }
2033
2034 static void pc_machine_device_unplug_request_cb(HotplugHandler *hotplug_dev,
2035                                                 DeviceState *dev, Error **errp)
2036 {
2037     if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
2038         pc_memory_unplug_request(hotplug_dev, dev, errp);
2039     } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
2040         pc_cpu_unplug_request_cb(hotplug_dev, dev, errp);
2041     } else {
2042         error_setg(errp, "acpi: device unplug request for not supported device"
2043                    " type: %s", object_get_typename(OBJECT(dev)));
2044     }
2045 }
2046
2047 static void pc_machine_device_unplug_cb(HotplugHandler *hotplug_dev,
2048                                         DeviceState *dev, Error **errp)
2049 {
2050     if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
2051         pc_memory_unplug(hotplug_dev, dev, errp);
2052     } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
2053         pc_cpu_unplug_cb(hotplug_dev, dev, errp);
2054     } else {
2055         error_setg(errp, "acpi: device unplug for not supported device"
2056                    " type: %s", object_get_typename(OBJECT(dev)));
2057     }
2058 }
2059
2060 static HotplugHandler *pc_get_hotpug_handler(MachineState *machine,
2061                                              DeviceState *dev)
2062 {
2063     if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) ||
2064         object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
2065         return HOTPLUG_HANDLER(machine);
2066     }
2067
2068     return NULL;
2069 }
2070
2071 static void
2072 pc_machine_get_device_memory_region_size(Object *obj, Visitor *v,
2073                                          const char *name, void *opaque,
2074                                          Error **errp)
2075 {
2076     MachineState *ms = MACHINE(obj);
2077     int64_t value = memory_region_size(&ms->device_memory->mr);
2078
2079     visit_type_int(v, name, &value, errp);
2080 }
2081
2082 static void pc_machine_get_max_ram_below_4g(Object *obj, Visitor *v,
2083                                             const char *name, void *opaque,
2084                                             Error **errp)
2085 {
2086     PCMachineState *pcms = PC_MACHINE(obj);
2087     uint64_t value = pcms->max_ram_below_4g;
2088
2089     visit_type_size(v, name, &value, errp);
2090 }
2091
2092 static void pc_machine_set_max_ram_below_4g(Object *obj, Visitor *v,
2093                                             const char *name, void *opaque,
2094                                             Error **errp)
2095 {
2096     PCMachineState *pcms = PC_MACHINE(obj);
2097     Error *error = NULL;
2098     uint64_t value;
2099
2100     visit_type_size(v, name, &value, &error);
2101     if (error) {
2102         error_propagate(errp, error);
2103         return;
2104     }
2105     if (value > 4 * GiB) {
2106         error_setg(&error,
2107                    "Machine option 'max-ram-below-4g=%"PRIu64
2108                    "' expects size less than or equal to 4G", value);
2109         error_propagate(errp, error);
2110         return;
2111     }
2112
2113     if (value < 1 * MiB) {
2114         warn_report("Only %" PRIu64 " bytes of RAM below the 4GiB boundary,"
2115                     "BIOS may not work with less than 1MiB", value);
2116     }
2117
2118     pcms->max_ram_below_4g = value;
2119 }
2120
2121 static void pc_machine_get_vmport(Object *obj, Visitor *v, const char *name,
2122                                   void *opaque, Error **errp)
2123 {
2124     PCMachineState *pcms = PC_MACHINE(obj);
2125     OnOffAuto vmport = pcms->vmport;
2126
2127     visit_type_OnOffAuto(v, name, &vmport, errp);
2128 }
2129
2130 static void pc_machine_set_vmport(Object *obj, Visitor *v, const char *name,
2131                                   void *opaque, Error **errp)
2132 {
2133     PCMachineState *pcms = PC_MACHINE(obj);
2134
2135     visit_type_OnOffAuto(v, name, &pcms->vmport, errp);
2136 }
2137
2138 bool pc_machine_is_smm_enabled(PCMachineState *pcms)
2139 {
2140     bool smm_available = false;
2141
2142     if (pcms->smm == ON_OFF_AUTO_OFF) {
2143         return false;
2144     }
2145
2146     if (tcg_enabled() || qtest_enabled()) {
2147         smm_available = true;
2148     } else if (kvm_enabled()) {
2149         smm_available = kvm_has_smm();
2150     }
2151
2152     if (smm_available) {
2153         return true;
2154     }
2155
2156     if (pcms->smm == ON_OFF_AUTO_ON) {
2157         error_report("System Management Mode not supported by this hypervisor.");
2158         exit(1);
2159     }
2160     return false;
2161 }
2162
2163 static void pc_machine_get_smm(Object *obj, Visitor *v, const char *name,
2164                                void *opaque, Error **errp)
2165 {
2166     PCMachineState *pcms = PC_MACHINE(obj);
2167     OnOffAuto smm = pcms->smm;
2168
2169     visit_type_OnOffAuto(v, name, &smm, errp);
2170 }
2171
2172 static void pc_machine_set_smm(Object *obj, Visitor *v, const char *name,
2173                                void *opaque, Error **errp)
2174 {
2175     PCMachineState *pcms = PC_MACHINE(obj);
2176
2177     visit_type_OnOffAuto(v, name, &pcms->smm, errp);
2178 }
2179
2180 static bool pc_machine_get_nvdimm(Object *obj, Error **errp)
2181 {
2182     PCMachineState *pcms = PC_MACHINE(obj);
2183
2184     return pcms->acpi_nvdimm_state.is_enabled;
2185 }
2186
2187 static void pc_machine_set_nvdimm(Object *obj, bool value, Error **errp)
2188 {
2189     PCMachineState *pcms = PC_MACHINE(obj);
2190
2191     pcms->acpi_nvdimm_state.is_enabled = value;
2192 }
2193
2194 static char *pc_machine_get_nvdimm_persistence(Object *obj, Error **errp)
2195 {
2196     PCMachineState *pcms = PC_MACHINE(obj);
2197
2198     return g_strdup(pcms->acpi_nvdimm_state.persistence_string);
2199 }
2200
2201 static void pc_machine_set_nvdimm_persistence(Object *obj, const char *value,
2202                                                Error **errp)
2203 {
2204     PCMachineState *pcms = PC_MACHINE(obj);
2205     AcpiNVDIMMState *nvdimm_state = &pcms->acpi_nvdimm_state;
2206
2207     if (strcmp(value, "cpu") == 0)
2208         nvdimm_state->persistence = 3;
2209     else if (strcmp(value, "mem-ctrl") == 0)
2210         nvdimm_state->persistence = 2;
2211     else {
2212         error_report("-machine nvdimm-persistence=%s: unsupported option", value);
2213         exit(EXIT_FAILURE);
2214     }
2215
2216     g_free(nvdimm_state->persistence_string);
2217     nvdimm_state->persistence_string = g_strdup(value);
2218 }
2219
2220 static bool pc_machine_get_smbus(Object *obj, Error **errp)
2221 {
2222     PCMachineState *pcms = PC_MACHINE(obj);
2223
2224     return pcms->smbus;
2225 }
2226
2227 static void pc_machine_set_smbus(Object *obj, bool value, Error **errp)
2228 {
2229     PCMachineState *pcms = PC_MACHINE(obj);
2230
2231     pcms->smbus = value;
2232 }
2233
2234 static bool pc_machine_get_sata(Object *obj, Error **errp)
2235 {
2236     PCMachineState *pcms = PC_MACHINE(obj);
2237
2238     return pcms->sata;
2239 }
2240
2241 static void pc_machine_set_sata(Object *obj, bool value, Error **errp)
2242 {
2243     PCMachineState *pcms = PC_MACHINE(obj);
2244
2245     pcms->sata = value;
2246 }
2247
2248 static bool pc_machine_get_pit(Object *obj, Error **errp)
2249 {
2250     PCMachineState *pcms = PC_MACHINE(obj);
2251
2252     return pcms->pit;
2253 }
2254
2255 static void pc_machine_set_pit(Object *obj, bool value, Error **errp)
2256 {
2257     PCMachineState *pcms = PC_MACHINE(obj);
2258
2259     pcms->pit = value;
2260 }
2261
2262 static void pc_machine_initfn(Object *obj)
2263 {
2264     PCMachineState *pcms = PC_MACHINE(obj);
2265
2266     pcms->max_ram_below_4g = 0; /* use default */
2267     pcms->smm = ON_OFF_AUTO_AUTO;
2268     pcms->vmport = ON_OFF_AUTO_AUTO;
2269     /* nvdimm is disabled on default. */
2270     pcms->acpi_nvdimm_state.is_enabled = false;
2271     /* acpi build is enabled by default if machine supports it */
2272     pcms->acpi_build_enabled = PC_MACHINE_GET_CLASS(pcms)->has_acpi_build;
2273     pcms->smbus = true;
2274     pcms->sata = true;
2275     pcms->pit = true;
2276 }
2277
2278 static void pc_machine_reset(void)
2279 {
2280     CPUState *cs;
2281     X86CPU *cpu;
2282
2283     qemu_devices_reset();
2284
2285     /* Reset APIC after devices have been reset to cancel
2286      * any changes that qemu_devices_reset() might have done.
2287      */
2288     CPU_FOREACH(cs) {
2289         cpu = X86_CPU(cs);
2290
2291         if (cpu->apic_state) {
2292             device_reset(cpu->apic_state);
2293         }
2294     }
2295 }
2296
2297 static CpuInstanceProperties
2298 pc_cpu_index_to_props(MachineState *ms, unsigned cpu_index)
2299 {
2300     MachineClass *mc = MACHINE_GET_CLASS(ms);
2301     const CPUArchIdList *possible_cpus = mc->possible_cpu_arch_ids(ms);
2302
2303     assert(cpu_index < possible_cpus->len);
2304     return possible_cpus->cpus[cpu_index].props;
2305 }
2306
2307 static int64_t pc_get_default_cpu_node_id(const MachineState *ms, int idx)
2308 {
2309    X86CPUTopoInfo topo;
2310
2311    assert(idx < ms->possible_cpus->len);
2312    x86_topo_ids_from_apicid(ms->possible_cpus->cpus[idx].arch_id,
2313                             smp_cores, smp_threads, &topo);
2314    return topo.pkg_id % nb_numa_nodes;
2315 }
2316
2317 static const CPUArchIdList *pc_possible_cpu_arch_ids(MachineState *ms)
2318 {
2319     int i;
2320
2321     if (ms->possible_cpus) {
2322         /*
2323          * make sure that max_cpus hasn't changed since the first use, i.e.
2324          * -smp hasn't been parsed after it
2325         */
2326         assert(ms->possible_cpus->len == max_cpus);
2327         return ms->possible_cpus;
2328     }
2329
2330     ms->possible_cpus = g_malloc0(sizeof(CPUArchIdList) +
2331                                   sizeof(CPUArchId) * max_cpus);
2332     ms->possible_cpus->len = max_cpus;
2333     for (i = 0; i < ms->possible_cpus->len; i++) {
2334         X86CPUTopoInfo topo;
2335
2336         ms->possible_cpus->cpus[i].type = ms->cpu_type;
2337         ms->possible_cpus->cpus[i].vcpus_count = 1;
2338         ms->possible_cpus->cpus[i].arch_id = x86_cpu_apic_id_from_index(i);
2339         x86_topo_ids_from_apicid(ms->possible_cpus->cpus[i].arch_id,
2340                                  smp_cores, smp_threads, &topo);
2341         ms->possible_cpus->cpus[i].props.has_socket_id = true;
2342         ms->possible_cpus->cpus[i].props.socket_id = topo.pkg_id;
2343         ms->possible_cpus->cpus[i].props.has_core_id = true;
2344         ms->possible_cpus->cpus[i].props.core_id = topo.core_id;
2345         ms->possible_cpus->cpus[i].props.has_thread_id = true;
2346         ms->possible_cpus->cpus[i].props.thread_id = topo.smt_id;
2347     }
2348     return ms->possible_cpus;
2349 }
2350
2351 static void x86_nmi(NMIState *n, int cpu_index, Error **errp)
2352 {
2353     /* cpu index isn't used */
2354     CPUState *cs;
2355
2356     CPU_FOREACH(cs) {
2357         X86CPU *cpu = X86_CPU(cs);
2358
2359         if (!cpu->apic_state) {
2360             cpu_interrupt(cs, CPU_INTERRUPT_NMI);
2361         } else {
2362             apic_deliver_nmi(cpu->apic_state);
2363         }
2364     }
2365 }
2366
2367 static void pc_machine_class_init(ObjectClass *oc, void *data)
2368 {
2369     MachineClass *mc = MACHINE_CLASS(oc);
2370     PCMachineClass *pcmc = PC_MACHINE_CLASS(oc);
2371     HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc);
2372     NMIClass *nc = NMI_CLASS(oc);
2373
2374     pcmc->pci_enabled = true;
2375     pcmc->has_acpi_build = true;
2376     pcmc->rsdp_in_ram = true;
2377     pcmc->smbios_defaults = true;
2378     pcmc->smbios_uuid_encoded = true;
2379     pcmc->gigabyte_align = true;
2380     pcmc->has_reserved_memory = true;
2381     pcmc->kvmclock_enabled = true;
2382     pcmc->enforce_aligned_dimm = true;
2383     /* BIOS ACPI tables: 128K. Other BIOS datastructures: less than 4K reported
2384      * to be used at the moment, 32K should be enough for a while.  */
2385     pcmc->acpi_data_size = 0x20000 + 0x8000;
2386     pcmc->save_tsc_khz = true;
2387     pcmc->linuxboot_dma_enabled = true;
2388     assert(!mc->get_hotplug_handler);
2389     mc->get_hotplug_handler = pc_get_hotpug_handler;
2390     mc->cpu_index_to_instance_props = pc_cpu_index_to_props;
2391     mc->get_default_cpu_node_id = pc_get_default_cpu_node_id;
2392     mc->possible_cpu_arch_ids = pc_possible_cpu_arch_ids;
2393     mc->auto_enable_numa_with_memhp = true;
2394     mc->has_hotpluggable_cpus = true;
2395     mc->default_boot_order = "cad";
2396     mc->hot_add_cpu = pc_hot_add_cpu;
2397     mc->block_default_type = IF_IDE;
2398     mc->max_cpus = 255;
2399     mc->reset = pc_machine_reset;
2400     hc->pre_plug = pc_machine_device_pre_plug_cb;
2401     hc->plug = pc_machine_device_plug_cb;
2402     hc->unplug_request = pc_machine_device_unplug_request_cb;
2403     hc->unplug = pc_machine_device_unplug_cb;
2404     nc->nmi_monitor_handler = x86_nmi;
2405     mc->default_cpu_type = TARGET_DEFAULT_CPU_TYPE;
2406
2407     object_class_property_add(oc, PC_MACHINE_DEVMEM_REGION_SIZE, "int",
2408         pc_machine_get_device_memory_region_size, NULL,
2409         NULL, NULL, &error_abort);
2410
2411     object_class_property_add(oc, PC_MACHINE_MAX_RAM_BELOW_4G, "size",
2412         pc_machine_get_max_ram_below_4g, pc_machine_set_max_ram_below_4g,
2413         NULL, NULL, &error_abort);
2414
2415     object_class_property_set_description(oc, PC_MACHINE_MAX_RAM_BELOW_4G,
2416         "Maximum ram below the 4G boundary (32bit boundary)", &error_abort);
2417
2418     object_class_property_add(oc, PC_MACHINE_SMM, "OnOffAuto",
2419         pc_machine_get_smm, pc_machine_set_smm,
2420         NULL, NULL, &error_abort);
2421     object_class_property_set_description(oc, PC_MACHINE_SMM,
2422         "Enable SMM (pc & q35)", &error_abort);
2423
2424     object_class_property_add(oc, PC_MACHINE_VMPORT, "OnOffAuto",
2425         pc_machine_get_vmport, pc_machine_set_vmport,
2426         NULL, NULL, &error_abort);
2427     object_class_property_set_description(oc, PC_MACHINE_VMPORT,
2428         "Enable vmport (pc & q35)", &error_abort);
2429
2430     object_class_property_add_bool(oc, PC_MACHINE_NVDIMM,
2431         pc_machine_get_nvdimm, pc_machine_set_nvdimm, &error_abort);
2432
2433     object_class_property_add_str(oc, PC_MACHINE_NVDIMM_PERSIST,
2434         pc_machine_get_nvdimm_persistence,
2435         pc_machine_set_nvdimm_persistence, &error_abort);
2436
2437     object_class_property_add_bool(oc, PC_MACHINE_SMBUS,
2438         pc_machine_get_smbus, pc_machine_set_smbus, &error_abort);
2439
2440     object_class_property_add_bool(oc, PC_MACHINE_SATA,
2441         pc_machine_get_sata, pc_machine_set_sata, &error_abort);
2442
2443     object_class_property_add_bool(oc, PC_MACHINE_PIT,
2444         pc_machine_get_pit, pc_machine_set_pit, &error_abort);
2445 }
2446
2447 static const TypeInfo pc_machine_info = {
2448     .name = TYPE_PC_MACHINE,
2449     .parent = TYPE_MACHINE,
2450     .abstract = true,
2451     .instance_size = sizeof(PCMachineState),
2452     .instance_init = pc_machine_initfn,
2453     .class_size = sizeof(PCMachineClass),
2454     .class_init = pc_machine_class_init,
2455     .interfaces = (InterfaceInfo[]) {
2456          { TYPE_HOTPLUG_HANDLER },
2457          { TYPE_NMI },
2458          { }
2459     },
2460 };
2461
2462 static void pc_machine_register_types(void)
2463 {
2464     type_register_static(&pc_machine_info);
2465 }
2466
2467 type_init(pc_machine_register_types)