Merge tag 'pull-loongarch-20241016' of https://gitlab.com/gaosong/qemu into staging
[qemu/armbru.git] / bsd-user / riscv / target_arch_cpu.c
blob44e25d2ddf5d6e8820d8dae1451cd8dcc1741e78
1 /*
2 * RISC-V CPU related code
4 * Copyright (c) 2019 Mark Corbin
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, see <http://www.gnu.org/licenses/>.
19 #include "qemu/osdep.h"
21 #include "target_arch.h"
23 #define TP_OFFSET 16
25 /* Compare with cpu_set_user_tls() in riscv/riscv/vm_machdep.c */
26 void target_cpu_set_tls(CPURISCVState *env, target_ulong newtls)
28 env->gpr[xTP] = newtls + TP_OFFSET;