Merge tag 'pull-loongarch-20241016' of https://gitlab.com/gaosong/qemu into staging
[qemu/armbru.git] / bsd-user / riscv / target_arch_elf.h
blob4eb915e61ecbedf32181e46ba5b4c472e67f4d52
1 /*
2 * RISC-V ELF definitions
4 * Copyright (c) 2019 Mark Corbin
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, see <http://www.gnu.org/licenses/>.
20 #ifndef TARGET_ARCH_ELF_H
21 #define TARGET_ARCH_ELF_H
23 #define elf_check_arch(x) ((x) == EM_RISCV)
24 #define ELF_START_MMAP 0x80000000
25 #define ELF_ET_DYN_LOAD_ADDR 0x100000
26 #define ELF_CLASS ELFCLASS64
28 #define ELF_DATA ELFDATA2LSB
29 #define ELF_ARCH EM_RISCV
31 #define ELF_HWCAP get_elf_hwcap()
32 static uint32_t get_elf_hwcap(void)
34 RISCVCPU *cpu = RISCV_CPU(thread_cpu);
36 return cpu->env.misa_ext_mask;
39 #define USE_ELF_CORE_DUMP
40 #define ELF_EXEC_PAGESIZE 4096
42 #endif /* TARGET_ARCH_ELF_H */