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Merge tag 'pull-loongarch-20241016' of https://gitlab.com/gaosong/qemu into staging
[qemu/armbru.git] / hw / arm / aspeed.c
blobcf0c6c580b2a4a2909cf836b95ca8e24da3752f8
1 /*
2 * OpenPOWER Palmetto BMC
3 *
4 * Andrew Jeffery <andrew@aj.id.au>
5 *
6 * Copyright 2016 IBM Corp.
7 *
8 * This code is licensed under the GPL version 2 or later. See
9 * the COPYING file in the top-level directory.
10 */
11
12 #include "qemu/osdep.h"
13 #include "qapi/error.h"
14 #include "hw/arm/boot.h"
15 #include "hw/arm/aspeed.h"
16 #include "hw/arm/aspeed_soc.h"
17 #include "hw/arm/aspeed_eeprom.h"
18 #include "hw/block/flash.h"
19 #include "hw/i2c/i2c_mux_pca954x.h"
20 #include "hw/i2c/smbus_eeprom.h"
21 #include "hw/gpio/pca9552.h"
22 #include "hw/nvram/eeprom_at24c.h"
23 #include "hw/sensor/tmp105.h"
24 #include "hw/misc/led.h"
25 #include "hw/qdev-properties.h"
26 #include "sysemu/block-backend.h"
27 #include "sysemu/reset.h"
28 #include "hw/loader.h"
29 #include "qemu/error-report.h"
30 #include "qemu/units.h"
31 #include "hw/qdev-clock.h"
32 #include "sysemu/sysemu.h"
33
34 static struct arm_boot_info aspeed_board_binfo = {
35 .board_id = -1, /* device-tree-only board */
36 };
37
38 struct AspeedMachineState {
39 /* Private */
40 MachineState parent_obj;
41 /* Public */
42
43 AspeedSoCState *soc;
44 MemoryRegion boot_rom;
45 bool mmio_exec;
46 uint32_t uart_chosen;
47 char *fmc_model;
48 char *spi_model;
49 uint32_t hw_strap1;
50 };
51
52 /* On 32-bit hosts, lower RAM to 1G because of the 2047 MB limit */
53 #if HOST_LONG_BITS == 32
54 #define ASPEED_RAM_SIZE(sz) MIN((sz), 1 * GiB)
55 #else
56 #define ASPEED_RAM_SIZE(sz) (sz)
57 #endif
58
59 /* Palmetto hardware value: 0x120CE416 */
60 #define PALMETTO_BMC_HW_STRAP1 ( \
61 SCU_AST2400_HW_STRAP_DRAM_SIZE(DRAM_SIZE_256MB) | \
62 SCU_AST2400_HW_STRAP_DRAM_CONFIG(2 /* DDR3 with CL=6, CWL=5 */) | \
63 SCU_AST2400_HW_STRAP_ACPI_DIS | \
64 SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(AST2400_CLK_48M_IN) | \
65 SCU_HW_STRAP_VGA_CLASS_CODE | \
66 SCU_HW_STRAP_LPC_RESET_PIN | \
67 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_M_S_EN) | \
68 SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(AST2400_CPU_AHB_RATIO_2_1) | \
69 SCU_HW_STRAP_SPI_WIDTH | \
70 SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \
71 SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT))
72
73 /* TODO: Find the actual hardware value */
74 #define SUPERMICROX11_BMC_HW_STRAP1 ( \
75 SCU_AST2400_HW_STRAP_DRAM_SIZE(DRAM_SIZE_128MB) | \
76 SCU_AST2400_HW_STRAP_DRAM_CONFIG(2) | \
77 SCU_AST2400_HW_STRAP_ACPI_DIS | \
78 SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(AST2400_CLK_48M_IN) | \
79 SCU_HW_STRAP_VGA_CLASS_CODE | \
80 SCU_HW_STRAP_LPC_RESET_PIN | \
81 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_M_S_EN) | \
82 SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(AST2400_CPU_AHB_RATIO_2_1) | \
83 SCU_HW_STRAP_SPI_WIDTH | \
84 SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \
85 SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT))
86
87 /* TODO: Find the actual hardware value */
88 #define SUPERMICRO_X11SPI_BMC_HW_STRAP1 ( \
89 AST2500_HW_STRAP1_DEFAULTS | \
90 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \
91 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \
92 SCU_AST2500_HW_STRAP_UART_DEBUG | \
93 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \
94 SCU_HW_STRAP_SPI_WIDTH | \
95 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_M_S_EN))
96
97 /* AST2500 evb hardware value: 0xF100C2E6 */
98 #define AST2500_EVB_HW_STRAP1 (( \
99 AST2500_HW_STRAP1_DEFAULTS | \
100 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \
101 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \
102 SCU_AST2500_HW_STRAP_UART_DEBUG | \
103 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \
104 SCU_HW_STRAP_MAC1_RGMII | \
105 SCU_HW_STRAP_MAC0_RGMII) & \
106 ~SCU_HW_STRAP_2ND_BOOT_WDT)
107
108 /* Romulus hardware value: 0xF10AD206 */
109 #define ROMULUS_BMC_HW_STRAP1 ( \
110 AST2500_HW_STRAP1_DEFAULTS | \
111 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \
112 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \
113 SCU_AST2500_HW_STRAP_UART_DEBUG | \
114 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \
115 SCU_AST2500_HW_STRAP_ACPI_ENABLE | \
116 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER))
117
118 /* Sonorapass hardware value: 0xF100D216 */
119 #define SONORAPASS_BMC_HW_STRAP1 ( \
120 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \
121 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \
122 SCU_AST2500_HW_STRAP_UART_DEBUG | \
123 SCU_AST2500_HW_STRAP_RESERVED28 | \
124 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \
125 SCU_HW_STRAP_VGA_CLASS_CODE | \
126 SCU_HW_STRAP_LPC_RESET_PIN | \
127 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER) | \
128 SCU_AST2500_HW_STRAP_SET_AXI_AHB_RATIO(AXI_AHB_RATIO_2_1) | \
129 SCU_HW_STRAP_VGA_BIOS_ROM | \
130 SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \
131 SCU_AST2500_HW_STRAP_RESERVED1)
132
133 #define G220A_BMC_HW_STRAP1 ( \
134 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \
135 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \
136 SCU_AST2500_HW_STRAP_UART_DEBUG | \
137 SCU_AST2500_HW_STRAP_RESERVED28 | \
138 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \
139 SCU_HW_STRAP_2ND_BOOT_WDT | \
140 SCU_HW_STRAP_VGA_CLASS_CODE | \
141 SCU_HW_STRAP_LPC_RESET_PIN | \
142 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER) | \
143 SCU_AST2500_HW_STRAP_SET_AXI_AHB_RATIO(AXI_AHB_RATIO_2_1) | \
144 SCU_HW_STRAP_VGA_SIZE_SET(VGA_64M_DRAM) | \
145 SCU_AST2500_HW_STRAP_RESERVED1)
146
147 /* FP5280G2 hardware value: 0XF100D286 */
148 #define FP5280G2_BMC_HW_STRAP1 ( \
149 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \
150 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \
151 SCU_AST2500_HW_STRAP_UART_DEBUG | \
152 SCU_AST2500_HW_STRAP_RESERVED28 | \
153 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \
154 SCU_HW_STRAP_VGA_CLASS_CODE | \
155 SCU_HW_STRAP_LPC_RESET_PIN | \
156 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER) | \
157 SCU_AST2500_HW_STRAP_SET_AXI_AHB_RATIO(AXI_AHB_RATIO_2_1) | \
158 SCU_HW_STRAP_MAC1_RGMII | \
159 SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \
160 SCU_AST2500_HW_STRAP_RESERVED1)
161
162 /* Witherspoon hardware value: 0xF10AD216 (but use romulus definition) */
163 #define WITHERSPOON_BMC_HW_STRAP1 ROMULUS_BMC_HW_STRAP1
164
165 /* Quanta-Q71l hardware value */
166 #define QUANTA_Q71L_BMC_HW_STRAP1 ( \
167 SCU_AST2400_HW_STRAP_DRAM_SIZE(DRAM_SIZE_128MB) | \
168 SCU_AST2400_HW_STRAP_DRAM_CONFIG(2/* DDR3 with CL=6, CWL=5 */) | \
169 SCU_AST2400_HW_STRAP_ACPI_DIS | \
170 SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(AST2400_CLK_24M_IN) | \
171 SCU_HW_STRAP_VGA_CLASS_CODE | \
172 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_PASS_THROUGH) | \
173 SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(AST2400_CPU_AHB_RATIO_2_1) | \
174 SCU_HW_STRAP_SPI_WIDTH | \
175 SCU_HW_STRAP_VGA_SIZE_SET(VGA_8M_DRAM) | \
176 SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT))
177
178 /* AST2600 evb hardware value */
179 #define AST2600_EVB_HW_STRAP1 0x000000C0
180 #define AST2600_EVB_HW_STRAP2 0x00000003
181
182 #ifdef TARGET_AARCH64
183 /* AST2700 evb hardware value */
184 #define AST2700_EVB_HW_STRAP1 0x000000C0
185 #define AST2700_EVB_HW_STRAP2 0x00000003
186 #endif
187
188 /* Tacoma hardware value */
189 #define TACOMA_BMC_HW_STRAP1 0x00000000
190 #define TACOMA_BMC_HW_STRAP2 0x00000040
191
192 /* Rainier hardware value: (QEMU prototype) */
193 #define RAINIER_BMC_HW_STRAP1 (0x00422016 | SCU_AST2600_HW_STRAP_BOOT_SRC_EMMC)
194 #define RAINIER_BMC_HW_STRAP2 0x80000848
195
196 /* Fuji hardware value */
197 #define FUJI_BMC_HW_STRAP1 0x00000000
198 #define FUJI_BMC_HW_STRAP2 0x00000000
199
200 /* Bletchley hardware value */
201 /* TODO: Leave same as EVB for now. */
202 #define BLETCHLEY_BMC_HW_STRAP1 AST2600_EVB_HW_STRAP1
203 #define BLETCHLEY_BMC_HW_STRAP2 AST2600_EVB_HW_STRAP2
204
205 /* Qualcomm DC-SCM hardware value */
206 #define QCOM_DC_SCM_V1_BMC_HW_STRAP1 0x00000000
207 #define QCOM_DC_SCM_V1_BMC_HW_STRAP2 0x00000041
208
209 #define AST_SMP_MAILBOX_BASE 0x1e6e2180
210 #define AST_SMP_MBOX_FIELD_ENTRY (AST_SMP_MAILBOX_BASE + 0x0)
211 #define AST_SMP_MBOX_FIELD_GOSIGN (AST_SMP_MAILBOX_BASE + 0x4)
212 #define AST_SMP_MBOX_FIELD_READY (AST_SMP_MAILBOX_BASE + 0x8)
213 #define AST_SMP_MBOX_FIELD_POLLINSN (AST_SMP_MAILBOX_BASE + 0xc)
214 #define AST_SMP_MBOX_CODE (AST_SMP_MAILBOX_BASE + 0x10)
215 #define AST_SMP_MBOX_GOSIGN 0xabbaab00
216
217 static void aspeed_write_smpboot(ARMCPU *cpu,
218 const struct arm_boot_info *info)
219 {
220 AddressSpace *as = arm_boot_address_space(cpu, info);
221 static const ARMInsnFixup poll_mailbox_ready[] = {
222 /*
223 * r2 = per-cpu go sign value
224 * r1 = AST_SMP_MBOX_FIELD_ENTRY
225 * r0 = AST_SMP_MBOX_FIELD_GOSIGN
226 */
227 { 0xee100fb0 }, /* mrc p15, 0, r0, c0, c0, 5 */
228 { 0xe21000ff }, /* ands r0, r0, #255 */
229 { 0xe59f201c }, /* ldr r2, [pc, #28] */
230 { 0xe1822000 }, /* orr r2, r2, r0 */
231
232 { 0xe59f1018 }, /* ldr r1, [pc, #24] */
233 { 0xe59f0018 }, /* ldr r0, [pc, #24] */
234
235 { 0xe320f002 }, /* wfe */
236 { 0xe5904000 }, /* ldr r4, [r0] */
237 { 0xe1520004 }, /* cmp r2, r4 */
238 { 0x1afffffb }, /* bne <wfe> */
239 { 0xe591f000 }, /* ldr pc, [r1] */
240 { AST_SMP_MBOX_GOSIGN },
241 { AST_SMP_MBOX_FIELD_ENTRY },
242 { AST_SMP_MBOX_FIELD_GOSIGN },
243 { 0, FIXUP_TERMINATOR }
244 };
245 static const uint32_t fixupcontext[FIXUP_MAX] = { 0 };
246
247 arm_write_bootloader("aspeed.smpboot", as, info->smp_loader_start,
248 poll_mailbox_ready, fixupcontext);
249 }
250
251 static void aspeed_reset_secondary(ARMCPU *cpu,
252 const struct arm_boot_info *info)
253 {
254 AddressSpace *as = arm_boot_address_space(cpu, info);
255 CPUState *cs = CPU(cpu);
256
257 /* info->smp_bootreg_addr */
258 address_space_stl_notdirty(as, AST_SMP_MBOX_FIELD_GOSIGN, 0,
259 MEMTXATTRS_UNSPECIFIED, NULL);
260 cpu_set_pc(cs, info->smp_loader_start);
261 }
262
263 static void write_boot_rom(BlockBackend *blk, hwaddr addr, size_t rom_size,
264 Error **errp)
265 {
266 g_autofree void *storage = NULL;
267 int64_t size;
268
269 /*
270 * The block backend size should have already been 'validated' by
271 * the creation of the m25p80 object.
272 */
273 size = blk_getlength(blk);
274 if (size <= 0) {
275 error_setg(errp, "failed to get flash size");
276 return;
277 }
278
279 if (rom_size > size) {
280 rom_size = size;
281 }
282
283 storage = g_malloc0(rom_size);
284 if (blk_pread(blk, 0, rom_size, storage, 0) < 0) {
285 error_setg(errp, "failed to read the initial flash content");
286 return;
287 }
288
289 rom_add_blob_fixed("aspeed.boot_rom", storage, rom_size, addr);
290 }
291
292 /*
293 * Create a ROM and copy the flash contents at the expected address
294 * (0x0). Boots faster than execute-in-place.
295 */
296 static void aspeed_install_boot_rom(AspeedMachineState *bmc, BlockBackend *blk,
297 uint64_t rom_size)
298 {
299 AspeedSoCState *soc = bmc->soc;
300 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(soc);
301
302 memory_region_init_rom(&bmc->boot_rom, NULL, "aspeed.boot_rom", rom_size,
303 &error_abort);
304 memory_region_add_subregion_overlap(&soc->spi_boot_container, 0,
305 &bmc->boot_rom, 1);
306 write_boot_rom(blk, sc->memmap[ASPEED_DEV_SPI_BOOT],
307 rom_size, &error_abort);
308 }
309
310 void aspeed_board_init_flashes(AspeedSMCState *s, const char *flashtype,
311 unsigned int count, int unit0)
312 {
313 int i;
314
315 if (!flashtype) {
316 return;
317 }
318
319 for (i = 0; i < count; ++i) {
320 DriveInfo *dinfo = drive_get(IF_MTD, 0, unit0 + i);
321 DeviceState *dev;
322
323 dev = qdev_new(flashtype);
324 if (dinfo) {
325 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo));
326 }
327 qdev_prop_set_uint8(dev, "cs", i);
328 qdev_realize_and_unref(dev, BUS(s->spi), &error_fatal);
329 }
330 }
331
332 static void sdhci_attach_drive(SDHCIState *sdhci, DriveInfo *dinfo, bool emmc,
333 bool boot_emmc)
334 {
335 DeviceState *card;
336
337 if (!dinfo) {
338 return;
339 }
340 card = qdev_new(emmc ? TYPE_EMMC : TYPE_SD_CARD);
341 if (emmc) {
342 qdev_prop_set_uint64(card, "boot-partition-size", 1 * MiB);
343 qdev_prop_set_uint8(card, "boot-config",
344 boot_emmc ? 0x1 << 3 : 0x0);
345 }
346 qdev_prop_set_drive_err(card, "drive", blk_by_legacy_dinfo(dinfo),
347 &error_fatal);
348 qdev_realize_and_unref(card,
349 qdev_get_child_bus(DEVICE(sdhci), "sd-bus"),
350 &error_fatal);
351 }
352
353 static void connect_serial_hds_to_uarts(AspeedMachineState *bmc)
354 {
355 AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(bmc);
356 AspeedSoCState *s = bmc->soc;
357 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
358 int uart_chosen = bmc->uart_chosen ? bmc->uart_chosen : amc->uart_default;
359
360 aspeed_soc_uart_set_chr(s, uart_chosen, serial_hd(0));
361 for (int i = 1, uart = sc->uarts_base; i < sc->uarts_num; i++, uart++) {
362 if (uart == uart_chosen) {
363 continue;
364 }
365 aspeed_soc_uart_set_chr(s, uart, serial_hd(i));
366 }
367 }
368
369 static void aspeed_machine_init(MachineState *machine)
370 {
371 AspeedMachineState *bmc = ASPEED_MACHINE(machine);
372 AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(machine);
373 AspeedSoCClass *sc;
374 int i;
375 DriveInfo *emmc0 = NULL;
376 bool boot_emmc;
377
378 bmc->soc = ASPEED_SOC(object_new(amc->soc_name));
379 object_property_add_child(OBJECT(machine), "soc", OBJECT(bmc->soc));
380 object_unref(OBJECT(bmc->soc));
381 sc = ASPEED_SOC_GET_CLASS(bmc->soc);
382
383 /*
384 * This will error out if the RAM size is not supported by the
385 * memory controller of the SoC.
386 */
387 object_property_set_uint(OBJECT(bmc->soc), "ram-size", machine->ram_size,
388 &error_fatal);
389
390 for (i = 0; i < sc->macs_num; i++) {
391 if ((amc->macs_mask & (1 << i)) &&
392 !qemu_configure_nic_device(DEVICE(&bmc->soc->ftgmac100[i]),
393 true, NULL)) {
394 break; /* No configs left; stop asking */
395 }
396 }
397
398 object_property_set_int(OBJECT(bmc->soc), "hw-strap1", bmc->hw_strap1,
399 &error_abort);
400 object_property_set_int(OBJECT(bmc->soc), "hw-strap2", amc->hw_strap2,
401 &error_abort);
402 object_property_set_link(OBJECT(bmc->soc), "memory",
403 OBJECT(get_system_memory()), &error_abort);
404 object_property_set_link(OBJECT(bmc->soc), "dram",
405 OBJECT(machine->ram), &error_abort);
406 if (machine->kernel_filename) {
407 /*
408 * When booting with a -kernel command line there is no u-boot
409 * that runs to unlock the SCU. In this case set the default to
410 * be unlocked as the kernel expects
411 */
412 object_property_set_int(OBJECT(bmc->soc), "hw-prot-key",
413 ASPEED_SCU_PROT_KEY, &error_abort);
414 }
415 connect_serial_hds_to_uarts(bmc);
416 qdev_realize(DEVICE(bmc->soc), NULL, &error_abort);
417
418 if (defaults_enabled()) {
419 aspeed_board_init_flashes(&bmc->soc->fmc,
420 bmc->fmc_model ? bmc->fmc_model : amc->fmc_model,
421 amc->num_cs, 0);
422 aspeed_board_init_flashes(&bmc->soc->spi[0],
423 bmc->spi_model ? bmc->spi_model : amc->spi_model,
424 1, amc->num_cs);
425 }
426
427 if (machine->kernel_filename && sc->num_cpus > 1) {
428 /* With no u-boot we must set up a boot stub for the secondary CPU */
429 MemoryRegion *smpboot = g_new(MemoryRegion, 1);
430 memory_region_init_ram(smpboot, NULL, "aspeed.smpboot",
431 0x80, &error_abort);
432 memory_region_add_subregion(get_system_memory(),
433 AST_SMP_MAILBOX_BASE, smpboot);
434
435 aspeed_board_binfo.write_secondary_boot = aspeed_write_smpboot;
436 aspeed_board_binfo.secondary_cpu_reset_hook = aspeed_reset_secondary;
437 aspeed_board_binfo.smp_loader_start = AST_SMP_MBOX_CODE;
438 }
439
440 aspeed_board_binfo.ram_size = machine->ram_size;
441 aspeed_board_binfo.loader_start = sc->memmap[ASPEED_DEV_SDRAM];
442
443 if (amc->i2c_init) {
444 amc->i2c_init(bmc);
445 }
446
447 for (i = 0; i < bmc->soc->sdhci.num_slots; i++) {
448 sdhci_attach_drive(&bmc->soc->sdhci.slots[i],
449 drive_get(IF_SD, 0, i), false, false);
450 }
451
452 boot_emmc = sc->boot_from_emmc(bmc->soc);
453
454 if (bmc->soc->emmc.num_slots) {
455 emmc0 = drive_get(IF_SD, 0, bmc->soc->sdhci.num_slots);
456 sdhci_attach_drive(&bmc->soc->emmc.slots[0], emmc0, true, boot_emmc);
457 }
458
459 if (!bmc->mmio_exec) {
460 DeviceState *dev = ssi_get_cs(bmc->soc->fmc.spi, 0);
461 BlockBackend *fmc0 = dev ? m25p80_get_blk(dev) : NULL;
462
463 if (fmc0 && !boot_emmc) {
464 uint64_t rom_size = memory_region_size(&bmc->soc->spi_boot);
465 aspeed_install_boot_rom(bmc, fmc0, rom_size);
466 } else if (emmc0) {
467 aspeed_install_boot_rom(bmc, blk_by_legacy_dinfo(emmc0), 64 * KiB);
468 }
469 }
470
471 arm_load_kernel(ARM_CPU(first_cpu), machine, &aspeed_board_binfo);
472 }
473
474 static void palmetto_bmc_i2c_init(AspeedMachineState *bmc)
475 {
476 AspeedSoCState *soc = bmc->soc;
477 DeviceState *dev;
478 uint8_t *eeprom_buf = g_malloc0(32 * 1024);
479
480 /*
481 * The palmetto platform expects a ds3231 RTC but a ds1338 is
482 * enough to provide basic RTC features. Alarms will be missing
483 */
484 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 0), "ds1338", 0x68);
485
486 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 0), 0x50,
487 eeprom_buf);
488
489 /* add a TMP423 temperature sensor */
490 dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2),
491 "tmp423", 0x4c));
492 object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort);
493 object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort);
494 object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort);
495 object_property_set_int(OBJECT(dev), "temperature3", 110000, &error_abort);
496 }
497
498 static void quanta_q71l_bmc_i2c_init(AspeedMachineState *bmc)
499 {
500 AspeedSoCState *soc = bmc->soc;
501
502 /*
503 * The quanta-q71l platform expects tmp75s which are compatible with
504 * tmp105s.
505 */
506 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1), "tmp105", 0x4c);
507 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1), "tmp105", 0x4e);
508 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1), "tmp105", 0x4f);
509
510 /* TODO: i2c-1: Add baseboard FRU eeprom@54 24c64 */
511 /* TODO: i2c-1: Add Frontpanel FRU eeprom@57 24c64 */
512 /* TODO: Add Memory Riser i2c mux and eeproms. */
513
514 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "pca9546", 0x74);
515 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "pca9548", 0x77);
516
517 /* TODO: i2c-3: Add BIOS FRU eeprom@56 24c64 */
518
519 /* i2c-7 */
520 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "pca9546", 0x70);
521 /* - i2c@0: pmbus@59 */
522 /* - i2c@1: pmbus@58 */
523 /* - i2c@2: pmbus@58 */
524 /* - i2c@3: pmbus@59 */
525
526 /* TODO: i2c-7: Add PDB FRU eeprom@52 */
527 /* TODO: i2c-8: Add BMC FRU eeprom@50 */
528 }
529
530 static void ast2500_evb_i2c_init(AspeedMachineState *bmc)
531 {
532 AspeedSoCState *soc = bmc->soc;
533 uint8_t *eeprom_buf = g_malloc0(8 * 1024);
534
535 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 3), 0x50,
536 eeprom_buf);
537
538 /* The AST2500 EVB expects a LM75 but a TMP105 is compatible */
539 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7),
540 TYPE_TMP105, 0x4d);
541 }
542
543 static void ast2600_evb_i2c_init(AspeedMachineState *bmc)
544 {
545 AspeedSoCState *soc = bmc->soc;
546 uint8_t *eeprom_buf = g_malloc0(8 * 1024);
547
548 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 7), 0x50,
549 eeprom_buf);
550
551 /* LM75 is compatible with TMP105 driver */
552 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8),
553 TYPE_TMP105, 0x4d);
554 }
555
556 static void yosemitev2_bmc_i2c_init(AspeedMachineState *bmc)
557 {
558 AspeedSoCState *soc = bmc->soc;
559
560 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 4), 0x51, 128 * KiB);
561 at24c_eeprom_init_rom(aspeed_i2c_get_bus(&soc->i2c, 8), 0x51, 128 * KiB,
562 yosemitev2_bmc_fruid, yosemitev2_bmc_fruid_len);
563 /* TMP421 */
564 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), "tmp421", 0x1f);
565 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "tmp421", 0x4e);
566 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "tmp421", 0x4f);
567
568 }
569
570 static void romulus_bmc_i2c_init(AspeedMachineState *bmc)
571 {
572 AspeedSoCState *soc = bmc->soc;
573
574 /*
575 * The romulus board expects Epson RX8900 I2C RTC but a ds1338 is
576 * good enough
577 */
578 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), "ds1338", 0x32);
579 }
580
581 static void tiogapass_bmc_i2c_init(AspeedMachineState *bmc)
582 {
583 AspeedSoCState *soc = bmc->soc;
584
585 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 4), 0x54, 128 * KiB);
586 at24c_eeprom_init_rom(aspeed_i2c_get_bus(&soc->i2c, 6), 0x54, 128 * KiB,
587 tiogapass_bmc_fruid, tiogapass_bmc_fruid_len);
588 /* TMP421 */
589 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), "tmp421", 0x1f);
590 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), "tmp421", 0x4f);
591 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), "tmp421", 0x4e);
592 }
593
594 static void create_pca9552(AspeedSoCState *soc, int bus_id, int addr)
595 {
596 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, bus_id),
597 TYPE_PCA9552, addr);
598 }
599
600 static void sonorapass_bmc_i2c_init(AspeedMachineState *bmc)
601 {
602 AspeedSoCState *soc = bmc->soc;
603
604 /* bus 2 : */
605 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "tmp105", 0x48);
606 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "tmp105", 0x49);
607 /* bus 2 : pca9546 @ 0x73 */
608
609 /* bus 3 : pca9548 @ 0x70 */
610
611 /* bus 4 : */
612 uint8_t *eeprom4_54 = g_malloc0(8 * 1024);
613 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 4), 0x54,
614 eeprom4_54);
615 /* PCA9539 @ 0x76, but PCA9552 is compatible */
616 create_pca9552(soc, 4, 0x76);
617 /* PCA9539 @ 0x77, but PCA9552 is compatible */
618 create_pca9552(soc, 4, 0x77);
619
620 /* bus 6 : */
621 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), "tmp105", 0x48);
622 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), "tmp105", 0x49);
623 /* bus 6 : pca9546 @ 0x73 */
624
625 /* bus 8 : */
626 uint8_t *eeprom8_56 = g_malloc0(8 * 1024);
627 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 8), 0x56,
628 eeprom8_56);
629 create_pca9552(soc, 8, 0x60);
630 create_pca9552(soc, 8, 0x61);
631 /* bus 8 : adc128d818 @ 0x1d */
632 /* bus 8 : adc128d818 @ 0x1f */
633
634 /*
635 * bus 13 : pca9548 @ 0x71
636 * - channel 3:
637 * - tmm421 @ 0x4c
638 * - tmp421 @ 0x4e
639 * - tmp421 @ 0x4f
640 */
641
642 }
643
644 static void witherspoon_bmc_i2c_init(AspeedMachineState *bmc)
645 {
646 static const struct {
647 unsigned gpio_id;
648 LEDColor color;
649 const char *description;
650 bool gpio_polarity;
651 } pca1_leds[] = {
652 {13, LED_COLOR_GREEN, "front-fault-4", GPIO_POLARITY_ACTIVE_LOW},
653 {14, LED_COLOR_GREEN, "front-power-3", GPIO_POLARITY_ACTIVE_LOW},
654 {15, LED_COLOR_GREEN, "front-id-5", GPIO_POLARITY_ACTIVE_LOW},
655 };
656 AspeedSoCState *soc = bmc->soc;
657 uint8_t *eeprom_buf = g_malloc0(8 * 1024);
658 DeviceState *dev;
659 LEDState *led;
660
661 /* Bus 3: TODO bmp280@77 */
662 dev = DEVICE(i2c_slave_new(TYPE_PCA9552, 0x60));
663 qdev_prop_set_string(dev, "description", "pca1");
664 i2c_slave_realize_and_unref(I2C_SLAVE(dev),
665 aspeed_i2c_get_bus(&soc->i2c, 3),
666 &error_fatal);
667
668 for (size_t i = 0; i < ARRAY_SIZE(pca1_leds); i++) {
669 led = led_create_simple(OBJECT(bmc),
670 pca1_leds[i].gpio_polarity,
671 pca1_leds[i].color,
672 pca1_leds[i].description);
673 qdev_connect_gpio_out(dev, pca1_leds[i].gpio_id,
674 qdev_get_gpio_in(DEVICE(led), 0));
675 }
676 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3), "dps310", 0x76);
677 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3), "max31785", 0x52);
678 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), "tmp423", 0x4c);
679 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), "tmp423", 0x4c);
680
681 /* The Witherspoon expects a TMP275 but a TMP105 is compatible */
682 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), TYPE_TMP105,
683 0x4a);
684
685 /*
686 * The witherspoon board expects Epson RX8900 I2C RTC but a ds1338 is
687 * good enough
688 */
689 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), "ds1338", 0x32);
690
691 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 11), 0x51,
692 eeprom_buf);
693 dev = DEVICE(i2c_slave_new(TYPE_PCA9552, 0x60));
694 qdev_prop_set_string(dev, "description", "pca0");
695 i2c_slave_realize_and_unref(I2C_SLAVE(dev),
696 aspeed_i2c_get_bus(&soc->i2c, 11),
697 &error_fatal);
698 /* Bus 11: TODO ucd90160@64 */
699 }
700
701 static void g220a_bmc_i2c_init(AspeedMachineState *bmc)
702 {
703 AspeedSoCState *soc = bmc->soc;
704 DeviceState *dev;
705
706 dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3),
707 "emc1413", 0x4c));
708 object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort);
709 object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort);
710 object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort);
711
712 dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 12),
713 "emc1413", 0x4c));
714 object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort);
715 object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort);
716 object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort);
717
718 dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 13),
719 "emc1413", 0x4c));
720 object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort);
721 object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort);
722 object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort);
723
724 static uint8_t eeprom_buf[2 * 1024] = {
725 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0xfe,
726 0x01, 0x06, 0x00, 0xc9, 0x42, 0x79, 0x74, 0x65,
727 0x64, 0x61, 0x6e, 0x63, 0x65, 0xc5, 0x47, 0x32,
728 0x32, 0x30, 0x41, 0xc4, 0x41, 0x41, 0x42, 0x42,
729 0xc4, 0x43, 0x43, 0x44, 0x44, 0xc4, 0x45, 0x45,
730 0x46, 0x46, 0xc4, 0x48, 0x48, 0x47, 0x47, 0xc1,
731 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa7,
732 };
733 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 4), 0x57,
734 eeprom_buf);
735 }
736
737 static void fp5280g2_bmc_i2c_init(AspeedMachineState *bmc)
738 {
739 AspeedSoCState *soc = bmc->soc;
740 I2CSlave *i2c_mux;
741
742 /* The at24c256 */
743 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 1), 0x50, 32768);
744
745 /* The fp5280g2 expects a TMP112 but a TMP105 is compatible */
746 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), TYPE_TMP105,
747 0x48);
748 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), TYPE_TMP105,
749 0x49);
750
751 i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2),
752 "pca9546", 0x70);
753 /* It expects a TMP112 but a TMP105 is compatible */
754 i2c_slave_create_simple(pca954x_i2c_get_bus(i2c_mux, 0), TYPE_TMP105,
755 0x4a);
756
757 /* It expects a ds3232 but a ds1338 is good enough */
758 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), "ds1338", 0x68);
759
760 /* It expects a pca9555 but a pca9552 is compatible */
761 create_pca9552(soc, 8, 0x30);
762 }
763
764 static void rainier_bmc_i2c_init(AspeedMachineState *bmc)
765 {
766 AspeedSoCState *soc = bmc->soc;
767 I2CSlave *i2c_mux;
768
769 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 0), 0x51, 32 * KiB);
770
771 create_pca9552(soc, 3, 0x61);
772
773 /* The rainier expects a TMP275 but a TMP105 is compatible */
774 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), TYPE_TMP105,
775 0x48);
776 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), TYPE_TMP105,
777 0x49);
778 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), TYPE_TMP105,
779 0x4a);
780 i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4),
781 "pca9546", 0x70);
782 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB);
783 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB);
784 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 2), 0x52, 64 * KiB);
785 create_pca9552(soc, 4, 0x60);
786
787 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), TYPE_TMP105,
788 0x48);
789 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), TYPE_TMP105,
790 0x49);
791 create_pca9552(soc, 5, 0x60);
792 create_pca9552(soc, 5, 0x61);
793 i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5),
794 "pca9546", 0x70);
795 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB);
796 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB);
797
798 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), TYPE_TMP105,
799 0x48);
800 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), TYPE_TMP105,
801 0x4a);
802 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), TYPE_TMP105,
803 0x4b);
804 i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6),
805 "pca9546", 0x70);
806 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB);
807 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB);
808 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 2), 0x50, 64 * KiB);
809 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 3), 0x51, 64 * KiB);
810
811 create_pca9552(soc, 7, 0x30);
812 create_pca9552(soc, 7, 0x31);
813 create_pca9552(soc, 7, 0x32);
814 create_pca9552(soc, 7, 0x33);
815 create_pca9552(soc, 7, 0x60);
816 create_pca9552(soc, 7, 0x61);
817 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "dps310", 0x76);
818 /* Bus 7: TODO si7021-a20@20 */
819 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), TYPE_TMP105,
820 0x48);
821 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "max31785", 0x52);
822 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 7), 0x50, 64 * KiB);
823 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 7), 0x51, 64 * KiB);
824
825 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), TYPE_TMP105,
826 0x48);
827 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), TYPE_TMP105,
828 0x4a);
829 at24c_eeprom_init_rom(aspeed_i2c_get_bus(&soc->i2c, 8), 0x50,
830 64 * KiB, rainier_bb_fruid, rainier_bb_fruid_len);
831 at24c_eeprom_init_rom(aspeed_i2c_get_bus(&soc->i2c, 8), 0x51,
832 64 * KiB, rainier_bmc_fruid, rainier_bmc_fruid_len);
833 create_pca9552(soc, 8, 0x60);
834 create_pca9552(soc, 8, 0x61);
835 /* Bus 8: ucd90320@11 */
836 /* Bus 8: ucd90320@b */
837 /* Bus 8: ucd90320@c */
838
839 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "tmp423", 0x4c);
840 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "tmp423", 0x4d);
841 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 9), 0x50, 128 * KiB);
842
843 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 10), "tmp423", 0x4c);
844 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 10), "tmp423", 0x4d);
845 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 10), 0x50, 128 * KiB);
846
847 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), TYPE_TMP105,
848 0x48);
849 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), TYPE_TMP105,
850 0x49);
851 i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11),
852 "pca9546", 0x70);
853 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB);
854 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB);
855 create_pca9552(soc, 11, 0x60);
856
857
858 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 13), 0x50, 64 * KiB);
859 create_pca9552(soc, 13, 0x60);
860
861 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 14), 0x50, 64 * KiB);
862 create_pca9552(soc, 14, 0x60);
863
864 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 15), 0x50, 64 * KiB);
865 create_pca9552(soc, 15, 0x60);
866 }
867
868 static void get_pca9548_channels(I2CBus *bus, uint8_t mux_addr,
869 I2CBus **channels)
870 {
871 I2CSlave *mux = i2c_slave_create_simple(bus, "pca9548", mux_addr);
872 for (int i = 0; i < 8; i++) {
873 channels[i] = pca954x_i2c_get_bus(mux, i);
874 }
875 }
876
877 #define TYPE_LM75 TYPE_TMP105
878 #define TYPE_TMP75 TYPE_TMP105
879 #define TYPE_TMP422 "tmp422"
880
881 static void fuji_bmc_i2c_init(AspeedMachineState *bmc)
882 {
883 AspeedSoCState *soc = bmc->soc;
884 I2CBus *i2c[144] = {};
885
886 for (int i = 0; i < 16; i++) {
887 i2c[i] = aspeed_i2c_get_bus(&soc->i2c, i);
888 }
889 I2CBus *i2c180 = i2c[2];
890 I2CBus *i2c480 = i2c[8];
891 I2CBus *i2c600 = i2c[11];
892
893 get_pca9548_channels(i2c180, 0x70, &i2c[16]);
894 get_pca9548_channels(i2c480, 0x70, &i2c[24]);
895 /* NOTE: The device tree skips [32, 40) in the alias numbering */
896 get_pca9548_channels(i2c600, 0x77, &i2c[40]);
897 get_pca9548_channels(i2c[24], 0x71, &i2c[48]);
898 get_pca9548_channels(i2c[25], 0x72, &i2c[56]);
899 get_pca9548_channels(i2c[26], 0x76, &i2c[64]);
900 get_pca9548_channels(i2c[27], 0x76, &i2c[72]);
901 for (int i = 0; i < 8; i++) {
902 get_pca9548_channels(i2c[40 + i], 0x76, &i2c[80 + i * 8]);
903 }
904
905 i2c_slave_create_simple(i2c[17], TYPE_LM75, 0x4c);
906 i2c_slave_create_simple(i2c[17], TYPE_LM75, 0x4d);
907
908 /*
909 * EEPROM 24c64 size is 64Kbits or 8 Kbytes
910 * 24c02 size is 2Kbits or 256 bytes
911 */
912 at24c_eeprom_init(i2c[19], 0x52, 8 * KiB);
913 at24c_eeprom_init(i2c[20], 0x50, 256);
914 at24c_eeprom_init(i2c[22], 0x52, 256);
915
916 i2c_slave_create_simple(i2c[3], TYPE_LM75, 0x48);
917 i2c_slave_create_simple(i2c[3], TYPE_LM75, 0x49);
918 i2c_slave_create_simple(i2c[3], TYPE_LM75, 0x4a);
919 i2c_slave_create_simple(i2c[3], TYPE_TMP422, 0x4c);
920
921 at24c_eeprom_init(i2c[8], 0x51, 8 * KiB);
922 i2c_slave_create_simple(i2c[8], TYPE_LM75, 0x4a);
923
924 i2c_slave_create_simple(i2c[50], TYPE_LM75, 0x4c);
925 at24c_eeprom_init(i2c[50], 0x52, 8 * KiB);
926 i2c_slave_create_simple(i2c[51], TYPE_TMP75, 0x48);
927 i2c_slave_create_simple(i2c[52], TYPE_TMP75, 0x49);
928
929 i2c_slave_create_simple(i2c[59], TYPE_TMP75, 0x48);
930 i2c_slave_create_simple(i2c[60], TYPE_TMP75, 0x49);
931
932 at24c_eeprom_init(i2c[65], 0x53, 8 * KiB);
933 i2c_slave_create_simple(i2c[66], TYPE_TMP75, 0x49);
934 i2c_slave_create_simple(i2c[66], TYPE_TMP75, 0x48);
935 at24c_eeprom_init(i2c[68], 0x52, 8 * KiB);
936 at24c_eeprom_init(i2c[69], 0x52, 8 * KiB);
937 at24c_eeprom_init(i2c[70], 0x52, 8 * KiB);
938 at24c_eeprom_init(i2c[71], 0x52, 8 * KiB);
939
940 at24c_eeprom_init(i2c[73], 0x53, 8 * KiB);
941 i2c_slave_create_simple(i2c[74], TYPE_TMP75, 0x49);
942 i2c_slave_create_simple(i2c[74], TYPE_TMP75, 0x48);
943 at24c_eeprom_init(i2c[76], 0x52, 8 * KiB);
944 at24c_eeprom_init(i2c[77], 0x52, 8 * KiB);
945 at24c_eeprom_init(i2c[78], 0x52, 8 * KiB);
946 at24c_eeprom_init(i2c[79], 0x52, 8 * KiB);
947 at24c_eeprom_init(i2c[28], 0x50, 256);
948
949 for (int i = 0; i < 8; i++) {
950 at24c_eeprom_init(i2c[81 + i * 8], 0x56, 64 * KiB);
951 i2c_slave_create_simple(i2c[82 + i * 8], TYPE_TMP75, 0x48);
952 i2c_slave_create_simple(i2c[83 + i * 8], TYPE_TMP75, 0x4b);
953 i2c_slave_create_simple(i2c[84 + i * 8], TYPE_TMP75, 0x4a);
954 }
955 }
956
957 #define TYPE_TMP421 "tmp421"
958
959 static void bletchley_bmc_i2c_init(AspeedMachineState *bmc)
960 {
961 AspeedSoCState *soc = bmc->soc;
962 I2CBus *i2c[13] = {};
963 for (int i = 0; i < 13; i++) {
964 if ((i == 8) || (i == 11)) {
965 continue;
966 }
967 i2c[i] = aspeed_i2c_get_bus(&soc->i2c, i);
968 }
969
970 /* Bus 0 - 5 all have the same config. */
971 for (int i = 0; i < 6; i++) {
972 /* Missing model: ti,ina230 @ 0x45 */
973 /* Missing model: mps,mp5023 @ 0x40 */
974 i2c_slave_create_simple(i2c[i], TYPE_TMP421, 0x4f);
975 /* Missing model: nxp,pca9539 @ 0x76, but PCA9552 works enough */
976 i2c_slave_create_simple(i2c[i], TYPE_PCA9552, 0x76);
977 i2c_slave_create_simple(i2c[i], TYPE_PCA9552, 0x67);
978 /* Missing model: fsc,fusb302 @ 0x22 */
979 }
980
981 /* Bus 6 */
982 at24c_eeprom_init(i2c[6], 0x56, 65536);
983 /* Missing model: nxp,pcf85263 @ 0x51 , but ds1338 works enough */
984 i2c_slave_create_simple(i2c[6], "ds1338", 0x51);
985
986
987 /* Bus 7 */
988 at24c_eeprom_init(i2c[7], 0x54, 65536);
989
990 /* Bus 9 */
991 i2c_slave_create_simple(i2c[9], TYPE_TMP421, 0x4f);
992
993 /* Bus 10 */
994 i2c_slave_create_simple(i2c[10], TYPE_TMP421, 0x4f);
995 /* Missing model: ti,hdc1080 @ 0x40 */
996 i2c_slave_create_simple(i2c[10], TYPE_PCA9552, 0x67);
997
998 /* Bus 12 */
999 /* Missing model: adi,adm1278 @ 0x11 */
1000 i2c_slave_create_simple(i2c[12], TYPE_TMP421, 0x4c);
1001 i2c_slave_create_simple(i2c[12], TYPE_TMP421, 0x4d);
1002 i2c_slave_create_simple(i2c[12], TYPE_PCA9552, 0x67);
1003 }
1004
1005 static void fby35_i2c_init(AspeedMachineState *bmc)
1006 {
1007 AspeedSoCState *soc = bmc->soc;
1008 I2CBus *i2c[16];
1009
1010 for (int i = 0; i < 16; i++) {
1011 i2c[i] = aspeed_i2c_get_bus(&soc->i2c, i);
1012 }
1013
1014 i2c_slave_create_simple(i2c[2], TYPE_LM75, 0x4f);
1015 i2c_slave_create_simple(i2c[8], TYPE_TMP421, 0x1f);
1016 /* Hotswap controller is actually supposed to be mp5920 or ltc4282. */
1017 i2c_slave_create_simple(i2c[11], "adm1272", 0x44);
1018 i2c_slave_create_simple(i2c[12], TYPE_LM75, 0x4e);
1019 i2c_slave_create_simple(i2c[12], TYPE_LM75, 0x4f);
1020
1021 at24c_eeprom_init(i2c[4], 0x51, 128 * KiB);
1022 at24c_eeprom_init(i2c[6], 0x51, 128 * KiB);
1023 at24c_eeprom_init_rom(i2c[8], 0x50, 32 * KiB, fby35_nic_fruid,
1024 fby35_nic_fruid_len);
1025 at24c_eeprom_init_rom(i2c[11], 0x51, 128 * KiB, fby35_bb_fruid,
1026 fby35_bb_fruid_len);
1027 at24c_eeprom_init_rom(i2c[11], 0x54, 128 * KiB, fby35_bmc_fruid,
1028 fby35_bmc_fruid_len);
1029
1030 /*
1031 * TODO: There is a multi-master i2c connection to an AST1030 MiniBMC on
1032 * buses 0, 1, 2, 3, and 9. Source address 0x10, target address 0x20 on
1033 * each.
1034 */
1035 }
1036
1037 static void qcom_dc_scm_bmc_i2c_init(AspeedMachineState *bmc)
1038 {
1039 AspeedSoCState *soc = bmc->soc;
1040
1041 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 15), "tmp105", 0x4d);
1042 }
1043
1044 static void qcom_dc_scm_firework_i2c_init(AspeedMachineState *bmc)
1045 {
1046 AspeedSoCState *soc = bmc->soc;
1047 I2CSlave *therm_mux, *cpuvr_mux;
1048
1049 /* Create the generic DC-SCM hardware */
1050 qcom_dc_scm_bmc_i2c_init(bmc);
1051
1052 /* Now create the Firework specific hardware */
1053
1054 /* I2C7 CPUVR MUX */
1055 cpuvr_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7),
1056 "pca9546", 0x70);
1057 i2c_slave_create_simple(pca954x_i2c_get_bus(cpuvr_mux, 0), "pca9548", 0x72);
1058 i2c_slave_create_simple(pca954x_i2c_get_bus(cpuvr_mux, 1), "pca9548", 0x72);
1059 i2c_slave_create_simple(pca954x_i2c_get_bus(cpuvr_mux, 2), "pca9548", 0x72);
1060 i2c_slave_create_simple(pca954x_i2c_get_bus(cpuvr_mux, 3), "pca9548", 0x72);
1061
1062 /* I2C8 Thermal Diodes*/
1063 therm_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8),
1064 "pca9548", 0x70);
1065 i2c_slave_create_simple(pca954x_i2c_get_bus(therm_mux, 0), TYPE_LM75, 0x4C);
1066 i2c_slave_create_simple(pca954x_i2c_get_bus(therm_mux, 1), TYPE_LM75, 0x4C);
1067 i2c_slave_create_simple(pca954x_i2c_get_bus(therm_mux, 2), TYPE_LM75, 0x48);
1068 i2c_slave_create_simple(pca954x_i2c_get_bus(therm_mux, 3), TYPE_LM75, 0x48);
1069 i2c_slave_create_simple(pca954x_i2c_get_bus(therm_mux, 4), TYPE_LM75, 0x48);
1070
1071 /* I2C9 Fan Controller (MAX31785) */
1072 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "max31785", 0x52);
1073 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "max31785", 0x54);
1074 }
1075
1076 static bool aspeed_get_mmio_exec(Object *obj, Error **errp)
1077 {
1078 return ASPEED_MACHINE(obj)->mmio_exec;
1079 }
1080
1081 static void aspeed_set_mmio_exec(Object *obj, bool value, Error **errp)
1082 {
1083 ASPEED_MACHINE(obj)->mmio_exec = value;
1084 }
1085
1086 static void aspeed_machine_instance_init(Object *obj)
1087 {
1088 AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(obj);
1089
1090 ASPEED_MACHINE(obj)->mmio_exec = false;
1091 ASPEED_MACHINE(obj)->hw_strap1 = amc->hw_strap1;
1092 }
1093
1094 static char *aspeed_get_fmc_model(Object *obj, Error **errp)
1095 {
1096 AspeedMachineState *bmc = ASPEED_MACHINE(obj);
1097 return g_strdup(bmc->fmc_model);
1098 }
1099
1100 static void aspeed_set_fmc_model(Object *obj, const char *value, Error **errp)
1101 {
1102 AspeedMachineState *bmc = ASPEED_MACHINE(obj);
1103
1104 g_free(bmc->fmc_model);
1105 bmc->fmc_model = g_strdup(value);
1106 }
1107
1108 static char *aspeed_get_spi_model(Object *obj, Error **errp)
1109 {
1110 AspeedMachineState *bmc = ASPEED_MACHINE(obj);
1111 return g_strdup(bmc->spi_model);
1112 }
1113
1114 static void aspeed_set_spi_model(Object *obj, const char *value, Error **errp)
1115 {
1116 AspeedMachineState *bmc = ASPEED_MACHINE(obj);
1117
1118 g_free(bmc->spi_model);
1119 bmc->spi_model = g_strdup(value);
1120 }
1121
1122 static char *aspeed_get_bmc_console(Object *obj, Error **errp)
1123 {
1124 AspeedMachineState *bmc = ASPEED_MACHINE(obj);
1125 AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(bmc);
1126 int uart_chosen = bmc->uart_chosen ? bmc->uart_chosen : amc->uart_default;
1127
1128 return g_strdup_printf("uart%d", aspeed_uart_index(uart_chosen));
1129 }
1130
1131 static void aspeed_set_bmc_console(Object *obj, const char *value, Error **errp)
1132 {
1133 AspeedMachineState *bmc = ASPEED_MACHINE(obj);
1134 AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(bmc);
1135 AspeedSoCClass *sc = ASPEED_SOC_CLASS(object_class_by_name(amc->soc_name));
1136 int val;
1137 int uart_first = aspeed_uart_first(sc);
1138 int uart_last = aspeed_uart_last(sc);
1139
1140 if (sscanf(value, "uart%u", &val) != 1) {
1141 error_setg(errp, "Bad value for \"uart\" property");
1142 return;
1143 }
1144
1145 /* The number of UART depends on the SoC */
1146 if (val < uart_first || val > uart_last) {
1147 error_setg(errp, "\"uart\" should be in range [%d - %d]",
1148 uart_first, uart_last);
1149 return;
1150 }
1151 bmc->uart_chosen = val + ASPEED_DEV_UART0;
1152 }
1153
1154 static void aspeed_machine_class_props_init(ObjectClass *oc)
1155 {
1156 object_class_property_add_bool(oc, "execute-in-place",
1157 aspeed_get_mmio_exec,
1158 aspeed_set_mmio_exec);
1159 object_class_property_set_description(oc, "execute-in-place",
1160 "boot directly from CE0 flash device");
1161
1162 object_class_property_add_str(oc, "bmc-console", aspeed_get_bmc_console,
1163 aspeed_set_bmc_console);
1164 object_class_property_set_description(oc, "bmc-console",
1165 "Change the default UART to \"uartX\"");
1166
1167 object_class_property_add_str(oc, "fmc-model", aspeed_get_fmc_model,
1168 aspeed_set_fmc_model);
1169 object_class_property_set_description(oc, "fmc-model",
1170 "Change the FMC Flash model");
1171 object_class_property_add_str(oc, "spi-model", aspeed_get_spi_model,
1172 aspeed_set_spi_model);
1173 object_class_property_set_description(oc, "spi-model",
1174 "Change the SPI Flash model");
1175 }
1176
1177 static void aspeed_machine_class_init_cpus_defaults(MachineClass *mc)
1178 {
1179 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(mc);
1180 AspeedSoCClass *sc = ASPEED_SOC_CLASS(object_class_by_name(amc->soc_name));
1181
1182 mc->default_cpus = sc->num_cpus;
1183 mc->min_cpus = sc->num_cpus;
1184 mc->max_cpus = sc->num_cpus;
1185 mc->valid_cpu_types = sc->valid_cpu_types;
1186 }
1187
1188 static bool aspeed_machine_ast2600_get_boot_from_emmc(Object *obj, Error **errp)
1189 {
1190 AspeedMachineState *bmc = ASPEED_MACHINE(obj);
1191
1192 return !!(bmc->hw_strap1 & SCU_AST2600_HW_STRAP_BOOT_SRC_EMMC);
1193 }
1194
1195 static void aspeed_machine_ast2600_set_boot_from_emmc(Object *obj, bool value,
1196 Error **errp)
1197 {
1198 AspeedMachineState *bmc = ASPEED_MACHINE(obj);
1199
1200 if (value) {
1201 bmc->hw_strap1 |= SCU_AST2600_HW_STRAP_BOOT_SRC_EMMC;
1202 } else {
1203 bmc->hw_strap1 &= ~SCU_AST2600_HW_STRAP_BOOT_SRC_EMMC;
1204 }
1205 }
1206
1207 static void aspeed_machine_ast2600_class_emmc_init(ObjectClass *oc)
1208 {
1209 object_class_property_add_bool(oc, "boot-emmc",
1210 aspeed_machine_ast2600_get_boot_from_emmc,
1211 aspeed_machine_ast2600_set_boot_from_emmc);
1212 object_class_property_set_description(oc, "boot-emmc",
1213 "Set or unset boot from EMMC");
1214 }
1215
1216 static void aspeed_machine_class_init(ObjectClass *oc, void *data)
1217 {
1218 MachineClass *mc = MACHINE_CLASS(oc);
1219 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1220
1221 mc->init = aspeed_machine_init;
1222 mc->no_floppy = 1;
1223 mc->no_cdrom = 1;
1224 mc->no_parallel = 1;
1225 mc->default_ram_id = "ram";
1226 amc->macs_mask = ASPEED_MAC0_ON;
1227 amc->uart_default = ASPEED_DEV_UART5;
1228
1229 aspeed_machine_class_props_init(oc);
1230 }
1231
1232 static void aspeed_machine_palmetto_class_init(ObjectClass *oc, void *data)
1233 {
1234 MachineClass *mc = MACHINE_CLASS(oc);
1235 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1236
1237 mc->desc = "OpenPOWER Palmetto BMC (ARM926EJ-S)";
1238 amc->soc_name = "ast2400-a1";
1239 amc->hw_strap1 = PALMETTO_BMC_HW_STRAP1;
1240 amc->fmc_model = "n25q256a";
1241 amc->spi_model = "mx25l25635f";
1242 amc->num_cs = 1;
1243 amc->i2c_init = palmetto_bmc_i2c_init;
1244 mc->default_ram_size = 256 * MiB;
1245 aspeed_machine_class_init_cpus_defaults(mc);
1246 };
1247
1248 static void aspeed_machine_quanta_q71l_class_init(ObjectClass *oc, void *data)
1249 {
1250 MachineClass *mc = MACHINE_CLASS(oc);
1251 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1252
1253 mc->desc = "Quanta-Q71l BMC (ARM926EJ-S)";
1254 amc->soc_name = "ast2400-a1";
1255 amc->hw_strap1 = QUANTA_Q71L_BMC_HW_STRAP1;
1256 amc->fmc_model = "n25q256a";
1257 amc->spi_model = "mx25l25635e";
1258 amc->num_cs = 1;
1259 amc->i2c_init = quanta_q71l_bmc_i2c_init;
1260 mc->default_ram_size = 128 * MiB;
1261 aspeed_machine_class_init_cpus_defaults(mc);
1262 }
1263
1264 static void aspeed_machine_supermicrox11_bmc_class_init(ObjectClass *oc,
1265 void *data)
1266 {
1267 MachineClass *mc = MACHINE_CLASS(oc);
1268 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1269
1270 mc->desc = "Supermicro X11 BMC (ARM926EJ-S)";
1271 amc->soc_name = "ast2400-a1";
1272 amc->hw_strap1 = SUPERMICROX11_BMC_HW_STRAP1;
1273 amc->fmc_model = "mx25l25635e";
1274 amc->spi_model = "mx25l25635e";
1275 amc->num_cs = 1;
1276 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON;
1277 amc->i2c_init = palmetto_bmc_i2c_init;
1278 mc->default_ram_size = 256 * MiB;
1279 aspeed_machine_class_init_cpus_defaults(mc);
1280 }
1281
1282 static void aspeed_machine_supermicro_x11spi_bmc_class_init(ObjectClass *oc,
1283 void *data)
1284 {
1285 MachineClass *mc = MACHINE_CLASS(oc);
1286 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1287
1288 mc->desc = "Supermicro X11 SPI BMC (ARM1176)";
1289 amc->soc_name = "ast2500-a1";
1290 amc->hw_strap1 = SUPERMICRO_X11SPI_BMC_HW_STRAP1;
1291 amc->fmc_model = "mx25l25635e";
1292 amc->spi_model = "mx25l25635e";
1293 amc->num_cs = 1;
1294 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON;
1295 amc->i2c_init = palmetto_bmc_i2c_init;
1296 mc->default_ram_size = 512 * MiB;
1297 aspeed_machine_class_init_cpus_defaults(mc);
1298 }
1299
1300 static void aspeed_machine_ast2500_evb_class_init(ObjectClass *oc, void *data)
1301 {
1302 MachineClass *mc = MACHINE_CLASS(oc);
1303 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1304
1305 mc->desc = "Aspeed AST2500 EVB (ARM1176)";
1306 amc->soc_name = "ast2500-a1";
1307 amc->hw_strap1 = AST2500_EVB_HW_STRAP1;
1308 amc->fmc_model = "mx25l25635e";
1309 amc->spi_model = "mx25l25635f";
1310 amc->num_cs = 1;
1311 amc->i2c_init = ast2500_evb_i2c_init;
1312 mc->default_ram_size = 512 * MiB;
1313 aspeed_machine_class_init_cpus_defaults(mc);
1314 };
1315
1316 static void aspeed_machine_yosemitev2_class_init(ObjectClass *oc, void *data)
1317 {
1318 MachineClass *mc = MACHINE_CLASS(oc);
1319 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1320
1321 mc->desc = "Facebook YosemiteV2 BMC (ARM1176)";
1322 amc->soc_name = "ast2500-a1";
1323 amc->hw_strap1 = AST2500_EVB_HW_STRAP1;
1324 amc->hw_strap2 = 0;
1325 amc->fmc_model = "n25q256a";
1326 amc->spi_model = "mx25l25635e";
1327 amc->num_cs = 2;
1328 amc->i2c_init = yosemitev2_bmc_i2c_init;
1329 mc->default_ram_size = 512 * MiB;
1330 aspeed_machine_class_init_cpus_defaults(mc);
1331 };
1332
1333 static void aspeed_machine_romulus_class_init(ObjectClass *oc, void *data)
1334 {
1335 MachineClass *mc = MACHINE_CLASS(oc);
1336 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1337
1338 mc->desc = "OpenPOWER Romulus BMC (ARM1176)";
1339 amc->soc_name = "ast2500-a1";
1340 amc->hw_strap1 = ROMULUS_BMC_HW_STRAP1;
1341 amc->fmc_model = "n25q256a";
1342 amc->spi_model = "mx66l1g45g";
1343 amc->num_cs = 2;
1344 amc->i2c_init = romulus_bmc_i2c_init;
1345 mc->default_ram_size = 512 * MiB;
1346 aspeed_machine_class_init_cpus_defaults(mc);
1347 };
1348
1349 static void aspeed_machine_tiogapass_class_init(ObjectClass *oc, void *data)
1350 {
1351 MachineClass *mc = MACHINE_CLASS(oc);
1352 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1353
1354 mc->desc = "Facebook Tiogapass BMC (ARM1176)";
1355 amc->soc_name = "ast2500-a1";
1356 amc->hw_strap1 = AST2500_EVB_HW_STRAP1;
1357 amc->hw_strap2 = 0;
1358 amc->fmc_model = "n25q256a";
1359 amc->spi_model = "mx25l25635e";
1360 amc->num_cs = 2;
1361 amc->i2c_init = tiogapass_bmc_i2c_init;
1362 mc->default_ram_size = 1 * GiB;
1363 aspeed_machine_class_init_cpus_defaults(mc);
1364 };
1365
1366 static void aspeed_machine_sonorapass_class_init(ObjectClass *oc, void *data)
1367 {
1368 MachineClass *mc = MACHINE_CLASS(oc);
1369 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1370
1371 mc->desc = "OCP SonoraPass BMC (ARM1176)";
1372 amc->soc_name = "ast2500-a1";
1373 amc->hw_strap1 = SONORAPASS_BMC_HW_STRAP1;
1374 amc->fmc_model = "mx66l1g45g";
1375 amc->spi_model = "mx66l1g45g";
1376 amc->num_cs = 2;
1377 amc->i2c_init = sonorapass_bmc_i2c_init;
1378 mc->default_ram_size = 512 * MiB;
1379 aspeed_machine_class_init_cpus_defaults(mc);
1380 };
1381
1382 static void aspeed_machine_witherspoon_class_init(ObjectClass *oc, void *data)
1383 {
1384 MachineClass *mc = MACHINE_CLASS(oc);
1385 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1386
1387 mc->desc = "OpenPOWER Witherspoon BMC (ARM1176)";
1388 amc->soc_name = "ast2500-a1";
1389 amc->hw_strap1 = WITHERSPOON_BMC_HW_STRAP1;
1390 amc->fmc_model = "mx25l25635f";
1391 amc->spi_model = "mx66l1g45g";
1392 amc->num_cs = 2;
1393 amc->i2c_init = witherspoon_bmc_i2c_init;
1394 mc->default_ram_size = 512 * MiB;
1395 aspeed_machine_class_init_cpus_defaults(mc);
1396 };
1397
1398 static void aspeed_machine_ast2600_evb_class_init(ObjectClass *oc, void *data)
1399 {
1400 MachineClass *mc = MACHINE_CLASS(oc);
1401 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1402
1403 mc->desc = "Aspeed AST2600 EVB (Cortex-A7)";
1404 amc->soc_name = "ast2600-a3";
1405 amc->hw_strap1 = AST2600_EVB_HW_STRAP1;
1406 amc->hw_strap2 = AST2600_EVB_HW_STRAP2;
1407 amc->fmc_model = "mx66u51235f";
1408 amc->spi_model = "mx66u51235f";
1409 amc->num_cs = 1;
1410 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON | ASPEED_MAC2_ON |
1411 ASPEED_MAC3_ON;
1412 amc->i2c_init = ast2600_evb_i2c_init;
1413 mc->default_ram_size = 1 * GiB;
1414 aspeed_machine_class_init_cpus_defaults(mc);
1415 aspeed_machine_ast2600_class_emmc_init(oc);
1416 };
1417
1418 static void aspeed_machine_tacoma_class_init(ObjectClass *oc, void *data)
1419 {
1420 MachineClass *mc = MACHINE_CLASS(oc);
1421 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1422
1423 mc->desc = "OpenPOWER Tacoma BMC (Cortex-A7)";
1424 amc->soc_name = "ast2600-a3";
1425 amc->hw_strap1 = TACOMA_BMC_HW_STRAP1;
1426 amc->hw_strap2 = TACOMA_BMC_HW_STRAP2;
1427 amc->fmc_model = "mx66l1g45g";
1428 amc->spi_model = "mx66l1g45g";
1429 amc->num_cs = 2;
1430 amc->macs_mask = ASPEED_MAC2_ON;
1431 amc->i2c_init = witherspoon_bmc_i2c_init; /* Same board layout */
1432 mc->default_ram_size = 1 * GiB;
1433 aspeed_machine_class_init_cpus_defaults(mc);
1434
1435 mc->deprecation_reason = "Please use the similar 'rainier-bmc' machine";
1436 };
1437
1438 static void aspeed_machine_g220a_class_init(ObjectClass *oc, void *data)
1439 {
1440 MachineClass *mc = MACHINE_CLASS(oc);
1441 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1442
1443 mc->desc = "Bytedance G220A BMC (ARM1176)";
1444 amc->soc_name = "ast2500-a1";
1445 amc->hw_strap1 = G220A_BMC_HW_STRAP1;
1446 amc->fmc_model = "n25q512a";
1447 amc->spi_model = "mx25l25635e";
1448 amc->num_cs = 2;
1449 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON;
1450 amc->i2c_init = g220a_bmc_i2c_init;
1451 mc->default_ram_size = 1024 * MiB;
1452 aspeed_machine_class_init_cpus_defaults(mc);
1453 };
1454
1455 static void aspeed_machine_fp5280g2_class_init(ObjectClass *oc, void *data)
1456 {
1457 MachineClass *mc = MACHINE_CLASS(oc);
1458 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1459
1460 mc->desc = "Inspur FP5280G2 BMC (ARM1176)";
1461 amc->soc_name = "ast2500-a1";
1462 amc->hw_strap1 = FP5280G2_BMC_HW_STRAP1;
1463 amc->fmc_model = "n25q512a";
1464 amc->spi_model = "mx25l25635e";
1465 amc->num_cs = 2;
1466 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON;
1467 amc->i2c_init = fp5280g2_bmc_i2c_init;
1468 mc->default_ram_size = 512 * MiB;
1469 aspeed_machine_class_init_cpus_defaults(mc);
1470 };
1471
1472 static void aspeed_machine_rainier_class_init(ObjectClass *oc, void *data)
1473 {
1474 MachineClass *mc = MACHINE_CLASS(oc);
1475 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1476
1477 mc->desc = "IBM Rainier BMC (Cortex-A7)";
1478 amc->soc_name = "ast2600-a3";
1479 amc->hw_strap1 = RAINIER_BMC_HW_STRAP1;
1480 amc->hw_strap2 = RAINIER_BMC_HW_STRAP2;
1481 amc->fmc_model = "mx66l1g45g";
1482 amc->spi_model = "mx66l1g45g";
1483 amc->num_cs = 2;
1484 amc->macs_mask = ASPEED_MAC2_ON | ASPEED_MAC3_ON;
1485 amc->i2c_init = rainier_bmc_i2c_init;
1486 mc->default_ram_size = 1 * GiB;
1487 aspeed_machine_class_init_cpus_defaults(mc);
1488 aspeed_machine_ast2600_class_emmc_init(oc);
1489 };
1490
1491 #define FUJI_BMC_RAM_SIZE ASPEED_RAM_SIZE(2 * GiB)
1492
1493 static void aspeed_machine_fuji_class_init(ObjectClass *oc, void *data)
1494 {
1495 MachineClass *mc = MACHINE_CLASS(oc);
1496 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1497
1498 mc->desc = "Facebook Fuji BMC (Cortex-A7)";
1499 amc->soc_name = "ast2600-a3";
1500 amc->hw_strap1 = FUJI_BMC_HW_STRAP1;
1501 amc->hw_strap2 = FUJI_BMC_HW_STRAP2;
1502 amc->fmc_model = "mx66l1g45g";
1503 amc->spi_model = "mx66l1g45g";
1504 amc->num_cs = 2;
1505 amc->macs_mask = ASPEED_MAC3_ON;
1506 amc->i2c_init = fuji_bmc_i2c_init;
1507 amc->uart_default = ASPEED_DEV_UART1;
1508 mc->default_ram_size = FUJI_BMC_RAM_SIZE;
1509 aspeed_machine_class_init_cpus_defaults(mc);
1510 };
1511
1512 #define BLETCHLEY_BMC_RAM_SIZE ASPEED_RAM_SIZE(2 * GiB)
1513
1514 static void aspeed_machine_bletchley_class_init(ObjectClass *oc, void *data)
1515 {
1516 MachineClass *mc = MACHINE_CLASS(oc);
1517 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1518
1519 mc->desc = "Facebook Bletchley BMC (Cortex-A7)";
1520 amc->soc_name = "ast2600-a3";
1521 amc->hw_strap1 = BLETCHLEY_BMC_HW_STRAP1;
1522 amc->hw_strap2 = BLETCHLEY_BMC_HW_STRAP2;
1523 amc->fmc_model = "w25q01jvq";
1524 amc->spi_model = NULL;
1525 amc->num_cs = 2;
1526 amc->macs_mask = ASPEED_MAC2_ON;
1527 amc->i2c_init = bletchley_bmc_i2c_init;
1528 mc->default_ram_size = BLETCHLEY_BMC_RAM_SIZE;
1529 aspeed_machine_class_init_cpus_defaults(mc);
1530 }
1531
1532 static void fby35_reset(MachineState *state, ResetType type)
1533 {
1534 AspeedMachineState *bmc = ASPEED_MACHINE(state);
1535 AspeedGPIOState *gpio = &bmc->soc->gpio;
1536
1537 qemu_devices_reset(type);
1538
1539 /* Board ID: 7 (Class-1, 4 slots) */
1540 object_property_set_bool(OBJECT(gpio), "gpioV4", true, &error_fatal);
1541 object_property_set_bool(OBJECT(gpio), "gpioV5", true, &error_fatal);
1542 object_property_set_bool(OBJECT(gpio), "gpioV6", true, &error_fatal);
1543 object_property_set_bool(OBJECT(gpio), "gpioV7", false, &error_fatal);
1544
1545 /* Slot presence pins, inverse polarity. (False means present) */
1546 object_property_set_bool(OBJECT(gpio), "gpioH4", false, &error_fatal);
1547 object_property_set_bool(OBJECT(gpio), "gpioH5", true, &error_fatal);
1548 object_property_set_bool(OBJECT(gpio), "gpioH6", true, &error_fatal);
1549 object_property_set_bool(OBJECT(gpio), "gpioH7", true, &error_fatal);
1550
1551 /* Slot 12v power pins, normal polarity. (True means powered-on) */
1552 object_property_set_bool(OBJECT(gpio), "gpioB2", true, &error_fatal);
1553 object_property_set_bool(OBJECT(gpio), "gpioB3", false, &error_fatal);
1554 object_property_set_bool(OBJECT(gpio), "gpioB4", false, &error_fatal);
1555 object_property_set_bool(OBJECT(gpio), "gpioB5", false, &error_fatal);
1556 }
1557
1558 static void aspeed_machine_fby35_class_init(ObjectClass *oc, void *data)
1559 {
1560 MachineClass *mc = MACHINE_CLASS(oc);
1561 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1562
1563 mc->desc = "Facebook fby35 BMC (Cortex-A7)";
1564 mc->reset = fby35_reset;
1565 amc->fmc_model = "mx66l1g45g";
1566 amc->num_cs = 2;
1567 amc->macs_mask = ASPEED_MAC3_ON;
1568 amc->i2c_init = fby35_i2c_init;
1569 /* FIXME: Replace this macro with something more general */
1570 mc->default_ram_size = FUJI_BMC_RAM_SIZE;
1571 aspeed_machine_class_init_cpus_defaults(mc);
1572 }
1573
1574 #define AST1030_INTERNAL_FLASH_SIZE (1024 * 1024)
1575 /* Main SYSCLK frequency in Hz (200MHz) */
1576 #define SYSCLK_FRQ 200000000ULL
1577
1578 static void aspeed_minibmc_machine_init(MachineState *machine)
1579 {
1580 AspeedMachineState *bmc = ASPEED_MACHINE(machine);
1581 AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(machine);
1582 Clock *sysclk;
1583
1584 sysclk = clock_new(OBJECT(machine), "SYSCLK");
1585 clock_set_hz(sysclk, SYSCLK_FRQ);
1586
1587 bmc->soc = ASPEED_SOC(object_new(amc->soc_name));
1588 object_property_add_child(OBJECT(machine), "soc", OBJECT(bmc->soc));
1589 object_unref(OBJECT(bmc->soc));
1590 qdev_connect_clock_in(DEVICE(bmc->soc), "sysclk", sysclk);
1591
1592 object_property_set_link(OBJECT(bmc->soc), "memory",
1593 OBJECT(get_system_memory()), &error_abort);
1594 connect_serial_hds_to_uarts(bmc);
1595 qdev_realize(DEVICE(bmc->soc), NULL, &error_abort);
1596
1597 aspeed_board_init_flashes(&bmc->soc->fmc,
1598 bmc->fmc_model ? bmc->fmc_model : amc->fmc_model,
1599 amc->num_cs,
1600 0);
1601
1602 aspeed_board_init_flashes(&bmc->soc->spi[0],
1603 bmc->spi_model ? bmc->spi_model : amc->spi_model,
1604 amc->num_cs, amc->num_cs);
1605
1606 aspeed_board_init_flashes(&bmc->soc->spi[1],
1607 bmc->spi_model ? bmc->spi_model : amc->spi_model,
1608 amc->num_cs, (amc->num_cs * 2));
1609
1610 if (amc->i2c_init) {
1611 amc->i2c_init(bmc);
1612 }
1613
1614 armv7m_load_kernel(ARM_CPU(first_cpu),
1615 machine->kernel_filename,
1616 0,
1617 AST1030_INTERNAL_FLASH_SIZE);
1618 }
1619
1620 static void ast1030_evb_i2c_init(AspeedMachineState *bmc)
1621 {
1622 AspeedSoCState *soc = bmc->soc;
1623
1624 /* U10 24C08 connects to SDA/SCL Group 1 by default */
1625 uint8_t *eeprom_buf = g_malloc0(32 * 1024);
1626 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 0), 0x50, eeprom_buf);
1627
1628 /* U11 LM75 connects to SDA/SCL Group 2 by default */
1629 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1), "tmp105", 0x4d);
1630 }
1631
1632 static void aspeed_minibmc_machine_ast1030_evb_class_init(ObjectClass *oc,
1633 void *data)
1634 {
1635 MachineClass *mc = MACHINE_CLASS(oc);
1636 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1637
1638 mc->desc = "Aspeed AST1030 MiniBMC (Cortex-M4)";
1639 amc->soc_name = "ast1030-a1";
1640 amc->hw_strap1 = 0;
1641 amc->hw_strap2 = 0;
1642 mc->init = aspeed_minibmc_machine_init;
1643 amc->i2c_init = ast1030_evb_i2c_init;
1644 mc->default_ram_size = 0;
1645 amc->fmc_model = "sst25vf032b";
1646 amc->spi_model = "sst25vf032b";
1647 amc->num_cs = 2;
1648 amc->macs_mask = 0;
1649 aspeed_machine_class_init_cpus_defaults(mc);
1650 }
1651
1652 #ifdef TARGET_AARCH64
1653 static void ast2700_evb_i2c_init(AspeedMachineState *bmc)
1654 {
1655 AspeedSoCState *soc = bmc->soc;
1656
1657 /* LM75 is compatible with TMP105 driver */
1658 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 0),
1659 TYPE_TMP105, 0x4d);
1660 }
1661
1662 static void aspeed_machine_ast2700_evb_class_init(ObjectClass *oc, void *data)
1663 {
1664 MachineClass *mc = MACHINE_CLASS(oc);
1665 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1666
1667 mc->desc = "Aspeed AST2700 EVB (Cortex-A35)";
1668 amc->soc_name = "ast2700-a0";
1669 amc->hw_strap1 = AST2700_EVB_HW_STRAP1;
1670 amc->hw_strap2 = AST2700_EVB_HW_STRAP2;
1671 amc->fmc_model = "w25q01jvq";
1672 amc->spi_model = "w25q512jv";
1673 amc->num_cs = 2;
1674 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON | ASPEED_MAC2_ON;
1675 amc->uart_default = ASPEED_DEV_UART12;
1676 amc->i2c_init = ast2700_evb_i2c_init;
1677 mc->default_ram_size = 1 * GiB;
1678 aspeed_machine_class_init_cpus_defaults(mc);
1679 }
1680 #endif
1681
1682 static void aspeed_machine_qcom_dc_scm_v1_class_init(ObjectClass *oc,
1683 void *data)
1684 {
1685 MachineClass *mc = MACHINE_CLASS(oc);
1686 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1687
1688 mc->desc = "Qualcomm DC-SCM V1 BMC (Cortex A7)";
1689 amc->soc_name = "ast2600-a3";
1690 amc->hw_strap1 = QCOM_DC_SCM_V1_BMC_HW_STRAP1;
1691 amc->hw_strap2 = QCOM_DC_SCM_V1_BMC_HW_STRAP2;
1692 amc->fmc_model = "n25q512a";
1693 amc->spi_model = "n25q512a";
1694 amc->num_cs = 2;
1695 amc->macs_mask = ASPEED_MAC2_ON | ASPEED_MAC3_ON;
1696 amc->i2c_init = qcom_dc_scm_bmc_i2c_init;
1697 mc->default_ram_size = 1 * GiB;
1698 aspeed_machine_class_init_cpus_defaults(mc);
1699 };
1700
1701 static void aspeed_machine_qcom_firework_class_init(ObjectClass *oc,
1702 void *data)
1703 {
1704 MachineClass *mc = MACHINE_CLASS(oc);
1705 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1706
1707 mc->desc = "Qualcomm DC-SCM V1/Firework BMC (Cortex A7)";
1708 amc->soc_name = "ast2600-a3";
1709 amc->hw_strap1 = QCOM_DC_SCM_V1_BMC_HW_STRAP1;
1710 amc->hw_strap2 = QCOM_DC_SCM_V1_BMC_HW_STRAP2;
1711 amc->fmc_model = "n25q512a";
1712 amc->spi_model = "n25q512a";
1713 amc->num_cs = 2;
1714 amc->macs_mask = ASPEED_MAC2_ON | ASPEED_MAC3_ON;
1715 amc->i2c_init = qcom_dc_scm_firework_i2c_init;
1716 mc->default_ram_size = 1 * GiB;
1717 aspeed_machine_class_init_cpus_defaults(mc);
1718 };
1719
1720 static const TypeInfo aspeed_machine_types[] = {
1721 {
1722 .name = MACHINE_TYPE_NAME("palmetto-bmc"),
1723 .parent = TYPE_ASPEED_MACHINE,
1724 .class_init = aspeed_machine_palmetto_class_init,
1725 }, {
1726 .name = MACHINE_TYPE_NAME("supermicrox11-bmc"),
1727 .parent = TYPE_ASPEED_MACHINE,
1728 .class_init = aspeed_machine_supermicrox11_bmc_class_init,
1729 }, {
1730 .name = MACHINE_TYPE_NAME("supermicro-x11spi-bmc"),
1731 .parent = TYPE_ASPEED_MACHINE,
1732 .class_init = aspeed_machine_supermicro_x11spi_bmc_class_init,
1733 }, {
1734 .name = MACHINE_TYPE_NAME("ast2500-evb"),
1735 .parent = TYPE_ASPEED_MACHINE,
1736 .class_init = aspeed_machine_ast2500_evb_class_init,
1737 }, {
1738 .name = MACHINE_TYPE_NAME("romulus-bmc"),
1739 .parent = TYPE_ASPEED_MACHINE,
1740 .class_init = aspeed_machine_romulus_class_init,
1741 }, {
1742 .name = MACHINE_TYPE_NAME("sonorapass-bmc"),
1743 .parent = TYPE_ASPEED_MACHINE,
1744 .class_init = aspeed_machine_sonorapass_class_init,
1745 }, {
1746 .name = MACHINE_TYPE_NAME("witherspoon-bmc"),
1747 .parent = TYPE_ASPEED_MACHINE,
1748 .class_init = aspeed_machine_witherspoon_class_init,
1749 }, {
1750 .name = MACHINE_TYPE_NAME("ast2600-evb"),
1751 .parent = TYPE_ASPEED_MACHINE,
1752 .class_init = aspeed_machine_ast2600_evb_class_init,
1753 }, {
1754 .name = MACHINE_TYPE_NAME("yosemitev2-bmc"),
1755 .parent = TYPE_ASPEED_MACHINE,
1756 .class_init = aspeed_machine_yosemitev2_class_init,
1757 }, {
1758 .name = MACHINE_TYPE_NAME("tacoma-bmc"),
1759 .parent = TYPE_ASPEED_MACHINE,
1760 .class_init = aspeed_machine_tacoma_class_init,
1761 }, {
1762 .name = MACHINE_TYPE_NAME("tiogapass-bmc"),
1763 .parent = TYPE_ASPEED_MACHINE,
1764 .class_init = aspeed_machine_tiogapass_class_init,
1765 }, {
1766 .name = MACHINE_TYPE_NAME("g220a-bmc"),
1767 .parent = TYPE_ASPEED_MACHINE,
1768 .class_init = aspeed_machine_g220a_class_init,
1769 }, {
1770 .name = MACHINE_TYPE_NAME("qcom-dc-scm-v1-bmc"),
1771 .parent = TYPE_ASPEED_MACHINE,
1772 .class_init = aspeed_machine_qcom_dc_scm_v1_class_init,
1773 }, {
1774 .name = MACHINE_TYPE_NAME("qcom-firework-bmc"),
1775 .parent = TYPE_ASPEED_MACHINE,
1776 .class_init = aspeed_machine_qcom_firework_class_init,
1777 }, {
1778 .name = MACHINE_TYPE_NAME("fp5280g2-bmc"),
1779 .parent = TYPE_ASPEED_MACHINE,
1780 .class_init = aspeed_machine_fp5280g2_class_init,
1781 }, {
1782 .name = MACHINE_TYPE_NAME("quanta-q71l-bmc"),
1783 .parent = TYPE_ASPEED_MACHINE,
1784 .class_init = aspeed_machine_quanta_q71l_class_init,
1785 }, {
1786 .name = MACHINE_TYPE_NAME("rainier-bmc"),
1787 .parent = TYPE_ASPEED_MACHINE,
1788 .class_init = aspeed_machine_rainier_class_init,
1789 }, {
1790 .name = MACHINE_TYPE_NAME("fuji-bmc"),
1791 .parent = TYPE_ASPEED_MACHINE,
1792 .class_init = aspeed_machine_fuji_class_init,
1793 }, {
1794 .name = MACHINE_TYPE_NAME("bletchley-bmc"),
1795 .parent = TYPE_ASPEED_MACHINE,
1796 .class_init = aspeed_machine_bletchley_class_init,
1797 }, {
1798 .name = MACHINE_TYPE_NAME("fby35-bmc"),
1799 .parent = MACHINE_TYPE_NAME("ast2600-evb"),
1800 .class_init = aspeed_machine_fby35_class_init,
1801 }, {
1802 .name = MACHINE_TYPE_NAME("ast1030-evb"),
1803 .parent = TYPE_ASPEED_MACHINE,
1804 .class_init = aspeed_minibmc_machine_ast1030_evb_class_init,
1805 #ifdef TARGET_AARCH64
1806 }, {
1807 .name = MACHINE_TYPE_NAME("ast2700-evb"),
1808 .parent = TYPE_ASPEED_MACHINE,
1809 .class_init = aspeed_machine_ast2700_evb_class_init,
1810 #endif
1811 }, {
1812 .name = TYPE_ASPEED_MACHINE,
1813 .parent = TYPE_MACHINE,
1814 .instance_size = sizeof(AspeedMachineState),
1815 .instance_init = aspeed_machine_instance_init,
1816 .class_size = sizeof(AspeedMachineClass),
1817 .class_init = aspeed_machine_class_init,
1818 .abstract = true,
1819 }
1820 };
1821
1822 DEFINE_TYPES(aspeed_machine_types)
armbru's QEMU hackery