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Merge tag 'pull-loongarch-20241016' of https://gitlab.com/gaosong/qemu into staging
[qemu/armbru.git] / hw / arm / virt-acpi-build.c
blobf76fb117adff30e6e8b3f21ee83048648d9e963a
1 /* Support for generating ACPI tables and passing them to Guests
2 *
3 * ARM virt ACPI generation
4 *
5 * Copyright (C) 2008-2010 Kevin O'Connor <kevin@koconnor.net>
6 * Copyright (C) 2006 Fabrice Bellard
7 * Copyright (C) 2013 Red Hat Inc
8 *
9 * Author: Michael S. Tsirkin <mst@redhat.com>
10 *
11 * Copyright (c) 2015 HUAWEI TECHNOLOGIES CO.,LTD.
12 *
13 * Author: Shannon Zhao <zhaoshenglong@huawei.com>
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2 of the License, or
18 * (at your option) any later version.
19
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24
25 * You should have received a copy of the GNU General Public License along
26 * with this program; if not, see <http://www.gnu.org/licenses/>.
27 */
28
29 #include "qemu/osdep.h"
30 #include "qapi/error.h"
31 #include "qemu/bitmap.h"
32 #include "qemu/error-report.h"
33 #include "trace.h"
34 #include "hw/core/cpu.h"
35 #include "hw/acpi/acpi-defs.h"
36 #include "hw/acpi/acpi.h"
37 #include "hw/nvram/fw_cfg_acpi.h"
38 #include "hw/acpi/bios-linker-loader.h"
39 #include "hw/acpi/aml-build.h"
40 #include "hw/acpi/utils.h"
41 #include "hw/acpi/pci.h"
42 #include "hw/acpi/memory_hotplug.h"
43 #include "hw/acpi/generic_event_device.h"
44 #include "hw/acpi/tpm.h"
45 #include "hw/acpi/hmat.h"
46 #include "hw/pci/pcie_host.h"
47 #include "hw/pci/pci.h"
48 #include "hw/pci/pci_bus.h"
49 #include "hw/pci-host/gpex.h"
50 #include "hw/arm/virt.h"
51 #include "hw/intc/arm_gicv3_its_common.h"
52 #include "hw/mem/nvdimm.h"
53 #include "hw/platform-bus.h"
54 #include "sysemu/numa.h"
55 #include "sysemu/reset.h"
56 #include "sysemu/tpm.h"
57 #include "migration/vmstate.h"
58 #include "hw/acpi/ghes.h"
59 #include "hw/acpi/viot.h"
60 #include "hw/acpi/acpi_generic_initiator.h"
61 #include "hw/virtio/virtio-acpi.h"
62 #include "target/arm/multiprocessing.h"
63
64 #define ARM_SPI_BASE 32
65
66 #define ACPI_BUILD_TABLE_SIZE 0x20000
67
68 static void acpi_dsdt_add_cpus(Aml *scope, VirtMachineState *vms)
69 {
70 MachineState *ms = MACHINE(vms);
71 uint16_t i;
72
73 for (i = 0; i < ms->smp.cpus; i++) {
74 Aml *dev = aml_device("C%.03X", i);
75 aml_append(dev, aml_name_decl("_HID", aml_string("ACPI0007")));
76 aml_append(dev, aml_name_decl("_UID", aml_int(i)));
77 aml_append(scope, dev);
78 }
79 }
80
81 static void acpi_dsdt_add_uart(Aml *scope, const MemMapEntry *uart_memmap,
82 uint32_t uart_irq, int uartidx)
83 {
84 Aml *dev = aml_device("COM%d", uartidx);
85 aml_append(dev, aml_name_decl("_HID", aml_string("ARMH0011")));
86 aml_append(dev, aml_name_decl("_UID", aml_int(uartidx)));
87
88 Aml *crs = aml_resource_template();
89 aml_append(crs, aml_memory32_fixed(uart_memmap->base,
90 uart_memmap->size, AML_READ_WRITE));
91 aml_append(crs,
92 aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
93 AML_EXCLUSIVE, &uart_irq, 1));
94 aml_append(dev, aml_name_decl("_CRS", crs));
95
96 aml_append(scope, dev);
97 }
98
99 static void acpi_dsdt_add_flash(Aml *scope, const MemMapEntry *flash_memmap)
100 {
101 Aml *dev, *crs;
102 hwaddr base = flash_memmap->base;
103 hwaddr size = flash_memmap->size / 2;
104
105 dev = aml_device("FLS0");
106 aml_append(dev, aml_name_decl("_HID", aml_string("LNRO0015")));
107 aml_append(dev, aml_name_decl("_UID", aml_int(0)));
108
109 crs = aml_resource_template();
110 aml_append(crs, aml_memory32_fixed(base, size, AML_READ_WRITE));
111 aml_append(dev, aml_name_decl("_CRS", crs));
112 aml_append(scope, dev);
113
114 dev = aml_device("FLS1");
115 aml_append(dev, aml_name_decl("_HID", aml_string("LNRO0015")));
116 aml_append(dev, aml_name_decl("_UID", aml_int(1)));
117 crs = aml_resource_template();
118 aml_append(crs, aml_memory32_fixed(base + size, size, AML_READ_WRITE));
119 aml_append(dev, aml_name_decl("_CRS", crs));
120 aml_append(scope, dev);
121 }
122
123 static void acpi_dsdt_add_pci(Aml *scope, const MemMapEntry *memmap,
124 uint32_t irq, VirtMachineState *vms)
125 {
126 int ecam_id = VIRT_ECAM_ID(vms->highmem_ecam);
127 struct GPEXConfig cfg = {
128 .mmio32 = memmap[VIRT_PCIE_MMIO],
129 .pio = memmap[VIRT_PCIE_PIO],
130 .ecam = memmap[ecam_id],
131 .irq = irq,
132 .bus = vms->bus,
133 };
134
135 if (vms->highmem_mmio) {
136 cfg.mmio64 = memmap[VIRT_HIGH_PCIE_MMIO];
137 }
138
139 acpi_dsdt_add_gpex(scope, &cfg);
140 }
141
142 static void acpi_dsdt_add_gpio(Aml *scope, const MemMapEntry *gpio_memmap,
143 uint32_t gpio_irq)
144 {
145 Aml *dev = aml_device("GPO0");
146 aml_append(dev, aml_name_decl("_HID", aml_string("ARMH0061")));
147 aml_append(dev, aml_name_decl("_UID", aml_int(0)));
148
149 Aml *crs = aml_resource_template();
150 aml_append(crs, aml_memory32_fixed(gpio_memmap->base, gpio_memmap->size,
151 AML_READ_WRITE));
152 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
153 AML_EXCLUSIVE, &gpio_irq, 1));
154 aml_append(dev, aml_name_decl("_CRS", crs));
155
156 Aml *aei = aml_resource_template();
157
158 const uint32_t pin = GPIO_PIN_POWER_BUTTON;
159 aml_append(aei, aml_gpio_int(AML_CONSUMER, AML_EDGE, AML_ACTIVE_HIGH,
160 AML_EXCLUSIVE, AML_PULL_UP, 0, &pin, 1,
161 "GPO0", NULL, 0));
162 aml_append(dev, aml_name_decl("_AEI", aei));
163
164 /* _E03 is handle for power button */
165 Aml *method = aml_method("_E03", 0, AML_NOTSERIALIZED);
166 aml_append(method, aml_notify(aml_name(ACPI_POWER_BUTTON_DEVICE),
167 aml_int(0x80)));
168 aml_append(dev, method);
169 aml_append(scope, dev);
170 }
171
172 #ifdef CONFIG_TPM
173 static void acpi_dsdt_add_tpm(Aml *scope, VirtMachineState *vms)
174 {
175 PlatformBusDevice *pbus = PLATFORM_BUS_DEVICE(vms->platform_bus_dev);
176 hwaddr pbus_base = vms->memmap[VIRT_PLATFORM_BUS].base;
177 SysBusDevice *sbdev = SYS_BUS_DEVICE(tpm_find());
178 MemoryRegion *sbdev_mr;
179 hwaddr tpm_base;
180
181 if (!sbdev) {
182 return;
183 }
184
185 tpm_base = platform_bus_get_mmio_addr(pbus, sbdev, 0);
186 assert(tpm_base != -1);
187
188 tpm_base += pbus_base;
189
190 sbdev_mr = sysbus_mmio_get_region(sbdev, 0);
191
192 Aml *dev = aml_device("TPM0");
193 aml_append(dev, aml_name_decl("_HID", aml_string("MSFT0101")));
194 aml_append(dev, aml_name_decl("_STR", aml_string("TPM 2.0 Device")));
195 aml_append(dev, aml_name_decl("_UID", aml_int(0)));
196
197 Aml *crs = aml_resource_template();
198 aml_append(crs,
199 aml_memory32_fixed(tpm_base,
200 (uint32_t)memory_region_size(sbdev_mr),
201 AML_READ_WRITE));
202 aml_append(dev, aml_name_decl("_CRS", crs));
203 aml_append(scope, dev);
204 }
205 #endif
206
207 #define ID_MAPPING_ENTRY_SIZE 20
208 #define SMMU_V3_ENTRY_SIZE 68
209 #define ROOT_COMPLEX_ENTRY_SIZE 36
210 #define IORT_NODE_OFFSET 48
211
212 /*
213 * Append an ID mapping entry as described by "Table 4 ID mapping format" in
214 * "IO Remapping Table System Software on ARM Platforms", Chapter 3.
215 * Document number: ARM DEN 0049E.f, Apr 2024
216 *
217 * Note that @id_count gets internally subtracted by one, following the spec.
218 */
219 static void build_iort_id_mapping(GArray *table_data, uint32_t input_base,
220 uint32_t id_count, uint32_t out_ref)
221 {
222 build_append_int_noprefix(table_data, input_base, 4); /* Input base */
223 /* Number of IDs - The number of IDs in the range minus one */
224 build_append_int_noprefix(table_data, id_count - 1, 4);
225 build_append_int_noprefix(table_data, input_base, 4); /* Output base */
226 build_append_int_noprefix(table_data, out_ref, 4); /* Output Reference */
227 /* Flags */
228 build_append_int_noprefix(table_data, 0 /* Single mapping (disabled) */, 4);
229 }
230
231 struct AcpiIortIdMapping {
232 uint32_t input_base;
233 uint32_t id_count;
234 };
235 typedef struct AcpiIortIdMapping AcpiIortIdMapping;
236
237 /* Build the iort ID mapping to SMMUv3 for a given PCI host bridge */
238 static int
239 iort_host_bridges(Object *obj, void *opaque)
240 {
241 GArray *idmap_blob = opaque;
242
243 if (object_dynamic_cast(obj, TYPE_PCI_HOST_BRIDGE)) {
244 PCIBus *bus = PCI_HOST_BRIDGE(obj)->bus;
245
246 if (bus && !pci_bus_bypass_iommu(bus)) {
247 int min_bus, max_bus;
248
249 pci_bus_range(bus, &min_bus, &max_bus);
250
251 AcpiIortIdMapping idmap = {
252 .input_base = min_bus << 8,
253 .id_count = (max_bus - min_bus + 1) << 8,
254 };
255 g_array_append_val(idmap_blob, idmap);
256 }
257 }
258
259 return 0;
260 }
261
262 static int iort_idmap_compare(gconstpointer a, gconstpointer b)
263 {
264 AcpiIortIdMapping *idmap_a = (AcpiIortIdMapping *)a;
265 AcpiIortIdMapping *idmap_b = (AcpiIortIdMapping *)b;
266
267 return idmap_a->input_base - idmap_b->input_base;
268 }
269
270 /*
271 * Input Output Remapping Table (IORT)
272 * Conforms to "IO Remapping Table System Software on ARM Platforms",
273 * Document number: ARM DEN 0049E.b, Feb 2021
274 */
275 static void
276 build_iort(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
277 {
278 int i, nb_nodes, rc_mapping_count;
279 size_t node_size, smmu_offset = 0;
280 AcpiIortIdMapping *idmap;
281 uint32_t id = 0;
282 GArray *smmu_idmaps = g_array_new(false, true, sizeof(AcpiIortIdMapping));
283 GArray *its_idmaps = g_array_new(false, true, sizeof(AcpiIortIdMapping));
284
285 AcpiTable table = { .sig = "IORT", .rev = 3, .oem_id = vms->oem_id,
286 .oem_table_id = vms->oem_table_id };
287 /* Table 2 The IORT */
288 acpi_table_begin(&table, table_data);
289
290 if (vms->iommu == VIRT_IOMMU_SMMUV3) {
291 AcpiIortIdMapping next_range = {0};
292
293 object_child_foreach_recursive(object_get_root(),
294 iort_host_bridges, smmu_idmaps);
295
296 /* Sort the smmu idmap by input_base */
297 g_array_sort(smmu_idmaps, iort_idmap_compare);
298
299 /*
300 * Split the whole RIDs by mapping from RC to SMMU,
301 * build the ID mapping from RC to ITS directly.
302 */
303 for (i = 0; i < smmu_idmaps->len; i++) {
304 idmap = &g_array_index(smmu_idmaps, AcpiIortIdMapping, i);
305
306 if (next_range.input_base < idmap->input_base) {
307 next_range.id_count = idmap->input_base - next_range.input_base;
308 g_array_append_val(its_idmaps, next_range);
309 }
310
311 next_range.input_base = idmap->input_base + idmap->id_count;
312 }
313
314 /* Append the last RC -> ITS ID mapping */
315 if (next_range.input_base < 0x10000) {
316 next_range.id_count = 0x10000 - next_range.input_base;
317 g_array_append_val(its_idmaps, next_range);
318 }
319
320 nb_nodes = 3; /* RC, ITS, SMMUv3 */
321 rc_mapping_count = smmu_idmaps->len + its_idmaps->len;
322 } else {
323 nb_nodes = 2; /* RC, ITS */
324 rc_mapping_count = 1;
325 }
326 /* Number of IORT Nodes */
327 build_append_int_noprefix(table_data, nb_nodes, 4);
328
329 /* Offset to Array of IORT Nodes */
330 build_append_int_noprefix(table_data, IORT_NODE_OFFSET, 4);
331 build_append_int_noprefix(table_data, 0, 4); /* Reserved */
332
333 /* Table 12 ITS Group Format */
334 build_append_int_noprefix(table_data, 0 /* ITS Group */, 1); /* Type */
335 node_size = 20 /* fixed header size */ + 4 /* 1 GIC ITS Identifier */;
336 build_append_int_noprefix(table_data, node_size, 2); /* Length */
337 build_append_int_noprefix(table_data, 1, 1); /* Revision */
338 build_append_int_noprefix(table_data, id++, 4); /* Identifier */
339 build_append_int_noprefix(table_data, 0, 4); /* Number of ID mappings */
340 build_append_int_noprefix(table_data, 0, 4); /* Reference to ID Array */
341 build_append_int_noprefix(table_data, 1, 4); /* Number of ITSs */
342 /* GIC ITS Identifier Array */
343 build_append_int_noprefix(table_data, 0 /* MADT translation_id */, 4);
344
345 if (vms->iommu == VIRT_IOMMU_SMMUV3) {
346 int irq = vms->irqmap[VIRT_SMMU] + ARM_SPI_BASE;
347
348 smmu_offset = table_data->len - table.table_offset;
349 /* Table 9 SMMUv3 Format */
350 build_append_int_noprefix(table_data, 4 /* SMMUv3 */, 1); /* Type */
351 node_size = SMMU_V3_ENTRY_SIZE + ID_MAPPING_ENTRY_SIZE;
352 build_append_int_noprefix(table_data, node_size, 2); /* Length */
353 build_append_int_noprefix(table_data, 4, 1); /* Revision */
354 build_append_int_noprefix(table_data, id++, 4); /* Identifier */
355 build_append_int_noprefix(table_data, 1, 4); /* Number of ID mappings */
356 /* Reference to ID Array */
357 build_append_int_noprefix(table_data, SMMU_V3_ENTRY_SIZE, 4);
358 /* Base address */
359 build_append_int_noprefix(table_data, vms->memmap[VIRT_SMMU].base, 8);
360 /* Flags */
361 build_append_int_noprefix(table_data, 1 /* COHACC Override */, 4);
362 build_append_int_noprefix(table_data, 0, 4); /* Reserved */
363 build_append_int_noprefix(table_data, 0, 8); /* VATOS address */
364 /* Model */
365 build_append_int_noprefix(table_data, 0 /* Generic SMMU-v3 */, 4);
366 build_append_int_noprefix(table_data, irq, 4); /* Event */
367 build_append_int_noprefix(table_data, irq + 1, 4); /* PRI */
368 build_append_int_noprefix(table_data, irq + 3, 4); /* GERR */
369 build_append_int_noprefix(table_data, irq + 2, 4); /* Sync */
370 build_append_int_noprefix(table_data, 0, 4); /* Proximity domain */
371 /* DeviceID mapping index (ignored since interrupts are GSIV based) */
372 build_append_int_noprefix(table_data, 0, 4);
373
374 /* output IORT node is the ITS group node (the first node) */
375 build_iort_id_mapping(table_data, 0, 0x10000, IORT_NODE_OFFSET);
376 }
377
378 /* Table 17 Root Complex Node */
379 build_append_int_noprefix(table_data, 2 /* Root complex */, 1); /* Type */
380 node_size = ROOT_COMPLEX_ENTRY_SIZE +
381 ID_MAPPING_ENTRY_SIZE * rc_mapping_count;
382 build_append_int_noprefix(table_data, node_size, 2); /* Length */
383 build_append_int_noprefix(table_data, 3, 1); /* Revision */
384 build_append_int_noprefix(table_data, id++, 4); /* Identifier */
385 /* Number of ID mappings */
386 build_append_int_noprefix(table_data, rc_mapping_count, 4);
387 /* Reference to ID Array */
388 build_append_int_noprefix(table_data, ROOT_COMPLEX_ENTRY_SIZE, 4);
389
390 /* Table 14 Memory access properties */
391 /* CCA: Cache Coherent Attribute */
392 build_append_int_noprefix(table_data, 1 /* fully coherent */, 4);
393 build_append_int_noprefix(table_data, 0, 1); /* AH: Note Allocation Hints */
394 build_append_int_noprefix(table_data, 0, 2); /* Reserved */
395 /* Table 15 Memory Access Flags */
396 build_append_int_noprefix(table_data, 0x3 /* CCA = CPM = DACS = 1 */, 1);
397
398 build_append_int_noprefix(table_data, 0, 4); /* ATS Attribute */
399 /* MCFG pci_segment */
400 build_append_int_noprefix(table_data, 0, 4); /* PCI Segment number */
401
402 /* Memory address size limit */
403 build_append_int_noprefix(table_data, 64, 1);
404
405 build_append_int_noprefix(table_data, 0, 3); /* Reserved */
406
407 /* Output Reference */
408 if (vms->iommu == VIRT_IOMMU_SMMUV3) {
409 AcpiIortIdMapping *range;
410
411 /* translated RIDs connect to SMMUv3 node: RC -> SMMUv3 -> ITS */
412 for (i = 0; i < smmu_idmaps->len; i++) {
413 range = &g_array_index(smmu_idmaps, AcpiIortIdMapping, i);
414 /* output IORT node is the smmuv3 node */
415 build_iort_id_mapping(table_data, range->input_base,
416 range->id_count, smmu_offset);
417 }
418
419 /* bypassed RIDs connect to ITS group node directly: RC -> ITS */
420 for (i = 0; i < its_idmaps->len; i++) {
421 range = &g_array_index(its_idmaps, AcpiIortIdMapping, i);
422 /* output IORT node is the ITS group node (the first node) */
423 build_iort_id_mapping(table_data, range->input_base,
424 range->id_count, IORT_NODE_OFFSET);
425 }
426 } else {
427 /* output IORT node is the ITS group node (the first node) */
428 build_iort_id_mapping(table_data, 0, 0x10000, IORT_NODE_OFFSET);
429 }
430
431 acpi_table_end(linker, &table);
432 g_array_free(smmu_idmaps, true);
433 g_array_free(its_idmaps, true);
434 }
435
436 /*
437 * Serial Port Console Redirection Table (SPCR)
438 * Rev: 1.07
439 */
440 static void
441 spcr_setup(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
442 {
443 AcpiSpcrData serial = {
444 .interface_type = 3, /* ARM PL011 UART */
445 .base_addr.id = AML_AS_SYSTEM_MEMORY,
446 .base_addr.width = 32,
447 .base_addr.offset = 0,
448 .base_addr.size = 3,
449 .base_addr.addr = vms->memmap[VIRT_UART0].base,
450 .interrupt_type = (1 << 3),/* Bit[3] ARMH GIC interrupt*/
451 .pc_interrupt = 0, /* IRQ */
452 .interrupt = (vms->irqmap[VIRT_UART0] + ARM_SPI_BASE),
453 .baud_rate = 3, /* 9600 */
454 .parity = 0, /* No Parity */
455 .stop_bits = 1, /* 1 Stop bit */
456 .flow_control = 1 << 1, /* RTS/CTS hardware flow control */
457 .terminal_type = 0, /* VT100 */
458 .language = 0, /* Language */
459 .pci_device_id = 0xffff, /* not a PCI device*/
460 .pci_vendor_id = 0xffff, /* not a PCI device*/
461 .pci_bus = 0,
462 .pci_device = 0,
463 .pci_function = 0,
464 .pci_flags = 0,
465 .pci_segment = 0,
466 };
467
468 build_spcr(table_data, linker, &serial, 2, vms->oem_id, vms->oem_table_id);
469 }
470
471 /*
472 * ACPI spec, Revision 5.1
473 * 5.2.16 System Resource Affinity Table (SRAT)
474 */
475 static void
476 build_srat(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
477 {
478 int i;
479 uint64_t mem_base;
480 MachineClass *mc = MACHINE_GET_CLASS(vms);
481 MachineState *ms = MACHINE(vms);
482 const CPUArchIdList *cpu_list = mc->possible_cpu_arch_ids(ms);
483 AcpiTable table = { .sig = "SRAT", .rev = 3, .oem_id = vms->oem_id,
484 .oem_table_id = vms->oem_table_id };
485
486 acpi_table_begin(&table, table_data);
487 build_append_int_noprefix(table_data, 1, 4); /* Reserved */
488 build_append_int_noprefix(table_data, 0, 8); /* Reserved */
489
490 for (i = 0; i < cpu_list->len; ++i) {
491 uint32_t nodeid = cpu_list->cpus[i].props.node_id;
492 /*
493 * 5.2.16.4 GICC Affinity Structure
494 */
495 build_append_int_noprefix(table_data, 3, 1); /* Type */
496 build_append_int_noprefix(table_data, 18, 1); /* Length */
497 build_append_int_noprefix(table_data, nodeid, 4); /* Proximity Domain */
498 build_append_int_noprefix(table_data, i, 4); /* ACPI Processor UID */
499 /* Flags, Table 5-76 */
500 build_append_int_noprefix(table_data, 1 /* Enabled */, 4);
501 build_append_int_noprefix(table_data, 0, 4); /* Clock Domain */
502 }
503
504 mem_base = vms->memmap[VIRT_MEM].base;
505 for (i = 0; i < ms->numa_state->num_nodes; ++i) {
506 if (ms->numa_state->nodes[i].node_mem > 0) {
507 build_srat_memory(table_data, mem_base,
508 ms->numa_state->nodes[i].node_mem, i,
509 MEM_AFFINITY_ENABLED);
510 mem_base += ms->numa_state->nodes[i].node_mem;
511 }
512 }
513
514 build_srat_generic_pci_initiator(table_data);
515
516 if (ms->nvdimms_state->is_enabled) {
517 nvdimm_build_srat(table_data);
518 }
519
520 if (ms->device_memory) {
521 build_srat_memory(table_data, ms->device_memory->base,
522 memory_region_size(&ms->device_memory->mr),
523 ms->numa_state->num_nodes - 1,
524 MEM_AFFINITY_HOTPLUGGABLE | MEM_AFFINITY_ENABLED);
525 }
526
527 acpi_table_end(linker, &table);
528 }
529
530 /*
531 * ACPI spec, Revision 6.5
532 * 5.2.25 Generic Timer Description Table (GTDT)
533 */
534 static void
535 build_gtdt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
536 {
537 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms);
538 /*
539 * Table 5-117 Flag Definitions
540 * set only "Timer interrupt Mode" and assume "Timer Interrupt
541 * polarity" bit as '0: Interrupt is Active high'
542 */
543 uint32_t irqflags = vmc->claim_edge_triggered_timers ?
544 1 : /* Interrupt is Edge triggered */
545 0; /* Interrupt is Level triggered */
546 AcpiTable table = { .sig = "GTDT", .rev = 3, .oem_id = vms->oem_id,
547 .oem_table_id = vms->oem_table_id };
548
549 acpi_table_begin(&table, table_data);
550
551 /* CntControlBase Physical Address */
552 build_append_int_noprefix(table_data, 0xFFFFFFFFFFFFFFFF, 8);
553 build_append_int_noprefix(table_data, 0, 4); /* Reserved */
554 /*
555 * FIXME: clarify comment:
556 * The interrupt values are the same with the device tree when adding 16
557 */
558 /* Secure EL1 timer GSIV */
559 build_append_int_noprefix(table_data, ARCH_TIMER_S_EL1_IRQ, 4);
560 /* Secure EL1 timer Flags */
561 build_append_int_noprefix(table_data, irqflags, 4);
562 /* Non-Secure EL1 timer GSIV */
563 build_append_int_noprefix(table_data, ARCH_TIMER_NS_EL1_IRQ, 4);
564 /* Non-Secure EL1 timer Flags */
565 build_append_int_noprefix(table_data, irqflags |
566 1UL << 2, /* Always-on Capability */
567 4);
568 /* Virtual timer GSIV */
569 build_append_int_noprefix(table_data, ARCH_TIMER_VIRT_IRQ, 4);
570 /* Virtual Timer Flags */
571 build_append_int_noprefix(table_data, irqflags, 4);
572 /* Non-Secure EL2 timer GSIV */
573 build_append_int_noprefix(table_data, ARCH_TIMER_NS_EL2_IRQ, 4);
574 /* Non-Secure EL2 timer Flags */
575 build_append_int_noprefix(table_data, irqflags, 4);
576 /* CntReadBase Physical address */
577 build_append_int_noprefix(table_data, 0xFFFFFFFFFFFFFFFF, 8);
578 /* Platform Timer Count */
579 build_append_int_noprefix(table_data, 0, 4);
580 /* Platform Timer Offset */
581 build_append_int_noprefix(table_data, 0, 4);
582 if (vms->ns_el2_virt_timer_irq) {
583 /* Virtual EL2 Timer GSIV */
584 build_append_int_noprefix(table_data, ARCH_TIMER_NS_EL2_VIRT_IRQ, 4);
585 /* Virtual EL2 Timer Flags */
586 build_append_int_noprefix(table_data, irqflags, 4);
587 } else {
588 build_append_int_noprefix(table_data, 0, 4);
589 build_append_int_noprefix(table_data, 0, 4);
590 }
591 acpi_table_end(linker, &table);
592 }
593
594 /* Debug Port Table 2 (DBG2) */
595 static void
596 build_dbg2(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
597 {
598 AcpiTable table = { .sig = "DBG2", .rev = 0, .oem_id = vms->oem_id,
599 .oem_table_id = vms->oem_table_id };
600 int dbg2devicelength;
601 const char name[] = "COM0";
602 const int namespace_length = sizeof(name);
603
604 acpi_table_begin(&table, table_data);
605
606 dbg2devicelength = 22 + /* BaseAddressRegister[] offset */
607 12 + /* BaseAddressRegister[] */
608 4 + /* AddressSize[] */
609 namespace_length /* NamespaceString[] */;
610
611 /* OffsetDbgDeviceInfo */
612 build_append_int_noprefix(table_data, 44, 4);
613 /* NumberDbgDeviceInfo */
614 build_append_int_noprefix(table_data, 1, 4);
615
616 /* Table 2. Debug Device Information structure format */
617 build_append_int_noprefix(table_data, 0, 1); /* Revision */
618 build_append_int_noprefix(table_data, dbg2devicelength, 2); /* Length */
619 /* NumberofGenericAddressRegisters */
620 build_append_int_noprefix(table_data, 1, 1);
621 /* NameSpaceStringLength */
622 build_append_int_noprefix(table_data, namespace_length, 2);
623 build_append_int_noprefix(table_data, 38, 2); /* NameSpaceStringOffset */
624 build_append_int_noprefix(table_data, 0, 2); /* OemDataLength */
625 /* OemDataOffset (0 means no OEM data) */
626 build_append_int_noprefix(table_data, 0, 2);
627
628 /* Port Type */
629 build_append_int_noprefix(table_data, 0x8000 /* Serial */, 2);
630 /* Port Subtype */
631 build_append_int_noprefix(table_data, 0x3 /* ARM PL011 UART */, 2);
632 build_append_int_noprefix(table_data, 0, 2); /* Reserved */
633 /* BaseAddressRegisterOffset */
634 build_append_int_noprefix(table_data, 22, 2);
635 /* AddressSizeOffset */
636 build_append_int_noprefix(table_data, 34, 2);
637
638 /* BaseAddressRegister[] */
639 build_append_gas(table_data, AML_AS_SYSTEM_MEMORY, 32, 0, 3,
640 vms->memmap[VIRT_UART0].base);
641
642 /* AddressSize[] */
643 build_append_int_noprefix(table_data,
644 vms->memmap[VIRT_UART0].size, 4);
645
646 /* NamespaceString[] */
647 g_array_append_vals(table_data, name, namespace_length);
648
649 acpi_table_end(linker, &table);
650 };
651
652 /*
653 * ACPI spec, Revision 6.0 Errata A
654 * 5.2.12 Multiple APIC Description Table (MADT)
655 */
656 static void build_append_gicr(GArray *table_data, uint64_t base, uint32_t size)
657 {
658 build_append_int_noprefix(table_data, 0xE, 1); /* Type */
659 build_append_int_noprefix(table_data, 16, 1); /* Length */
660 build_append_int_noprefix(table_data, 0, 2); /* Reserved */
661 /* Discovery Range Base Address */
662 build_append_int_noprefix(table_data, base, 8);
663 build_append_int_noprefix(table_data, size, 4); /* Discovery Range Length */
664 }
665
666 static void
667 build_madt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
668 {
669 int i;
670 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms);
671 const MemMapEntry *memmap = vms->memmap;
672 AcpiTable table = { .sig = "APIC", .rev = 4, .oem_id = vms->oem_id,
673 .oem_table_id = vms->oem_table_id };
674
675 acpi_table_begin(&table, table_data);
676 /* Local Interrupt Controller Address */
677 build_append_int_noprefix(table_data, 0, 4);
678 build_append_int_noprefix(table_data, 0, 4); /* Flags */
679
680 /* 5.2.12.15 GIC Distributor Structure */
681 build_append_int_noprefix(table_data, 0xC, 1); /* Type */
682 build_append_int_noprefix(table_data, 24, 1); /* Length */
683 build_append_int_noprefix(table_data, 0, 2); /* Reserved */
684 build_append_int_noprefix(table_data, 0, 4); /* GIC ID */
685 /* Physical Base Address */
686 build_append_int_noprefix(table_data, memmap[VIRT_GIC_DIST].base, 8);
687 build_append_int_noprefix(table_data, 0, 4); /* System Vector Base */
688 /* GIC version */
689 build_append_int_noprefix(table_data, vms->gic_version, 1);
690 build_append_int_noprefix(table_data, 0, 3); /* Reserved */
691
692 for (i = 0; i < MACHINE(vms)->smp.cpus; i++) {
693 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(i));
694 uint64_t physical_base_address = 0, gich = 0, gicv = 0;
695 uint32_t vgic_interrupt = vms->virt ? ARCH_GIC_MAINT_IRQ : 0;
696 uint32_t pmu_interrupt = arm_feature(&armcpu->env, ARM_FEATURE_PMU) ?
697 VIRTUAL_PMU_IRQ : 0;
698
699 if (vms->gic_version == VIRT_GIC_VERSION_2) {
700 physical_base_address = memmap[VIRT_GIC_CPU].base;
701 gicv = memmap[VIRT_GIC_VCPU].base;
702 gich = memmap[VIRT_GIC_HYP].base;
703 }
704
705 /* 5.2.12.14 GIC Structure */
706 build_append_int_noprefix(table_data, 0xB, 1); /* Type */
707 build_append_int_noprefix(table_data, 80, 1); /* Length */
708 build_append_int_noprefix(table_data, 0, 2); /* Reserved */
709 build_append_int_noprefix(table_data, i, 4); /* GIC ID */
710 build_append_int_noprefix(table_data, i, 4); /* ACPI Processor UID */
711 /* Flags */
712 build_append_int_noprefix(table_data, 1, 4); /* Enabled */
713 /* Parking Protocol Version */
714 build_append_int_noprefix(table_data, 0, 4);
715 /* Performance Interrupt GSIV */
716 build_append_int_noprefix(table_data, pmu_interrupt, 4);
717 build_append_int_noprefix(table_data, 0, 8); /* Parked Address */
718 /* Physical Base Address */
719 build_append_int_noprefix(table_data, physical_base_address, 8);
720 build_append_int_noprefix(table_data, gicv, 8); /* GICV */
721 build_append_int_noprefix(table_data, gich, 8); /* GICH */
722 /* VGIC Maintenance interrupt */
723 build_append_int_noprefix(table_data, vgic_interrupt, 4);
724 build_append_int_noprefix(table_data, 0, 8); /* GICR Base Address*/
725 /* MPIDR */
726 build_append_int_noprefix(table_data, arm_cpu_mp_affinity(armcpu), 8);
727 /* Processor Power Efficiency Class */
728 build_append_int_noprefix(table_data, 0, 1);
729 /* Reserved */
730 build_append_int_noprefix(table_data, 0, 3);
731 }
732
733 if (vms->gic_version != VIRT_GIC_VERSION_2) {
734 build_append_gicr(table_data, memmap[VIRT_GIC_REDIST].base,
735 memmap[VIRT_GIC_REDIST].size);
736 if (virt_gicv3_redist_region_count(vms) == 2) {
737 build_append_gicr(table_data, memmap[VIRT_HIGH_GIC_REDIST2].base,
738 memmap[VIRT_HIGH_GIC_REDIST2].size);
739 }
740
741 if (its_class_name() && !vmc->no_its) {
742 /*
743 * ACPI spec, Revision 6.0 Errata A
744 * (original 6.0 definition has invalid Length)
745 * 5.2.12.18 GIC ITS Structure
746 */
747 build_append_int_noprefix(table_data, 0xF, 1); /* Type */
748 build_append_int_noprefix(table_data, 20, 1); /* Length */
749 build_append_int_noprefix(table_data, 0, 2); /* Reserved */
750 build_append_int_noprefix(table_data, 0, 4); /* GIC ITS ID */
751 /* Physical Base Address */
752 build_append_int_noprefix(table_data, memmap[VIRT_GIC_ITS].base, 8);
753 build_append_int_noprefix(table_data, 0, 4); /* Reserved */
754 }
755 } else {
756 const uint16_t spi_base = vms->irqmap[VIRT_GIC_V2M] + ARM_SPI_BASE;
757
758 /* 5.2.12.16 GIC MSI Frame Structure */
759 build_append_int_noprefix(table_data, 0xD, 1); /* Type */
760 build_append_int_noprefix(table_data, 24, 1); /* Length */
761 build_append_int_noprefix(table_data, 0, 2); /* Reserved */
762 build_append_int_noprefix(table_data, 0, 4); /* GIC MSI Frame ID */
763 /* Physical Base Address */
764 build_append_int_noprefix(table_data, memmap[VIRT_GIC_V2M].base, 8);
765 build_append_int_noprefix(table_data, 1, 4); /* Flags */
766 /* SPI Count */
767 build_append_int_noprefix(table_data, NUM_GICV2M_SPIS, 2);
768 build_append_int_noprefix(table_data, spi_base, 2); /* SPI Base */
769 }
770 acpi_table_end(linker, &table);
771 }
772
773 /* FADT */
774 static void build_fadt_rev6(GArray *table_data, BIOSLinker *linker,
775 VirtMachineState *vms, unsigned dsdt_tbl_offset)
776 {
777 /* ACPI v6.3 */
778 AcpiFadtData fadt = {
779 .rev = 6,
780 .minor_ver = 3,
781 .flags = 1 << ACPI_FADT_F_HW_REDUCED_ACPI,
782 .xdsdt_tbl_offset = &dsdt_tbl_offset,
783 };
784
785 switch (vms->psci_conduit) {
786 case QEMU_PSCI_CONDUIT_DISABLED:
787 fadt.arm_boot_arch = 0;
788 break;
789 case QEMU_PSCI_CONDUIT_HVC:
790 fadt.arm_boot_arch = ACPI_FADT_ARM_PSCI_COMPLIANT |
791 ACPI_FADT_ARM_PSCI_USE_HVC;
792 break;
793 case QEMU_PSCI_CONDUIT_SMC:
794 fadt.arm_boot_arch = ACPI_FADT_ARM_PSCI_COMPLIANT;
795 break;
796 default:
797 g_assert_not_reached();
798 }
799
800 build_fadt(table_data, linker, &fadt, vms->oem_id, vms->oem_table_id);
801 }
802
803 /* DSDT */
804 static void
805 build_dsdt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
806 {
807 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms);
808 Aml *scope, *dsdt;
809 MachineState *ms = MACHINE(vms);
810 const MemMapEntry *memmap = vms->memmap;
811 const int *irqmap = vms->irqmap;
812 AcpiTable table = { .sig = "DSDT", .rev = 2, .oem_id = vms->oem_id,
813 .oem_table_id = vms->oem_table_id };
814
815 acpi_table_begin(&table, table_data);
816 dsdt = init_aml_allocator();
817
818 /* When booting the VM with UEFI, UEFI takes ownership of the RTC hardware.
819 * While UEFI can use libfdt to disable the RTC device node in the DTB that
820 * it passes to the OS, it cannot modify AML. Therefore, we won't generate
821 * the RTC ACPI device at all when using UEFI.
822 */
823 scope = aml_scope("\\_SB");
824 acpi_dsdt_add_cpus(scope, vms);
825 acpi_dsdt_add_uart(scope, &memmap[VIRT_UART0],
826 (irqmap[VIRT_UART0] + ARM_SPI_BASE), 0);
827 if (vms->second_ns_uart_present) {
828 acpi_dsdt_add_uart(scope, &memmap[VIRT_UART1],
829 (irqmap[VIRT_UART1] + ARM_SPI_BASE), 1);
830 }
831 if (vmc->acpi_expose_flash) {
832 acpi_dsdt_add_flash(scope, &memmap[VIRT_FLASH]);
833 }
834 fw_cfg_acpi_dsdt_add(scope, &memmap[VIRT_FW_CFG]);
835 virtio_acpi_dsdt_add(scope, memmap[VIRT_MMIO].base, memmap[VIRT_MMIO].size,
836 (irqmap[VIRT_MMIO] + ARM_SPI_BASE),
837 0, NUM_VIRTIO_TRANSPORTS);
838 acpi_dsdt_add_pci(scope, memmap, irqmap[VIRT_PCIE] + ARM_SPI_BASE, vms);
839 if (vms->acpi_dev) {
840 build_ged_aml(scope, "\\_SB."GED_DEVICE,
841 HOTPLUG_HANDLER(vms->acpi_dev),
842 irqmap[VIRT_ACPI_GED] + ARM_SPI_BASE, AML_SYSTEM_MEMORY,
843 memmap[VIRT_ACPI_GED].base);
844 } else {
845 acpi_dsdt_add_gpio(scope, &memmap[VIRT_GPIO],
846 (irqmap[VIRT_GPIO] + ARM_SPI_BASE));
847 }
848
849 if (vms->acpi_dev) {
850 uint32_t event = object_property_get_uint(OBJECT(vms->acpi_dev),
851 "ged-event", &error_abort);
852
853 if (event & ACPI_GED_MEM_HOTPLUG_EVT) {
854 build_memory_hotplug_aml(scope, ms->ram_slots, "\\_SB", NULL,
855 AML_SYSTEM_MEMORY,
856 memmap[VIRT_PCDIMM_ACPI].base);
857 }
858 }
859
860 acpi_dsdt_add_power_button(scope);
861 #ifdef CONFIG_TPM
862 acpi_dsdt_add_tpm(scope, vms);
863 #endif
864
865 aml_append(dsdt, scope);
866
867 /* copy AML table into ACPI tables blob */
868 g_array_append_vals(table_data, dsdt->buf->data, dsdt->buf->len);
869
870 acpi_table_end(linker, &table);
871 free_aml_allocator();
872 }
873
874 typedef
875 struct AcpiBuildState {
876 /* Copy of table in RAM (for patching). */
877 MemoryRegion *table_mr;
878 MemoryRegion *rsdp_mr;
879 MemoryRegion *linker_mr;
880 /* Is table patched? */
881 bool patched;
882 } AcpiBuildState;
883
884 static void acpi_align_size(GArray *blob, unsigned align)
885 {
886 /*
887 * Align size to multiple of given size. This reduces the chance
888 * we need to change size in the future (breaking cross version migration).
889 */
890 g_array_set_size(blob, ROUND_UP(acpi_data_len(blob), align));
891 }
892
893 static
894 void virt_acpi_build(VirtMachineState *vms, AcpiBuildTables *tables)
895 {
896 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms);
897 GArray *table_offsets;
898 unsigned dsdt, xsdt;
899 GArray *tables_blob = tables->table_data;
900 MachineState *ms = MACHINE(vms);
901
902 table_offsets = g_array_new(false, true /* clear */,
903 sizeof(uint32_t));
904
905 bios_linker_loader_alloc(tables->linker,
906 ACPI_BUILD_TABLE_FILE, tables_blob,
907 64, false /* high memory */);
908
909 /* DSDT is pointed to by FADT */
910 dsdt = tables_blob->len;
911 build_dsdt(tables_blob, tables->linker, vms);
912
913 /* FADT MADT PPTT GTDT MCFG SPCR DBG2 pointed to by RSDT */
914 acpi_add_table(table_offsets, tables_blob);
915 build_fadt_rev6(tables_blob, tables->linker, vms, dsdt);
916
917 acpi_add_table(table_offsets, tables_blob);
918 build_madt(tables_blob, tables->linker, vms);
919
920 if (!vmc->no_cpu_topology) {
921 acpi_add_table(table_offsets, tables_blob);
922 build_pptt(tables_blob, tables->linker, ms,
923 vms->oem_id, vms->oem_table_id);
924 }
925
926 acpi_add_table(table_offsets, tables_blob);
927 build_gtdt(tables_blob, tables->linker, vms);
928
929 acpi_add_table(table_offsets, tables_blob);
930 {
931 AcpiMcfgInfo mcfg = {
932 .base = vms->memmap[VIRT_ECAM_ID(vms->highmem_ecam)].base,
933 .size = vms->memmap[VIRT_ECAM_ID(vms->highmem_ecam)].size,
934 };
935 build_mcfg(tables_blob, tables->linker, &mcfg, vms->oem_id,
936 vms->oem_table_id);
937 }
938
939 acpi_add_table(table_offsets, tables_blob);
940 spcr_setup(tables_blob, tables->linker, vms);
941
942 acpi_add_table(table_offsets, tables_blob);
943 build_dbg2(tables_blob, tables->linker, vms);
944
945 if (vms->ras) {
946 build_ghes_error_table(tables->hardware_errors, tables->linker);
947 acpi_add_table(table_offsets, tables_blob);
948 acpi_build_hest(tables_blob, tables->linker, vms->oem_id,
949 vms->oem_table_id);
950 }
951
952 if (ms->numa_state->num_nodes > 0) {
953 acpi_add_table(table_offsets, tables_blob);
954 build_srat(tables_blob, tables->linker, vms);
955 if (ms->numa_state->have_numa_distance) {
956 acpi_add_table(table_offsets, tables_blob);
957 build_slit(tables_blob, tables->linker, ms, vms->oem_id,
958 vms->oem_table_id);
959 }
960
961 if (ms->numa_state->hmat_enabled) {
962 acpi_add_table(table_offsets, tables_blob);
963 build_hmat(tables_blob, tables->linker, ms->numa_state,
964 vms->oem_id, vms->oem_table_id);
965 }
966 }
967
968 if (ms->nvdimms_state->is_enabled) {
969 nvdimm_build_acpi(table_offsets, tables_blob, tables->linker,
970 ms->nvdimms_state, ms->ram_slots, vms->oem_id,
971 vms->oem_table_id);
972 }
973
974 if (its_class_name() && !vmc->no_its) {
975 acpi_add_table(table_offsets, tables_blob);
976 build_iort(tables_blob, tables->linker, vms);
977 }
978
979 #ifdef CONFIG_TPM
980 if (tpm_get_version(tpm_find()) == TPM_VERSION_2_0) {
981 acpi_add_table(table_offsets, tables_blob);
982 build_tpm2(tables_blob, tables->linker, tables->tcpalog, vms->oem_id,
983 vms->oem_table_id);
984 }
985 #endif
986
987 if (vms->iommu == VIRT_IOMMU_VIRTIO) {
988 acpi_add_table(table_offsets, tables_blob);
989 build_viot(ms, tables_blob, tables->linker, vms->virtio_iommu_bdf,
990 vms->oem_id, vms->oem_table_id);
991 }
992
993 /* XSDT is pointed to by RSDP */
994 xsdt = tables_blob->len;
995 build_xsdt(tables_blob, tables->linker, table_offsets, vms->oem_id,
996 vms->oem_table_id);
997
998 /* RSDP is in FSEG memory, so allocate it separately */
999 {
1000 AcpiRsdpData rsdp_data = {
1001 .revision = 2,
1002 .oem_id = vms->oem_id,
1003 .xsdt_tbl_offset = &xsdt,
1004 .rsdt_tbl_offset = NULL,
1005 };
1006 build_rsdp(tables->rsdp, tables->linker, &rsdp_data);
1007 }
1008
1009 /*
1010 * The align size is 128, warn if 64k is not enough therefore
1011 * the align size could be resized.
1012 */
1013 if (tables_blob->len > ACPI_BUILD_TABLE_SIZE / 2) {
1014 warn_report("ACPI table size %u exceeds %d bytes,"
1015 " migration may not work",
1016 tables_blob->len, ACPI_BUILD_TABLE_SIZE / 2);
1017 error_printf("Try removing CPUs, NUMA nodes, memory slots"
1018 " or PCI bridges.\n");
1019 }
1020 acpi_align_size(tables_blob, ACPI_BUILD_TABLE_SIZE);
1021
1022
1023 /* Cleanup memory that's no longer used. */
1024 g_array_free(table_offsets, true);
1025 }
1026
1027 static void acpi_ram_update(MemoryRegion *mr, GArray *data)
1028 {
1029 uint32_t size = acpi_data_len(data);
1030
1031 /* Make sure RAM size is correct - in case it got changed
1032 * e.g. by migration */
1033 memory_region_ram_resize(mr, size, &error_abort);
1034
1035 memcpy(memory_region_get_ram_ptr(mr), data->data, size);
1036 memory_region_set_dirty(mr, 0, size);
1037 }
1038
1039 static void virt_acpi_build_update(void *build_opaque)
1040 {
1041 AcpiBuildState *build_state = build_opaque;
1042 AcpiBuildTables tables;
1043
1044 /* No state to update or already patched? Nothing to do. */
1045 if (!build_state || build_state->patched) {
1046 return;
1047 }
1048 build_state->patched = true;
1049
1050 acpi_build_tables_init(&tables);
1051
1052 virt_acpi_build(VIRT_MACHINE(qdev_get_machine()), &tables);
1053
1054 acpi_ram_update(build_state->table_mr, tables.table_data);
1055 acpi_ram_update(build_state->rsdp_mr, tables.rsdp);
1056 acpi_ram_update(build_state->linker_mr, tables.linker->cmd_blob);
1057
1058 acpi_build_tables_cleanup(&tables, true);
1059 }
1060
1061 static void virt_acpi_build_reset(void *build_opaque)
1062 {
1063 AcpiBuildState *build_state = build_opaque;
1064 build_state->patched = false;
1065 }
1066
1067 static const VMStateDescription vmstate_virt_acpi_build = {
1068 .name = "virt_acpi_build",
1069 .version_id = 1,
1070 .minimum_version_id = 1,
1071 .fields = (const VMStateField[]) {
1072 VMSTATE_BOOL(patched, AcpiBuildState),
1073 VMSTATE_END_OF_LIST()
1074 },
1075 };
1076
1077 void virt_acpi_setup(VirtMachineState *vms)
1078 {
1079 AcpiBuildTables tables;
1080 AcpiBuildState *build_state;
1081 AcpiGedState *acpi_ged_state;
1082
1083 if (!vms->fw_cfg) {
1084 trace_virt_acpi_setup();
1085 return;
1086 }
1087
1088 if (!virt_is_acpi_enabled(vms)) {
1089 trace_virt_acpi_setup();
1090 return;
1091 }
1092
1093 build_state = g_malloc0(sizeof *build_state);
1094
1095 acpi_build_tables_init(&tables);
1096 virt_acpi_build(vms, &tables);
1097
1098 /* Now expose it all to Guest */
1099 build_state->table_mr = acpi_add_rom_blob(virt_acpi_build_update,
1100 build_state, tables.table_data,
1101 ACPI_BUILD_TABLE_FILE);
1102 assert(build_state->table_mr != NULL);
1103
1104 build_state->linker_mr = acpi_add_rom_blob(virt_acpi_build_update,
1105 build_state,
1106 tables.linker->cmd_blob,
1107 ACPI_BUILD_LOADER_FILE);
1108
1109 fw_cfg_add_file(vms->fw_cfg, ACPI_BUILD_TPMLOG_FILE, tables.tcpalog->data,
1110 acpi_data_len(tables.tcpalog));
1111
1112 if (vms->ras) {
1113 assert(vms->acpi_dev);
1114 acpi_ged_state = ACPI_GED(vms->acpi_dev);
1115 acpi_ghes_add_fw_cfg(&acpi_ged_state->ghes_state,
1116 vms->fw_cfg, tables.hardware_errors);
1117 }
1118
1119 build_state->rsdp_mr = acpi_add_rom_blob(virt_acpi_build_update,
1120 build_state, tables.rsdp,
1121 ACPI_BUILD_RSDP_FILE);
1122
1123 qemu_register_reset(virt_acpi_build_reset, build_state);
1124 virt_acpi_build_reset(build_state);
1125 vmstate_register(NULL, 0, &vmstate_virt_acpi_build, build_state);
1126
1127 /* Cleanup tables but don't free the memory: we track it
1128 * in build_state.
1129 */
1130 acpi_build_tables_cleanup(&tables, false);
1131 }
armbru's QEMU hackery