hw/intc/pnv_xive2_regs.h

   1 /*
   2  * QEMU PowerPC XIVE2 interrupt controller model  (POWER10)
   3  *
   4  * Copyright (c) 2019-2022, IBM Corporation.
   5  *
   6  * This code is licensed under the GPL version 2 or later. See the
   7  * COPYING file in the top-level directory.
   8  */
   9
  10 #ifndef PPC_PNV_XIVE2_REGS_H
  11 #define PPC_PNV_XIVE2_REGS_H
  12
  13 /*
  14  * CQ Common Queue (PowerBus bridge) Registers
  15  */
  16
  17 /* XIVE2 Capabilities */
  18 #define X_CQ_XIVE_CAP                           0x02
  19 #define CQ_XIVE_CAP                             0x010
  20 #define    CQ_XIVE_CAP_VERSION                  PPC_BITMASK(0, 3)
  21 /* 4:6 reserved */
  22 #define    CQ_XIVE_CAP_USER_INT_PRIO            PPC_BITMASK(8, 9)
  23 #define       CQ_XIVE_CAP_USER_INT_PRIO_1       0
  24 #define       CQ_XIVE_CAP_USER_INT_PRIO_1_2     1
  25 #define       CQ_XIVE_CAP_USER_INT_PRIO_1_4     2
  26 #define       CQ_XIVE_CAP_USER_INT_PRIO_1_8     3
  27 #define    CQ_XIVE_CAP_VP_INT_PRIO              PPC_BITMASK(10, 11)
  28 #define       CQ_XIVE_CAP_VP_INT_PRIO_1_8       0
  29 #define       CQ_XIVE_CAP_VP_INT_PRIO_2_8       1
  30 #define       CQ_XIVE_CAP_VP_INT_PRIO_4_8       2
  31 #define       CQ_XIVE_CAP_VP_INT_PRIO_8         3
  32 #define    CQ_XIVE_CAP_BLOCK_ID_WIDTH           PPC_BITMASK(12, 13)
  33 #define    CQ_XIVE_CAP_VP_SAVE_RESTORE          PPC_BIT(38)
  34
  35 #define    CQ_XIVE_CAP_PHB_PQ_DISABLE           PPC_BIT(56)
  36 #define    CQ_XIVE_CAP_PHB_ABT                  PPC_BIT(57)
  37 #define    CQ_XIVE_CAP_EXPLOITATION_MODE        PPC_BIT(58)
  38 #define    CQ_XIVE_CAP_STORE_EOI                PPC_BIT(59)
  39
  40 /* XIVE2 Configuration */
  41 #define X_CQ_XIVE_CFG                           0x03
  42 #define CQ_XIVE_CFG                             0x018
  43
  44 /* 0:7 reserved */
  45 #define    CQ_XIVE_CFG_USER_INT_PRIO            PPC_BITMASK(8, 9)
  46 #define    CQ_XIVE_CFG_VP_INT_PRIO              PPC_BITMASK(10, 11)
  47 #define       CQ_XIVE_CFG_INT_PRIO_1            0
  48 #define       CQ_XIVE_CFG_INT_PRIO_2            1
  49 #define       CQ_XIVE_CFG_INT_PRIO_4            2
  50 #define       CQ_XIVE_CFG_INT_PRIO_8            3
  51 #define    CQ_XIVE_CFG_BLOCK_ID_WIDTH           PPC_BITMASK(12, 13)
  52 #define       CQ_XIVE_CFG_BLOCK_ID_4BITS        0
  53 #define       CQ_XIVE_CFG_BLOCK_ID_5BITS        1
  54 #define       CQ_XIVE_CFG_BLOCK_ID_6BITS        2
  55 #define       CQ_XIVE_CFG_BLOCK_ID_7BITS        3
  56 #define    CQ_XIVE_CFG_HYP_HARD_RANGE           PPC_BITMASK(14, 15)
  57 #define       CQ_XIVE_CFG_THREADID_7BITS        0
  58 #define       CQ_XIVE_CFG_THREADID_8BITS        1
  59 #define       CQ_XIVE_CFG_THREADID_9BITS        2
  60 #define       CQ_XIVE_CFG_THREADID_10BITs       3
  61 #define    CQ_XIVE_CFG_HYP_HARD_BLKID_OVERRIDE  PPC_BIT(16)
  62 #define    CQ_XIVE_CFG_HYP_HARD_BLOCK_ID        PPC_BITMASK(17, 23)
  63
  64 #define    CQ_XIVE_CFG_GEN1_TIMA_OS             PPC_BIT(24)
  65 #define    CQ_XIVE_CFG_GEN1_TIMA_HYP            PPC_BIT(25)
  66 #define    CQ_XIVE_CFG_GEN1_TIMA_HYP_BLK0       PPC_BIT(26) /* 0 if bit[25]=0 */
  67 #define    CQ_XIVE_CFG_GEN1_TIMA_CROWD_DIS      PPC_BIT(27) /* 0 if bit[25]=0 */
  68 #define    CQ_XIVE_CFG_GEN1_END_ESX             PPC_BIT(28)
  69 #define    CQ_XIVE_CFG_EN_VP_SAVE_RESTORE       PPC_BIT(38) /* 0 if bit[25]=1 */
  70 #define    CQ_XIVE_CFG_EN_VP_SAVE_REST_STRICT   PPC_BIT(39) /* 0 if bit[25]=1 */
  71
  72 /* Interrupt Controller Base Address Register - 512 pages (32M) */
  73 #define X_CQ_IC_BAR                             0x08
  74 #define CQ_IC_BAR                               0x040
  75 #define    CQ_IC_BAR_VALID                      PPC_BIT(0)
  76 #define    CQ_IC_BAR_64K                        PPC_BIT(1)
  77 /* 2:7 reserved */
  78 #define    CQ_IC_BAR_ADDR                       PPC_BITMASK(8, 42)
  79 /* 43:63 reserved */
  80
  81 /* Thread Management Base Address Register - 4 pages */
  82 #define X_CQ_TM_BAR                             0x09
  83 #define CQ_TM_BAR                               0x048
  84 #define    CQ_TM_BAR_VALID                      PPC_BIT(0)
  85 #define    CQ_TM_BAR_64K                        PPC_BIT(1)
  86 #define    CQ_TM_BAR_ADDR                       PPC_BITMASK(8, 49)
  87
  88 /* ESB Base Address Register */
  89 #define X_CQ_ESB_BAR                            0x0A
  90 #define CQ_ESB_BAR                              0x050
  91 #define    CQ_BAR_VALID                         PPC_BIT(0)
  92 #define    CQ_BAR_64K                           PPC_BIT(1)
  93 /* 2:7 reserved */
  94 #define    CQ_BAR_ADDR                          PPC_BITMASK(8, 39)
  95 #define    CQ_BAR_SET_DIV                       PPC_BITMASK(56, 58)
  96 #define    CQ_BAR_RANGE                         PPC_BITMASK(59, 63)
  97                                                 /* 0 (16M) - 16 (16T) */
  98
  99 /* END Base Address Register */
 100 #define X_CQ_END_BAR                            0x0B
 101 #define CQ_END_BAR                              0x058
 102
 103 /* NVPG Base Address Register */
 104 #define X_CQ_NVPG_BAR                           0x0C
 105 #define CQ_NVPG_BAR                             0x060
 106
 107 /* NVC Base Address Register */
 108 #define X_CQ_NVC_BAR                            0x0D
 109 #define CQ_NVC_BAR                              0x068
 110
 111 /* Table Address Register */
 112 #define X_CQ_TAR                                0x0E
 113 #define CQ_TAR                                  0x070
 114 #define     CQ_TAR_AUTOINC                      PPC_BIT(0)
 115 #define     CQ_TAR_SELECT                       PPC_BITMASK(12, 15)
 116 #define     CQ_TAR_ESB                          0       /* 0 - 15 */
 117 #define     CQ_TAR_END                          2       /* 0 - 15 */
 118 #define     CQ_TAR_NVPG                         3       /* 0 - 15 */
 119 #define     CQ_TAR_NVC                          5       /* 0 - 15 */
 120 #define     CQ_TAR_ENTRY_SELECT                 PPC_BITMASK(28, 31)
 121
 122 /* Table Data Register */
 123 #define X_CQ_TDR                                0x0F
 124 #define CQ_TDR                                  0x078
 125 /* for the NVPG, NVC, ESB, END Set Translation Tables */
 126 #define     CQ_TDR_VALID                        PPC_BIT(0)
 127 #define     CQ_TDR_BLOCK_ID                     PPC_BITMASK(60, 63)
 128
 129 /*
 130  * Processor Cores Enabled for MsgSnd
 131  * Identifies which of the 32 possible core chiplets are enabled and
 132  * available to receive the MsgSnd command
 133  */
 134 #define X_CQ_MSGSND                             0x10
 135 #define CQ_MSGSND                               0x080
 136
 137 /* Interrupt Unit Reset Control */
 138 #define X_CQ_RST_CTL                            0x12
 139 #define CQ_RST_CTL                              0x090
 140 #define     CQ_RST_SYNC_RESET                   PPC_BIT(0)      /* Write Only */
 141 #define     CQ_RST_QUIESCE_PB                   PPC_BIT(1)      /* RW */
 142 #define     CQ_RST_MASTER_IDLE                  PPC_BIT(2)      /* Read Only */
 143 #define     CQ_RST_SAVE_IDLE                    PPC_BIT(3)      /* Read Only */
 144 #define     CQ_RST_PB_BAR_RESET                 PPC_BIT(4)      /* Write Only */
 145
 146 /* PowerBus General Configuration */
 147 #define X_CQ_CFG_PB_GEN                         0x14
 148 #define CQ_CFG_PB_GEN                           0x0A0
 149 #define    CQ_CFG_PB_GEN_PB_INIT                PPC_BIT(45)
 150
 151 /*
 152  * FIR
 153  *     (And-Mask)
 154  *     (Or-Mask)
 155  */
 156 #define X_CQ_FIR                                0x30
 157 #define X_CQ_FIR_AND                            0x31
 158 #define X_CQ_FIR_OR                             0x32
 159 #define CQ_FIR                                  0x180
 160 #define CQ_FIR_AND                              0x188
 161 #define CQ_FIR_OR                               0x190
 162 #define  CQ_FIR_PB_RCMDX_CI_ERR1                PPC_BIT(19)
 163 #define  CQ_FIR_VC_INFO_ERROR_0_2               PPC_BITMASK(61, 63)
 164
 165 /*
 166  * FIR Mask
 167  *     (And-Mask)
 168  *     (Or-Mask)
 169  */
 170 #define X_CQ_FIRMASK                            0x33
 171 #define X_CQ_FIRMASK_AND                        0x34
 172 #define X_CQ_FIRMASK_OR                         0x35
 173 #define CQ_FIRMASK                              0x198
 174 #define CQ_FIRMASK_AND                          0x1A0
 175 #define CQ_FIRMASK_OR                           0x1A8
 176
 177 /*
 178  * VC0
 179  */
 180
 181 /* VSD table address */
 182 #define X_VC_VSD_TABLE_ADDR                     0x100
 183 #define VC_VSD_TABLE_ADDR                       0x000
 184 #define   VC_VSD_TABLE_AUTOINC                  PPC_BIT(0)
 185 #define   VC_VSD_TABLE_SELECT                   PPC_BITMASK(12, 15)
 186 #define   VC_VSD_TABLE_ADDRESS                  PPC_BITMASK(28, 31)
 187
 188 /* VSD table data */
 189 #define X_VC_VSD_TABLE_DATA                     0x101
 190 #define VC_VSD_TABLE_DATA                       0x008
 191
 192 /* AIB AT macro indirect kill */
 193 #define X_VC_AT_MACRO_KILL                      0x102
 194 #define VC_AT_MACRO_KILL                        0x010
 195 #define  VC_AT_MACRO_KILL_VALID                 PPC_BIT(0)
 196 #define  VC_AT_MACRO_KILL_VSD                   PPC_BITMASK(12, 15)
 197 #define  VC_AT_MACRO_KILL_BLOCK_ID              PPC_BITMASK(28, 31)
 198 #define  VC_AT_MACRO_KILL_OFFSET                PPC_BITMASK(48, 60)
 199
 200 /* AIB AT macro indirect kill mask (same bit definitions) */
 201 #define X_VC_AT_MACRO_KILL_MASK                 0x103
 202 #define VC_AT_MACRO_KILL_MASK                   0x018
 203
 204 /* Remote IRQs and ERQs configuration [n] (n = 0:6) */
 205 #define X_VC_QUEUES_CFG_REM0                    0x117
 206
 207 #define VC_QUEUES_CFG_REM0                      0x0B8
 208 #define VC_QUEUES_CFG_REM1                      0x0C0
 209 #define VC_QUEUES_CFG_REM2                      0x0C8
 210 #define VC_QUEUES_CFG_REM3                      0x0D0
 211 #define VC_QUEUES_CFG_REM4                      0x0D8
 212 #define VC_QUEUES_CFG_REM5                      0x0E0
 213 #define VC_QUEUES_CFG_REM6                      0x0E8
 214 #define  VC_QUEUES_CFG_MEMB_EN                  PPC_BIT(38)
 215 #define  VC_QUEUES_CFG_MEMB_SZ                  PPC_BITMASK(42, 47)
 216
 217 /*
 218  * VC1
 219  */
 220
 221 /* ESBC cache flush control trigger */
 222 #define X_VC_ESBC_FLUSH_CTRL                    0x140
 223 #define VC_ESBC_FLUSH_CTRL                      0x200
 224 #define  VC_ESBC_FLUSH_CTRL_POLL_VALID          PPC_BIT(0)
 225 #define  VC_ESBC_FLUSH_CTRL_WANT_CACHE_DISABLE  PPC_BIT(2)
 226
 227 /* ESBC cache flush poll trigger */
 228 #define X_VC_ESBC_FLUSH_POLL                    0x141
 229 #define VC_ESBC_FLUSH_POLL                      0x208
 230 #define  VC_ESBC_FLUSH_POLL_BLOCK_ID            PPC_BITMASK(0, 3)
 231 #define  VC_ESBC_FLUSH_POLL_OFFSET              PPC_BITMASK(4, 31)  /* 28-bit */
 232 #define  VC_ESBC_FLUSH_POLL_BLOCK_ID_MASK       PPC_BITMASK(32, 35)
 233 #define  VC_ESBC_FLUSH_POLL_OFFSET_MASK         PPC_BITMASK(36, 63) /* 28-bit */
 234
 235 /* ESBC cache flush inject register */
 236 #define X_VC_ESBC_FLUSH_INJECT                  0x142
 237 #define VC_ESBC_FLUSH_INJECT                    0x210
 238
 239 /* ESBC configuration */
 240 #define X_VC_ESBC_CFG                           0x148
 241 #define VC_ESBC_CFG                             0x240
 242
 243 /* EASC flush control register */
 244 #define X_VC_EASC_FLUSH_CTRL                    0x160
 245 #define VC_EASC_FLUSH_CTRL                      0x300
 246 #define  VC_EASC_FLUSH_CTRL_POLL_VALID          PPC_BIT(0)
 247 #define  VC_EASC_FLUSH_CTRL_WANT_CACHE_DISABLE  PPC_BIT(2)
 248
 249 /* EASC flush poll register */
 250 #define X_VC_EASC_FLUSH_POLL                    0x161
 251 #define VC_EASC_FLUSH_POLL                      0x308
 252 #define  VC_EASC_FLUSH_POLL_BLOCK_ID            PPC_BITMASK(0, 3)
 253 #define  VC_EASC_FLUSH_POLL_OFFSET              PPC_BITMASK(4, 31)  /* 28-bit */
 254 #define  VC_EASC_FLUSH_POLL_BLOCK_ID_MASK       PPC_BITMASK(32, 35)
 255 #define  VC_EASC_FLUSH_POLL_OFFSET_MASK         PPC_BITMASK(36, 63) /* 28-bit */
 256
 257 /* EASC flush inject register */
 258 #define X_VC_EASC_FLUSH_INJECT                  0x162
 259 #define VC_EASC_FLUSH_INJECT                    0x310
 260
 261 /*
 262  * VC2
 263  */
 264
 265 /* ENDC flush control register */
 266 #define X_VC_ENDC_FLUSH_CTRL                    0x180
 267 #define VC_ENDC_FLUSH_CTRL                      0x400
 268 #define  VC_ENDC_FLUSH_CTRL_POLL_VALID          PPC_BIT(0)
 269 #define  VC_ENDC_FLUSH_CTRL_WANT_CACHE_DISABLE  PPC_BIT(2)
 270 #define  VC_ENDC_FLUSH_CTRL_WANT_INVALIDATE     PPC_BIT(3)
 271 #define  VC_ENDC_FLUSH_CTRL_INJECT_INVALIDATE   PPC_BIT(7)
 272
 273 /* ENDC flush poll register */
 274 #define X_VC_ENDC_FLUSH_POLL                    0x181
 275 #define VC_ENDC_FLUSH_POLL                      0x408
 276 #define  VC_ENDC_FLUSH_POLL_BLOCK_ID            PPC_BITMASK(4, 7)
 277 #define  VC_ENDC_FLUSH_POLL_OFFSET              PPC_BITMASK(8, 31)  /* 24-bit */
 278 #define  VC_ENDC_FLUSH_POLL_BLOCK_ID_MASK       PPC_BITMASK(36, 39)
 279 #define  VC_ENDC_FLUSH_POLL_OFFSET_MASK         PPC_BITMASK(40, 63) /* 24-bit */
 280
 281 /* ENDC flush inject register */
 282 #define X_VC_ENDC_FLUSH_INJECT                  0x182
 283 #define VC_ENDC_FLUSH_INJECT                    0x410
 284
 285 /* ENDC Sync done */
 286 #define X_VC_ENDC_SYNC_DONE                     0x184
 287 #define VC_ENDC_SYNC_DONE                       0x420
 288 #define   VC_ENDC_SYNC_POLL_DONE                PPC_BITMASK(0, 6)
 289 #define   VC_ENDC_SYNC_QUEUE_IPI                PPC_BIT(0)
 290 #define   VC_ENDC_SYNC_QUEUE_HWD                PPC_BIT(1)
 291 #define   VC_ENDC_SYNC_QUEUE_NXC                PPC_BIT(2)
 292 #define   VC_ENDC_SYNC_QUEUE_INT                PPC_BIT(3)
 293 #define   VC_ENDC_SYNC_QUEUE_OS                 PPC_BIT(4)
 294 #define   VC_ENDC_SYNC_QUEUE_POOL               PPC_BIT(5)
 295 #define   VC_ENDC_SYNC_QUEUE_HARD               PPC_BIT(6)
 296 #define   VC_QUEUE_COUNT                        7
 297
 298 /* ENDC cache watch assign */
 299 #define X_VC_ENDC_WATCH_ASSIGN                  0x186
 300 #define VC_ENDC_WATCH_ASSIGN                    0x430
 301
 302 /* ENDC configuration register */
 303 #define X_VC_ENDC_CFG                           0x188
 304 #define VC_ENDC_CFG                             0x440
 305 #define   VC_ENDC_CFG_CACHE_WATCH_ASSIGN        PPC_BITMASK(32, 35)
 306
 307 /* ENDC cache watch specification 0  */
 308 #define X_VC_ENDC_WATCH0_SPEC                   0x1A0
 309 #define VC_ENDC_WATCH0_SPEC                     0x500
 310 #define   VC_ENDC_WATCH_CONFLICT                PPC_BIT(0)
 311 #define   VC_ENDC_WATCH_FULL                    PPC_BIT(8)
 312 #define   VC_ENDC_WATCH_BLOCK_ID                PPC_BITMASK(28, 31)
 313 #define   VC_ENDC_WATCH_INDEX                   PPC_BITMASK(40, 63)
 314
 315 /* ENDC cache watch data 0 */
 316 #define X_VC_ENDC_WATCH0_DATA0                  0x1A4
 317 #define X_VC_ENDC_WATCH0_DATA1                  0x1A5
 318 #define X_VC_ENDC_WATCH0_DATA2                  0x1A6
 319 #define X_VC_ENDC_WATCH0_DATA3                  0x1A7
 320
 321 #define VC_ENDC_WATCH0_DATA0                    0x520
 322 #define VC_ENDC_WATCH0_DATA1                    0x528
 323 #define VC_ENDC_WATCH0_DATA2                    0x530
 324 #define VC_ENDC_WATCH0_DATA3                    0x538
 325
 326 /* ENDC cache watch 1  */
 327 #define X_VC_ENDC_WATCH1_SPEC                   0x1A8
 328 #define VC_ENDC_WATCH1_SPEC                     0x540
 329 #define X_VC_ENDC_WATCH1_DATA0                  0x1AC
 330 #define X_VC_ENDC_WATCH1_DATA1                  0x1AD
 331 #define X_VC_ENDC_WATCH1_DATA2                  0x1AE
 332 #define X_VC_ENDC_WATCH1_DATA3                  0x1AF
 333 #define VC_ENDC_WATCH1_DATA0                    0x560
 334 #define VC_ENDC_WATCH1_DATA1                    0x568
 335 #define VC_ENDC_WATCH1_DATA2                    0x570
 336 #define VC_ENDC_WATCH1_DATA3                    0x578
 337
 338 /* ENDC cache watch 2  */
 339 #define X_VC_ENDC_WATCH2_SPEC                   0x1B0
 340 #define VC_ENDC_WATCH2_SPEC                     0x580
 341 #define X_VC_ENDC_WATCH2_DATA0                  0x1B4
 342 #define X_VC_ENDC_WATCH2_DATA1                  0x1B5
 343 #define X_VC_ENDC_WATCH2_DATA2                  0x1B6
 344 #define X_VC_ENDC_WATCH2_DATA3                  0x1B7
 345 #define VC_ENDC_WATCH2_DATA0                    0x5A0
 346 #define VC_ENDC_WATCH2_DATA1                    0x5A8
 347 #define VC_ENDC_WATCH2_DATA2                    0x5B0
 348 #define VC_ENDC_WATCH2_DATA3                    0x5B8
 349
 350 /* ENDC cache watch 3  */
 351 #define X_VC_ENDC_WATCH3_SPEC                   0x1B8
 352 #define VC_ENDC_WATCH3_SPEC                     0x5C0
 353 #define X_VC_ENDC_WATCH3_DATA0                  0x1BC
 354 #define X_VC_ENDC_WATCH3_DATA1                  0x1BD
 355 #define X_VC_ENDC_WATCH3_DATA2                  0x1BE
 356 #define X_VC_ENDC_WATCH3_DATA3                  0x1BF
 357 #define VC_ENDC_WATCH3_DATA0                    0x5E0
 358 #define VC_ENDC_WATCH3_DATA1                    0x5E8
 359 #define VC_ENDC_WATCH3_DATA2                    0x5F0
 360 #define VC_ENDC_WATCH3_DATA3                    0x5F8
 361
 362 /*
 363  * PC LSB1
 364  */
 365
 366 /* VSD table address register */
 367 #define X_PC_VSD_TABLE_ADDR                     0x200
 368 #define PC_VSD_TABLE_ADDR                       0x000
 369 #define   PC_VSD_TABLE_AUTOINC                  PPC_BIT(0)
 370 #define   PC_VSD_TABLE_SELECT                   PPC_BITMASK(12, 15)
 371 #define   PC_VSD_TABLE_ADDRESS                  PPC_BITMASK(28, 31)
 372
 373 /* VSD table data register */
 374 #define X_PC_VSD_TABLE_DATA                     0x201
 375 #define PC_VSD_TABLE_DATA                       0x008
 376
 377 /* AT indirect kill register */
 378 #define X_PC_AT_KILL                            0x202
 379 #define PC_AT_KILL                              0x010
 380 #define     PC_AT_KILL_VALID                    PPC_BIT(0)
 381 #define     PC_AT_KILL_VSD_TYPE                 PPC_BITMASK(24, 27)
 382 /* Only NVP, NVG, NVC */
 383 #define     PC_AT_KILL_BLOCK_ID                 PPC_BITMASK(28, 31)
 384 #define     PC_AT_KILL_OFFSET                   PPC_BITMASK(48, 60)
 385
 386 /* AT indirect kill mask register */
 387 #define X_PC_AT_KILL_MASK                       0x203
 388 #define PC_AT_KILL_MASK                         0x018
 389 #define     PC_AT_KILL_MASK_VSD_TYPE            PPC_BITMASK(24, 27)
 390 #define     PC_AT_KILL_MASK_BLOCK_ID            PPC_BITMASK(28, 31)
 391 #define     PC_AT_KILL_MASK_OFFSET              PPC_BITMASK(48, 60)
 392
 393 /*
 394  * PC LSB2
 395  */
 396
 397 /* NxC Cache flush control */
 398 #define X_PC_NXC_FLUSH_CTRL                     0x280
 399 #define PC_NXC_FLUSH_CTRL                       0x400
 400 #define  PC_NXC_FLUSH_CTRL_POLL_VALID           PPC_BIT(0)
 401 #define  PC_NXC_FLUSH_CTRL_WANT_CACHE_DISABLE   PPC_BIT(2)
 402 #define  PC_NXC_FLUSH_CTRL_WANT_INVALIDATE      PPC_BIT(3)
 403 #define  PC_NXC_FLUSH_CTRL_INJECT_INVALIDATE    PPC_BIT(7)
 404
 405 /* NxC Cache flush poll */
 406 #define X_PC_NXC_FLUSH_POLL                     0x281
 407 #define PC_NXC_FLUSH_POLL                       0x408
 408 #define  PC_NXC_FLUSH_POLL_NXC_TYPE             PPC_BITMASK(2, 3)
 409 #define    PC_NXC_FLUSH_POLL_NXC_TYPE_NVP       0
 410 #define    PC_NXC_FLUSH_POLL_NXC_TYPE_NVG       2
 411 #define    PC_NXC_FLUSH_POLL_NXC_TYPE_NVC       3
 412 #define  PC_NXC_FLUSH_POLL_BLOCK_ID             PPC_BITMASK(4, 7)
 413 #define  PC_NXC_FLUSH_POLL_OFFSET               PPC_BITMASK(8, 31)  /* 24-bit */
 414 #define  PC_NXC_FLUSH_POLL_NXC_TYPE_MASK        PPC_BITMASK(34, 35) /* 0: Ign */
 415 #define  PC_NXC_FLUSH_POLL_BLOCK_ID_MASK        PPC_BITMASK(36, 39)
 416 #define  PC_NXC_FLUSH_POLL_OFFSET_MASK          PPC_BITMASK(40, 63) /* 24-bit */
 417
 418 /* NxC Cache flush inject */
 419 #define X_PC_NXC_FLUSH_INJECT                   0x282
 420 #define PC_NXC_FLUSH_INJECT                     0x410
 421
 422 /* NxC Cache watch assign */
 423 #define X_PC_NXC_WATCH_ASSIGN                   0x286
 424 #define PC_NXC_WATCH_ASSIGN                     0x430
 425
 426 /* NxC Proc config */
 427 #define X_PC_NXC_PROC_CONFIG                    0x28A
 428 #define PC_NXC_PROC_CONFIG                      0x450
 429 #define   PC_NXC_PROC_CONFIG_WATCH_ASSIGN       PPC_BITMASK(0, 3)
 430 #define   PC_NXC_PROC_CONFIG_NVG_TABLE_COMPRESS PPC_BITMASK(32, 35)
 431 #define   PC_NXC_PROC_CONFIG_NVC_TABLE_COMPRESS PPC_BITMASK(36, 39)
 432
 433 /* NxC Cache Watch 0 Specification */
 434 #define X_PC_NXC_WATCH0_SPEC                    0x2A0
 435 #define PC_NXC_WATCH0_SPEC                      0x500
 436 #define   PC_NXC_WATCH_CONFLICT                 PPC_BIT(0)
 437 #define   PC_NXC_WATCH_FULL                     PPC_BIT(8)
 438 #define   PC_NXC_WATCH_NXC_TYPE                 PPC_BITMASK(26, 27)
 439 #define     PC_NXC_WATCH_NXC_NVP                0
 440 #define     PC_NXC_WATCH_NXC_NVG                2
 441 #define     PC_NXC_WATCH_NXC_NVC                3
 442 #define   PC_NXC_WATCH_BLOCK_ID                 PPC_BITMASK(28, 31)
 443 #define   PC_NXC_WATCH_INDEX                    PPC_BITMASK(40, 63)
 444
 445 /* NxC Cache Watch 0 Data */
 446 #define X_PC_NXC_WATCH0_DATA0                   0x2A4
 447 #define X_PC_NXC_WATCH0_DATA1                   0x2A5
 448 #define X_PC_NXC_WATCH0_DATA2                   0x2A6
 449 #define X_PC_NXC_WATCH0_DATA3                   0x2A7
 450
 451 #define PC_NXC_WATCH0_DATA0                     0x520
 452 #define PC_NXC_WATCH0_DATA1                     0x528
 453 #define PC_NXC_WATCH0_DATA2                     0x530
 454 #define PC_NXC_WATCH0_DATA3                     0x538
 455
 456 /* NxC Cache Watch 1 */
 457 #define X_PC_NXC_WATCH1_SPEC                    0x2A8
 458 #define PC_NXC_WATCH1_SPEC                      0x540
 459 #define X_PC_NXC_WATCH1_DATA0                   0x2AC
 460 #define X_PC_NXC_WATCH1_DATA1                   0x2AD
 461 #define X_PC_NXC_WATCH1_DATA2                   0x2AE
 462 #define X_PC_NXC_WATCH1_DATA3                   0x2AF
 463 #define PC_NXC_WATCH1_DATA0                     0x560
 464 #define PC_NXC_WATCH1_DATA1                     0x568
 465 #define PC_NXC_WATCH1_DATA2                     0x570
 466 #define PC_NXC_WATCH1_DATA3                     0x578
 467
 468 /* NxC Cache Watch 2 */
 469 #define X_PC_NXC_WATCH2_SPEC                    0x2B0
 470 #define PC_NXC_WATCH2_SPEC                      0x580
 471 #define X_PC_NXC_WATCH2_DATA0                   0x2B4
 472 #define X_PC_NXC_WATCH2_DATA1                   0x2B5
 473 #define X_PC_NXC_WATCH2_DATA2                   0x2B6
 474 #define X_PC_NXC_WATCH2_DATA3                   0x2B7
 475 #define PC_NXC_WATCH2_DATA0                     0x5A0
 476 #define PC_NXC_WATCH2_DATA1                     0x5A8
 477 #define PC_NXC_WATCH2_DATA2                     0x5B0
 478 #define PC_NXC_WATCH2_DATA3                     0x5B8
 479
 480 /* NxC Cache Watch 3 */
 481 #define X_PC_NXC_WATCH3_SPEC                    0x2B8
 482 #define PC_NXC_WATCH3_SPEC                      0x5C0
 483 #define X_PC_NXC_WATCH3_DATA0                   0x2BC
 484 #define X_PC_NXC_WATCH3_DATA1                   0x2BD
 485 #define X_PC_NXC_WATCH3_DATA2                   0x2BE
 486 #define X_PC_NXC_WATCH3_DATA3                   0x2BF
 487 #define PC_NXC_WATCH3_DATA0                     0x5E0
 488 #define PC_NXC_WATCH3_DATA1                     0x5E8
 489 #define PC_NXC_WATCH3_DATA2                     0x5F0
 490 #define PC_NXC_WATCH3_DATA3                     0x5F8
 491
 492 /*
 493  * TCTXT Registers
 494  */
 495
 496 /* Physical Thread Enable0 register */
 497 #define X_TCTXT_EN0                             0x300
 498 #define TCTXT_EN0                               0x000
 499
 500 /* Physical Thread Enable0 Set register */
 501 #define X_TCTXT_EN0_SET                         0x302
 502 #define TCTXT_EN0_SET                           0x010
 503
 504 /* Physical Thread Enable0 Reset register */
 505 #define X_TCTXT_EN0_RESET                       0x303
 506 #define TCTXT_EN0_RESET                         0x018
 507
 508 /* Physical Thread Enable1 register */
 509 #define X_TCTXT_EN1                             0x304
 510 #define TCTXT_EN1                               0x020
 511
 512 /* Physical Thread Enable1 Set register */
 513 #define X_TCTXT_EN1_SET                         0x306
 514 #define TCTXT_EN1_SET                           0x030
 515
 516 /* Physical Thread Enable1 Reset register */
 517 #define X_TCTXT_EN1_RESET                       0x307
 518 #define TCTXT_EN1_RESET                         0x038
 519
 520 /* TCTXT Config register */
 521 #define X_TCTXT_CFG                             0x328
 522 #define TCTXT_CFG                               0x140
 523
 524 /*
 525  * VSD Tables
 526  */
 527 #define VST_ESB                  0
 528 #define VST_EAS                  1 /* No used by PC */
 529 #define VST_END                  2
 530 #define VST_NVP                  3
 531 #define VST_NVG                  4
 532 #define VST_NVC                  5
 533 #define VST_IC                   6 /* No used by PC */
 534 #define VST_SYNC                 7
 535 #define VST_ERQ                  8 /* No used by PC */
 536
 537 /*
 538  * Bits in a VSD entry.
 539  *
 540  * Note: the address is naturally aligned, we don't use a PPC_BITMASK,
 541  *       but just a mask to apply to the address before OR'ing it in.
 542  *
 543  * Note: VSD_FIRMWARE is a SW bit ! It hijacks an unused bit in the
 544  *       VSD and is only meant to be used in indirect mode !
 545  */
 546 #define VSD_MODE                PPC_BITMASK(0, 1)
 547 #define  VSD_MODE_SHARED        1
 548 #define  VSD_MODE_EXCLUSIVE     2
 549 #define  VSD_MODE_FORWARD       3
 550 #define VSD_FIRMWARE            PPC_BIT(2) /* Read warning */
 551 #define VSD_FIRMWARE2           PPC_BIT(3) /* unused */
 552 #define VSD_RESERVED            PPC_BITMASK(4, 7) /* P10 reserved */
 553 #define VSD_ADDRESS_MASK        0x00fffffffffff000ull
 554 #define VSD_MIGRATION_REG       PPC_BITMASK(52, 55)
 555 #define VSD_INDIRECT            PPC_BIT(56)
 556 #define VSD_TSIZE               PPC_BITMASK(59, 63)
 557
 558 #endif /* PPC_PNV_XIVE2_REGS_H */