hw/pci-host/gpex-acpi.c

   1 #include "qemu/osdep.h"
   2 #include "hw/acpi/aml-build.h"
   3 #include "hw/pci-host/gpex.h"
   4 #include "hw/arm/virt.h"
   5 #include "hw/pci/pci_bus.h"
   6 #include "hw/pci/pci_bridge.h"
   7 #include "hw/pci/pcie_host.h"
   8 #include "hw/acpi/cxl.h"
   9
  10 static void acpi_dsdt_add_pci_route_table(Aml *dev, uint32_t irq,
  11                                           Aml *scope, uint8_t bus_num)
  12 {
  13     Aml *method, *crs;
  14     int i, slot_no;
  15
  16     /* Declare the PCI Routing Table. */
  17     Aml *rt_pkg = aml_varpackage(PCI_SLOT_MAX * PCI_NUM_PINS);
  18     for (slot_no = 0; slot_no < PCI_SLOT_MAX; slot_no++) {
  19         for (i = 0; i < PCI_NUM_PINS; i++) {
  20             int gsi = (i + slot_no) % PCI_NUM_PINS;
  21             Aml *pkg = aml_package(4);
  22             aml_append(pkg, aml_int((slot_no << 16) | 0xFFFF));
  23             aml_append(pkg, aml_int(i));
  24             aml_append(pkg, aml_name("L%.02X%X", bus_num, gsi));
  25             aml_append(pkg, aml_int(0));
  26             aml_append(rt_pkg, pkg);
  27         }
  28     }
  29     aml_append(dev, aml_name_decl("_PRT", rt_pkg));
  30
  31     /* Create GSI link device */
  32     for (i = 0; i < PCI_NUM_PINS; i++) {
  33         uint32_t irqs = irq + i;
  34         Aml *dev_gsi = aml_device("L%.02X%X", bus_num, i);
  35         aml_append(dev_gsi, aml_name_decl("_HID", aml_string("PNP0C0F")));
  36         aml_append(dev_gsi, aml_name_decl("_UID", aml_int(i)));
  37         crs = aml_resource_template();
  38         aml_append(crs,
  39                    aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
  40                                  AML_EXCLUSIVE, &irqs, 1));
  41         aml_append(dev_gsi, aml_name_decl("_PRS", crs));
  42         crs = aml_resource_template();
  43         aml_append(crs,
  44                    aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
  45                                  AML_EXCLUSIVE, &irqs, 1));
  46         aml_append(dev_gsi, aml_name_decl("_CRS", crs));
  47         method = aml_method("_SRS", 1, AML_NOTSERIALIZED);
  48         aml_append(dev_gsi, method);
  49         aml_append(scope, dev_gsi);
  50     }
  51 }
  52
  53 static void acpi_dsdt_add_pci_osc(Aml *dev)
  54 {
  55     Aml *method, *UUID, *ifctx, *ifctx1, *elsectx, *buf;
  56
  57     /* Declare an _OSC (OS Control Handoff) method */
  58     aml_append(dev, aml_name_decl("SUPP", aml_int(0)));
  59     aml_append(dev, aml_name_decl("CTRL", aml_int(0)));
  60     method = aml_method("_OSC", 4, AML_NOTSERIALIZED);
  61     aml_append(method,
  62         aml_create_dword_field(aml_arg(3), aml_int(0), "CDW1"));
  63
  64     /* PCI Firmware Specification 3.0
  65      * 4.5.1. _OSC Interface for PCI Host Bridge Devices
  66      * The _OSC interface for a PCI/PCI-X/PCI Express hierarchy is
  67      * identified by the Universal Unique IDentifier (UUID)
  68      * 33DB4D5B-1FF7-401C-9657-7441C03DD766
  69      */
  70     UUID = aml_touuid("33DB4D5B-1FF7-401C-9657-7441C03DD766");
  71     ifctx = aml_if(aml_equal(aml_arg(0), UUID));
  72     aml_append(ifctx,
  73         aml_create_dword_field(aml_arg(3), aml_int(4), "CDW2"));
  74     aml_append(ifctx,
  75         aml_create_dword_field(aml_arg(3), aml_int(8), "CDW3"));
  76     aml_append(ifctx, aml_store(aml_name("CDW2"), aml_name("SUPP")));
  77     aml_append(ifctx, aml_store(aml_name("CDW3"), aml_name("CTRL")));
  78
  79     /*
  80      * Allow OS control for all 5 features:
  81      * PCIeHotplug SHPCHotplug PME AER PCIeCapability.
  82      */
  83     aml_append(ifctx, aml_and(aml_name("CTRL"), aml_int(0x1F),
  84                               aml_name("CTRL")));
  85
  86     ifctx1 = aml_if(aml_lnot(aml_equal(aml_arg(1), aml_int(0x1))));
  87     aml_append(ifctx1, aml_or(aml_name("CDW1"), aml_int(0x08),
  88                               aml_name("CDW1")));
  89     aml_append(ifctx, ifctx1);
  90
  91     ifctx1 = aml_if(aml_lnot(aml_equal(aml_name("CDW3"), aml_name("CTRL"))));
  92     aml_append(ifctx1, aml_or(aml_name("CDW1"), aml_int(0x10),
  93                               aml_name("CDW1")));
  94     aml_append(ifctx, ifctx1);
  95
  96     aml_append(ifctx, aml_store(aml_name("CTRL"), aml_name("CDW3")));
  97     aml_append(ifctx, aml_return(aml_arg(3)));
  98     aml_append(method, ifctx);
  99
 100     elsectx = aml_else();
 101     aml_append(elsectx, aml_or(aml_name("CDW1"), aml_int(4),
 102                                aml_name("CDW1")));
 103     aml_append(elsectx, aml_return(aml_arg(3)));
 104     aml_append(method, elsectx);
 105     aml_append(dev, method);
 106
 107     method = aml_method("_DSM", 4, AML_NOTSERIALIZED);
 108
 109     /* PCI Firmware Specification 3.0
 110      * 4.6.1. _DSM for PCI Express Slot Information
 111      * The UUID in _DSM in this context is
 112      * {E5C937D0-3553-4D7A-9117-EA4D19C3434D}
 113      */
 114     UUID = aml_touuid("E5C937D0-3553-4D7A-9117-EA4D19C3434D");
 115     ifctx = aml_if(aml_equal(aml_arg(0), UUID));
 116     ifctx1 = aml_if(aml_equal(aml_arg(2), aml_int(0)));
 117     uint8_t byte_list[1] = {1};
 118     buf = aml_buffer(1, byte_list);
 119     aml_append(ifctx1, aml_return(buf));
 120     aml_append(ifctx, ifctx1);
 121     aml_append(method, ifctx);
 122
 123     byte_list[0] = 0;
 124     buf = aml_buffer(1, byte_list);
 125     aml_append(method, aml_return(buf));
 126     aml_append(dev, method);
 127 }
 128
 129 void acpi_dsdt_add_gpex(Aml *scope, struct GPEXConfig *cfg)
 130 {
 131     int nr_pcie_buses = cfg->ecam.size / PCIE_MMCFG_SIZE_MIN;
 132     Aml *method, *crs, *dev, *rbuf;
 133     PCIBus *bus = cfg->bus;
 134     CrsRangeSet crs_range_set;
 135     CrsRangeEntry *entry;
 136     int i;
 137
 138     /* start to construct the tables for pxb */
 139     crs_range_set_init(&crs_range_set);
 140     if (bus) {
 141         QLIST_FOREACH(bus, &bus->child, sibling) {
 142             uint8_t bus_num = pci_bus_num(bus);
 143             uint8_t numa_node = pci_bus_numa_node(bus);
 144             bool is_cxl = pci_bus_is_cxl(bus);
 145
 146             if (!pci_bus_is_root(bus)) {
 147                 continue;
 148             }
 149
 150             /*
 151              * 0 - (nr_pcie_buses - 1) is the bus range for the main
 152              * host-bridge and it equals the MIN of the
 153              * busNr defined for pxb-pcie.
 154              */
 155             if (bus_num < nr_pcie_buses) {
 156                 nr_pcie_buses = bus_num;
 157             }
 158
 159             dev = aml_device("PC%.02X", bus_num);
 160             if (is_cxl) {
 161                 struct Aml *pkg = aml_package(2);
 162                 aml_append(dev, aml_name_decl("_HID", aml_string("ACPI0016")));
 163                 aml_append(pkg, aml_eisaid("PNP0A08"));
 164                 aml_append(pkg, aml_eisaid("PNP0A03"));
 165                 aml_append(dev, aml_name_decl("_CID", pkg));
 166             } else {
 167                 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A08")));
 168                 aml_append(dev, aml_name_decl("_CID", aml_string("PNP0A03")));
 169             }
 170             aml_append(dev, aml_name_decl("_BBN", aml_int(bus_num)));
 171             aml_append(dev, aml_name_decl("_UID", aml_int(bus_num)));
 172             aml_append(dev, aml_name_decl("_STR", aml_unicode("pxb Device")));
 173             aml_append(dev, aml_name_decl("_CCA", aml_int(1)));
 174             if (numa_node != NUMA_NODE_UNASSIGNED) {
 175                 aml_append(dev, aml_name_decl("_PXM", aml_int(numa_node)));
 176             }
 177
 178             acpi_dsdt_add_pci_route_table(dev, cfg->irq, scope, bus_num);
 179
 180             /*
 181              * Resources defined for PXBs are composed of the following parts:
 182              * 1. The resources the pci-brige/pcie-root-port need.
 183              * 2. The resources the devices behind pxb need.
 184              */
 185             crs = build_crs(PCI_HOST_BRIDGE(BUS(bus)->parent), &crs_range_set,
 186                             cfg->pio.base, 0, 0, 0);
 187             aml_append(dev, aml_name_decl("_CRS", crs));
 188
 189             if (is_cxl) {
 190                 build_cxl_osc_method(dev);
 191             } else {
 192                 acpi_dsdt_add_pci_osc(dev);
 193             }
 194
 195             aml_append(scope, dev);
 196         }
 197     }
 198
 199     /* tables for the main */
 200     dev = aml_device("%s", "PCI0");
 201     aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A08")));
 202     aml_append(dev, aml_name_decl("_CID", aml_string("PNP0A03")));
 203     aml_append(dev, aml_name_decl("_SEG", aml_int(0)));
 204     aml_append(dev, aml_name_decl("_BBN", aml_int(0)));
 205     aml_append(dev, aml_name_decl("_UID", aml_int(0)));
 206     aml_append(dev, aml_name_decl("_STR", aml_unicode("PCIe 0 Device")));
 207     aml_append(dev, aml_name_decl("_CCA", aml_int(1)));
 208
 209     acpi_dsdt_add_pci_route_table(dev, cfg->irq, scope, 0);
 210
 211     method = aml_method("_CBA", 0, AML_NOTSERIALIZED);
 212     aml_append(method, aml_return(aml_int(cfg->ecam.base)));
 213     aml_append(dev, method);
 214
 215     /*
 216      * At this point crs_range_set has all the ranges used by pci
 217      * busses *other* than PCI0.  These ranges will be excluded from
 218      * the PCI0._CRS.
 219      */
 220     rbuf = aml_resource_template();
 221     aml_append(rbuf,
 222         aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE,
 223                             0x0000, 0x0000, nr_pcie_buses - 1, 0x0000,
 224                             nr_pcie_buses));
 225     if (cfg->mmio32.size) {
 226         crs_replace_with_free_ranges(crs_range_set.mem_ranges,
 227                                      cfg->mmio32.base,
 228                                      cfg->mmio32.base + cfg->mmio32.size - 1);
 229         for (i = 0; i < crs_range_set.mem_ranges->len; i++) {
 230             entry = g_ptr_array_index(crs_range_set.mem_ranges, i);
 231             aml_append(rbuf,
 232                 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
 233                                  AML_NON_CACHEABLE, AML_READ_WRITE, 0x0000,
 234                                  entry->base, entry->limit,
 235                                  0x0000, entry->limit - entry->base + 1));
 236         }
 237     }
 238     if (cfg->pio.size) {
 239         crs_replace_with_free_ranges(crs_range_set.io_ranges,
 240                                      0x0000,
 241                                      cfg->pio.size - 1);
 242         for (i = 0; i < crs_range_set.io_ranges->len; i++) {
 243             entry = g_ptr_array_index(crs_range_set.io_ranges, i);
 244             aml_append(rbuf,
 245                 aml_dword_io(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE,
 246                              AML_ENTIRE_RANGE, 0x0000, entry->base,
 247                              entry->limit, cfg->pio.base,
 248                              entry->limit - entry->base + 1));
 249         }
 250     }
 251     if (cfg->mmio64.size) {
 252         crs_replace_with_free_ranges(crs_range_set.mem_64bit_ranges,
 253                                      cfg->mmio64.base,
 254                                      cfg->mmio64.base + cfg->mmio64.size - 1);
 255         for (i = 0; i < crs_range_set.mem_64bit_ranges->len; i++) {
 256             entry = g_ptr_array_index(crs_range_set.mem_64bit_ranges, i);
 257             aml_append(rbuf,
 258                 aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
 259                                  AML_NON_CACHEABLE, AML_READ_WRITE, 0x0000,
 260                                  entry->base,
 261                                  entry->limit, 0x0000,
 262                                  entry->limit - entry->base + 1));
 263         }
 264     }
 265     aml_append(dev, aml_name_decl("_CRS", rbuf));
 266
 267     acpi_dsdt_add_pci_osc(dev);
 268
 269     Aml *dev_res0 = aml_device("%s", "RES0");
 270     aml_append(dev_res0, aml_name_decl("_HID", aml_string("PNP0C02")));
 271     crs = aml_resource_template();
 272     aml_append(crs,
 273         aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
 274                          AML_NON_CACHEABLE, AML_READ_WRITE, 0x0000,
 275                          cfg->ecam.base,
 276                          cfg->ecam.base + cfg->ecam.size - 1,
 277                          0x0000,
 278                          cfg->ecam.size));
 279     aml_append(dev_res0, aml_name_decl("_CRS", crs));
 280     aml_append(dev, dev_res0);
 281     aml_append(scope, dev);
 282
 283     crs_range_set_free(&crs_range_set);
 284 }
 285
 286 void acpi_dsdt_add_gpex_host(Aml *scope, uint32_t irq)
 287 {
 288     bool ambig;
 289     Object *obj = object_resolve_path_type("", TYPE_GPEX_HOST, &ambig);
 290
 291     if (!obj || ambig) {
 292         return;
 293     }
 294
 295     GPEX_HOST(obj)->gpex_cfg.irq = irq;
 296     acpi_dsdt_add_gpex(scope, &GPEX_HOST(obj)->gpex_cfg);
 297 }