?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
Merge tag 'pull-loongarch-20241016' of https://gitlab.com/gaosong/qemu into staging
[qemu/armbru.git] / hw / pci-host / gt64120.c
blob14fc803d27948d12394edfd2f9d19b72a9fdfd0a
1 /*
2 * QEMU GT64120 PCI host
3 *
4 * (Datasheet GT-64120 Rev 1.4 from Sep 14, 1999)
5 *
6 * Copyright (c) 2006,2007 Aurelien Jarno
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a copy
9 * of this software and associated documentation files (the "Software"), to deal
10 * in the Software without restriction, including without limitation the rights
11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
12 * copies of the Software, and to permit persons to whom the Software is
13 * furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice shall be included in
16 * all copies or substantial portions of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
24 * THE SOFTWARE.
25 */
26
27 #include "qemu/osdep.h"
28 #include "qapi/error.h"
29 #include "qemu/units.h"
30 #include "qemu/log.h"
31 #include "hw/qdev-properties.h"
32 #include "hw/registerfields.h"
33 #include "hw/pci/pci_device.h"
34 #include "hw/pci/pci_host.h"
35 #include "hw/misc/empty_slot.h"
36 #include "migration/vmstate.h"
37 #include "hw/intc/i8259.h"
38 #include "hw/irq.h"
39 #include "trace.h"
40 #include "qom/object.h"
41
42 #define GT_REGS (0x1000 >> 2)
43
44 /* CPU Configuration */
45 #define GT_CPU (0x000 >> 2)
46 #define GT_MULTI (0x120 >> 2)
47
48 REG32(GT_CPU, 0x000)
49 FIELD(GT_CPU, Endianness, 12, 1)
50
51 /* CPU Address Decode */
52 #define GT_SCS10LD (0x008 >> 2)
53 #define GT_SCS10HD (0x010 >> 2)
54 #define GT_SCS32LD (0x018 >> 2)
55 #define GT_SCS32HD (0x020 >> 2)
56 #define GT_CS20LD (0x028 >> 2)
57 #define GT_CS20HD (0x030 >> 2)
58 #define GT_CS3BOOTLD (0x038 >> 2)
59 #define GT_CS3BOOTHD (0x040 >> 2)
60 #define GT_PCI0IOLD (0x048 >> 2)
61 #define GT_PCI0IOHD (0x050 >> 2)
62 #define GT_PCI0M0LD (0x058 >> 2)
63 #define GT_PCI0M0HD (0x060 >> 2)
64 #define GT_PCI0M1LD (0x080 >> 2)
65 #define GT_PCI0M1HD (0x088 >> 2)
66 #define GT_PCI1IOLD (0x090 >> 2)
67 #define GT_PCI1IOHD (0x098 >> 2)
68 #define GT_PCI1M0LD (0x0a0 >> 2)
69 #define GT_PCI1M0HD (0x0a8 >> 2)
70 #define GT_PCI1M1LD (0x0b0 >> 2)
71 #define GT_PCI1M1HD (0x0b8 >> 2)
72 #define GT_ISD (0x068 >> 2)
73
74 #define GT_SCS10AR (0x0d0 >> 2)
75 #define GT_SCS32AR (0x0d8 >> 2)
76 #define GT_CS20R (0x0e0 >> 2)
77 #define GT_CS3BOOTR (0x0e8 >> 2)
78
79 #define GT_PCI0IOREMAP (0x0f0 >> 2)
80 #define GT_PCI0M0REMAP (0x0f8 >> 2)
81 #define GT_PCI0M1REMAP (0x100 >> 2)
82 #define GT_PCI1IOREMAP (0x108 >> 2)
83 #define GT_PCI1M0REMAP (0x110 >> 2)
84 #define GT_PCI1M1REMAP (0x118 >> 2)
85
86 /* CPU Error Report */
87 #define GT_CPUERR_ADDRLO (0x070 >> 2)
88 #define GT_CPUERR_ADDRHI (0x078 >> 2)
89 #define GT_CPUERR_DATALO (0x128 >> 2) /* GT-64120A only */
90 #define GT_CPUERR_DATAHI (0x130 >> 2) /* GT-64120A only */
91 #define GT_CPUERR_PARITY (0x138 >> 2) /* GT-64120A only */
92
93 /* CPU Sync Barrier */
94 #define GT_PCI0SYNC (0x0c0 >> 2)
95 #define GT_PCI1SYNC (0x0c8 >> 2)
96
97 /* SDRAM and Device Address Decode */
98 #define GT_SCS0LD (0x400 >> 2)
99 #define GT_SCS0HD (0x404 >> 2)
100 #define GT_SCS1LD (0x408 >> 2)
101 #define GT_SCS1HD (0x40c >> 2)
102 #define GT_SCS2LD (0x410 >> 2)
103 #define GT_SCS2HD (0x414 >> 2)
104 #define GT_SCS3LD (0x418 >> 2)
105 #define GT_SCS3HD (0x41c >> 2)
106 #define GT_CS0LD (0x420 >> 2)
107 #define GT_CS0HD (0x424 >> 2)
108 #define GT_CS1LD (0x428 >> 2)
109 #define GT_CS1HD (0x42c >> 2)
110 #define GT_CS2LD (0x430 >> 2)
111 #define GT_CS2HD (0x434 >> 2)
112 #define GT_CS3LD (0x438 >> 2)
113 #define GT_CS3HD (0x43c >> 2)
114 #define GT_BOOTLD (0x440 >> 2)
115 #define GT_BOOTHD (0x444 >> 2)
116 #define GT_ADERR (0x470 >> 2)
117
118 /* SDRAM Configuration */
119 #define GT_SDRAM_CFG (0x448 >> 2)
120 #define GT_SDRAM_OPMODE (0x474 >> 2)
121 #define GT_SDRAM_BM (0x478 >> 2)
122 #define GT_SDRAM_ADDRDECODE (0x47c >> 2)
123
124 /* SDRAM Parameters */
125 #define GT_SDRAM_B0 (0x44c >> 2)
126 #define GT_SDRAM_B1 (0x450 >> 2)
127 #define GT_SDRAM_B2 (0x454 >> 2)
128 #define GT_SDRAM_B3 (0x458 >> 2)
129
130 /* Device Parameters */
131 #define GT_DEV_B0 (0x45c >> 2)
132 #define GT_DEV_B1 (0x460 >> 2)
133 #define GT_DEV_B2 (0x464 >> 2)
134 #define GT_DEV_B3 (0x468 >> 2)
135 #define GT_DEV_BOOT (0x46c >> 2)
136
137 /* ECC */
138 #define GT_ECC_ERRDATALO (0x480 >> 2) /* GT-64120A only */
139 #define GT_ECC_ERRDATAHI (0x484 >> 2) /* GT-64120A only */
140 #define GT_ECC_MEM (0x488 >> 2) /* GT-64120A only */
141 #define GT_ECC_CALC (0x48c >> 2) /* GT-64120A only */
142 #define GT_ECC_ERRADDR (0x490 >> 2) /* GT-64120A only */
143
144 /* DMA Record */
145 #define GT_DMA0_CNT (0x800 >> 2)
146 #define GT_DMA1_CNT (0x804 >> 2)
147 #define GT_DMA2_CNT (0x808 >> 2)
148 #define GT_DMA3_CNT (0x80c >> 2)
149 #define GT_DMA0_SA (0x810 >> 2)
150 #define GT_DMA1_SA (0x814 >> 2)
151 #define GT_DMA2_SA (0x818 >> 2)
152 #define GT_DMA3_SA (0x81c >> 2)
153 #define GT_DMA0_DA (0x820 >> 2)
154 #define GT_DMA1_DA (0x824 >> 2)
155 #define GT_DMA2_DA (0x828 >> 2)
156 #define GT_DMA3_DA (0x82c >> 2)
157 #define GT_DMA0_NEXT (0x830 >> 2)
158 #define GT_DMA1_NEXT (0x834 >> 2)
159 #define GT_DMA2_NEXT (0x838 >> 2)
160 #define GT_DMA3_NEXT (0x83c >> 2)
161 #define GT_DMA0_CUR (0x870 >> 2)
162 #define GT_DMA1_CUR (0x874 >> 2)
163 #define GT_DMA2_CUR (0x878 >> 2)
164 #define GT_DMA3_CUR (0x87c >> 2)
165
166 /* DMA Channel Control */
167 #define GT_DMA0_CTRL (0x840 >> 2)
168 #define GT_DMA1_CTRL (0x844 >> 2)
169 #define GT_DMA2_CTRL (0x848 >> 2)
170 #define GT_DMA3_CTRL (0x84c >> 2)
171
172 /* DMA Arbiter */
173 #define GT_DMA_ARB (0x860 >> 2)
174
175 /* Timer/Counter */
176 #define GT_TC0 (0x850 >> 2)
177 #define GT_TC1 (0x854 >> 2)
178 #define GT_TC2 (0x858 >> 2)
179 #define GT_TC3 (0x85c >> 2)
180 #define GT_TC_CONTROL (0x864 >> 2)
181
182 /* PCI Internal */
183 #define GT_PCI0_CMD (0xc00 >> 2)
184 #define GT_PCI0_TOR (0xc04 >> 2)
185 #define GT_PCI0_BS_SCS10 (0xc08 >> 2)
186 #define GT_PCI0_BS_SCS32 (0xc0c >> 2)
187 #define GT_PCI0_BS_CS20 (0xc10 >> 2)
188 #define GT_PCI0_BS_CS3BT (0xc14 >> 2)
189 #define GT_PCI1_IACK (0xc30 >> 2)
190 #define GT_PCI0_IACK (0xc34 >> 2)
191 #define GT_PCI0_BARE (0xc3c >> 2)
192 #define GT_PCI0_PREFMBR (0xc40 >> 2)
193 #define GT_PCI0_SCS10_BAR (0xc48 >> 2)
194 #define GT_PCI0_SCS32_BAR (0xc4c >> 2)
195 #define GT_PCI0_CS20_BAR (0xc50 >> 2)
196 #define GT_PCI0_CS3BT_BAR (0xc54 >> 2)
197 #define GT_PCI0_SSCS10_BAR (0xc58 >> 2)
198 #define GT_PCI0_SSCS32_BAR (0xc5c >> 2)
199 #define GT_PCI0_SCS3BT_BAR (0xc64 >> 2)
200 #define GT_PCI1_CMD (0xc80 >> 2)
201 #define GT_PCI1_TOR (0xc84 >> 2)
202 #define GT_PCI1_BS_SCS10 (0xc88 >> 2)
203 #define GT_PCI1_BS_SCS32 (0xc8c >> 2)
204 #define GT_PCI1_BS_CS20 (0xc90 >> 2)
205 #define GT_PCI1_BS_CS3BT (0xc94 >> 2)
206 #define GT_PCI1_BARE (0xcbc >> 2)
207 #define GT_PCI1_PREFMBR (0xcc0 >> 2)
208 #define GT_PCI1_SCS10_BAR (0xcc8 >> 2)
209 #define GT_PCI1_SCS32_BAR (0xccc >> 2)
210 #define GT_PCI1_CS20_BAR (0xcd0 >> 2)
211 #define GT_PCI1_CS3BT_BAR (0xcd4 >> 2)
212 #define GT_PCI1_SSCS10_BAR (0xcd8 >> 2)
213 #define GT_PCI1_SSCS32_BAR (0xcdc >> 2)
214 #define GT_PCI1_SCS3BT_BAR (0xce4 >> 2)
215 #define GT_PCI1_CFGADDR (0xcf0 >> 2)
216 #define GT_PCI1_CFGDATA (0xcf4 >> 2)
217 #define GT_PCI0_CFGADDR (0xcf8 >> 2)
218 #define GT_PCI0_CFGDATA (0xcfc >> 2)
219
220 REG32(GT_PCI0_CMD, 0xc00)
221 FIELD(GT_PCI0_CMD, MByteSwap, 0, 1)
222 FIELD(GT_PCI0_CMD, SByteSwap, 16, 1)
223 #define R_GT_PCI0_CMD_ByteSwap_MASK \
224 (R_GT_PCI0_CMD_MByteSwap_MASK | R_GT_PCI0_CMD_SByteSwap_MASK)
225 REG32(GT_PCI1_CMD, 0xc80)
226 FIELD(GT_PCI1_CMD, MByteSwap, 0, 1)
227 FIELD(GT_PCI1_CMD, SByteSwap, 16, 1)
228 #define R_GT_PCI1_CMD_ByteSwap_MASK \
229 (R_GT_PCI1_CMD_MByteSwap_MASK | R_GT_PCI1_CMD_SByteSwap_MASK)
230
231 /* Interrupts */
232 #define GT_INTRCAUSE (0xc18 >> 2)
233 #define GT_INTRMASK (0xc1c >> 2)
234 #define GT_PCI0_ICMASK (0xc24 >> 2)
235 #define GT_PCI0_SERR0MASK (0xc28 >> 2)
236 #define GT_CPU_INTSEL (0xc70 >> 2)
237 #define GT_PCI0_INTSEL (0xc74 >> 2)
238 #define GT_HINTRCAUSE (0xc98 >> 2)
239 #define GT_HINTRMASK (0xc9c >> 2)
240 #define GT_PCI0_HICMASK (0xca4 >> 2)
241 #define GT_PCI1_SERR1MASK (0xca8 >> 2)
242
243 #define PCI_MAPPING_ENTRY(regname) \
244 hwaddr regname ##_start; \
245 hwaddr regname ##_length; \
246 MemoryRegion regname ##_mem
247
248 #define TYPE_GT64120_PCI_HOST_BRIDGE "gt64120"
249
250 OBJECT_DECLARE_SIMPLE_TYPE(GT64120State, GT64120_PCI_HOST_BRIDGE)
251
252 struct GT64120State {
253 PCIHostState parent_obj;
254
255 uint32_t regs[GT_REGS];
256 PCI_MAPPING_ENTRY(PCI0IO);
257 PCI_MAPPING_ENTRY(PCI0M0);
258 PCI_MAPPING_ENTRY(PCI0M1);
259 PCI_MAPPING_ENTRY(ISD);
260 MemoryRegion pci0_mem;
261 AddressSpace pci0_mem_as;
262
263 /* properties */
264 bool cpu_little_endian;
265 };
266
267 /* Adjust range to avoid touching space which isn't mappable via PCI */
268 /*
269 * XXX: Hardcoded values for Malta: 0x1e000000 - 0x1f100000
270 * 0x1fc00000 - 0x1fd00000
271 */
272 static void check_reserved_space(hwaddr *start, hwaddr *length)
273 {
274 hwaddr begin = *start;
275 hwaddr end = *start + *length;
276
277 if (end >= 0x1e000000LL && end < 0x1f100000LL) {
278 end = 0x1e000000LL;
279 }
280 if (begin >= 0x1e000000LL && begin < 0x1f100000LL) {
281 begin = 0x1f100000LL;
282 }
283 if (end >= 0x1fc00000LL && end < 0x1fd00000LL) {
284 end = 0x1fc00000LL;
285 }
286 if (begin >= 0x1fc00000LL && begin < 0x1fd00000LL) {
287 begin = 0x1fd00000LL;
288 }
289 /* XXX: This is broken when a reserved range splits the requested range */
290 if (end >= 0x1f100000LL && begin < 0x1e000000LL) {
291 end = 0x1e000000LL;
292 }
293 if (end >= 0x1fd00000LL && begin < 0x1fc00000LL) {
294 end = 0x1fc00000LL;
295 }
296
297 *start = begin;
298 *length = end - begin;
299 }
300
301 static void gt64120_isd_mapping(GT64120State *s)
302 {
303 /* Bits 14:0 of ISD map to bits 35:21 of the start address. */
304 hwaddr start = ((hwaddr)s->regs[GT_ISD] << 21) & 0xFFFE00000ull;
305 hwaddr length = 0x1000;
306
307 memory_region_transaction_begin();
308
309 if (s->ISD_length) {
310 memory_region_del_subregion(get_system_memory(), &s->ISD_mem);
311 }
312 check_reserved_space(&start, &length);
313 length = 0x1000;
314 /* Map new address */
315 trace_gt64120_isd_remap(s->ISD_length, s->ISD_start, length, start);
316 s->ISD_start = start;
317 s->ISD_length = length;
318 memory_region_add_subregion(get_system_memory(), s->ISD_start, &s->ISD_mem);
319
320 memory_region_transaction_commit();
321 }
322
323 static void gt64120_update_pci_cfgdata_mapping(GT64120State *s)
324 {
325 /* Indexed on MByteSwap bit, see Table 158: PCI_0 Command, Offset: 0xc00 */
326 static const MemoryRegionOps *pci_host_data_ops[] = {
327 &pci_host_data_be_ops, &pci_host_data_le_ops
328 };
329 PCIHostState *phb = PCI_HOST_BRIDGE(s);
330
331 memory_region_transaction_begin();
332
333 /*
334 * The setting of the MByteSwap bit and MWordSwap bit in the PCI Internal
335 * Command Register determines how data transactions from the CPU to/from
336 * PCI are handled along with the setting of the Endianness bit in the CPU
337 * Configuration Register. See:
338 * - Table 16: 32-bit PCI Transaction Endianness
339 * - Table 158: PCI_0 Command, Offset: 0xc00
340 */
341
342 if (memory_region_is_mapped(&phb->data_mem)) {
343 memory_region_del_subregion(&s->ISD_mem, &phb->data_mem);
344 object_unparent(OBJECT(&phb->data_mem));
345 }
346 memory_region_init_io(&phb->data_mem, OBJECT(phb),
347 pci_host_data_ops[s->regs[GT_PCI0_CMD] & 1],
348 s, "pci-conf-data", 4);
349 memory_region_add_subregion_overlap(&s->ISD_mem, GT_PCI0_CFGDATA << 2,
350 &phb->data_mem, 1);
351
352 memory_region_transaction_commit();
353 }
354
355 static void gt64120_pci_mapping(GT64120State *s)
356 {
357 memory_region_transaction_begin();
358
359 /* Update PCI0IO mapping */
360 if ((s->regs[GT_PCI0IOLD] & 0x7f) <= s->regs[GT_PCI0IOHD]) {
361 /* Unmap old IO address */
362 if (s->PCI0IO_length) {
363 memory_region_del_subregion(get_system_memory(), &s->PCI0IO_mem);
364 object_unparent(OBJECT(&s->PCI0IO_mem));
365 }
366 /* Map new IO address */
367 s->PCI0IO_start = s->regs[GT_PCI0IOLD] << 21;
368 s->PCI0IO_length = ((s->regs[GT_PCI0IOHD] + 1) -
369 (s->regs[GT_PCI0IOLD] & 0x7f)) << 21;
370 if (s->PCI0IO_length) {
371 memory_region_init_alias(&s->PCI0IO_mem, OBJECT(s), "pci0-io",
372 get_system_io(), 0, s->PCI0IO_length);
373 memory_region_add_subregion(get_system_memory(), s->PCI0IO_start,
374 &s->PCI0IO_mem);
375 }
376 }
377
378 /* Update PCI0M0 mapping */
379 if ((s->regs[GT_PCI0M0LD] & 0x7f) <= s->regs[GT_PCI0M0HD]) {
380 /* Unmap old MEM address */
381 if (s->PCI0M0_length) {
382 memory_region_del_subregion(get_system_memory(), &s->PCI0M0_mem);
383 object_unparent(OBJECT(&s->PCI0M0_mem));
384 }
385 /* Map new mem address */
386 s->PCI0M0_start = s->regs[GT_PCI0M0LD] << 21;
387 s->PCI0M0_length = ((s->regs[GT_PCI0M0HD] + 1) -
388 (s->regs[GT_PCI0M0LD] & 0x7f)) << 21;
389 if (s->PCI0M0_length) {
390 memory_region_init_alias(&s->PCI0M0_mem, OBJECT(s), "pci0-mem0",
391 &s->pci0_mem, s->PCI0M0_start,
392 s->PCI0M0_length);
393 memory_region_add_subregion(get_system_memory(), s->PCI0M0_start,
394 &s->PCI0M0_mem);
395 }
396 }
397
398 /* Update PCI0M1 mapping */
399 if ((s->regs[GT_PCI0M1LD] & 0x7f) <= s->regs[GT_PCI0M1HD]) {
400 /* Unmap old MEM address */
401 if (s->PCI0M1_length) {
402 memory_region_del_subregion(get_system_memory(), &s->PCI0M1_mem);
403 object_unparent(OBJECT(&s->PCI0M1_mem));
404 }
405 /* Map new mem address */
406 s->PCI0M1_start = s->regs[GT_PCI0M1LD] << 21;
407 s->PCI0M1_length = ((s->regs[GT_PCI0M1HD] + 1) -
408 (s->regs[GT_PCI0M1LD] & 0x7f)) << 21;
409 if (s->PCI0M1_length) {
410 memory_region_init_alias(&s->PCI0M1_mem, OBJECT(s), "pci0-mem1",
411 &s->pci0_mem, s->PCI0M1_start,
412 s->PCI0M1_length);
413 memory_region_add_subregion(get_system_memory(), s->PCI0M1_start,
414 &s->PCI0M1_mem);
415 }
416 }
417
418 memory_region_transaction_commit();
419 }
420
421 static int gt64120_post_load(void *opaque, int version_id)
422 {
423 GT64120State *s = opaque;
424
425 gt64120_isd_mapping(s);
426 gt64120_pci_mapping(s);
427
428 return 0;
429 }
430
431 static const VMStateDescription vmstate_gt64120 = {
432 .name = "gt64120",
433 .version_id = 1,
434 .minimum_version_id = 1,
435 .post_load = gt64120_post_load,
436 .fields = (const VMStateField[]) {
437 VMSTATE_UINT32_ARRAY(regs, GT64120State, GT_REGS),
438 VMSTATE_END_OF_LIST()
439 }
440 };
441
442 static void gt64120_writel(void *opaque, hwaddr addr,
443 uint64_t val, unsigned size)
444 {
445 GT64120State *s = opaque;
446 uint32_t saddr = addr >> 2;
447
448 trace_gt64120_write(addr, val);
449 if (!(s->regs[GT_CPU] & 0x00001000)) {
450 val = bswap32(val);
451 }
452
453 switch (saddr) {
454
455 /* CPU Configuration */
456 case GT_CPU:
457 s->regs[GT_CPU] = val;
458 break;
459 case GT_MULTI:
460 /* Read-only register as only one GT64xxx is present on the CPU bus */
461 break;
462
463 /* CPU Address Decode */
464 case GT_PCI0IOLD:
465 s->regs[GT_PCI0IOLD] = val & 0x00007fff;
466 s->regs[GT_PCI0IOREMAP] = val & 0x000007ff;
467 gt64120_pci_mapping(s);
468 break;
469 case GT_PCI0M0LD:
470 s->regs[GT_PCI0M0LD] = val & 0x00007fff;
471 s->regs[GT_PCI0M0REMAP] = val & 0x000007ff;
472 gt64120_pci_mapping(s);
473 break;
474 case GT_PCI0M1LD:
475 s->regs[GT_PCI0M1LD] = val & 0x00007fff;
476 s->regs[GT_PCI0M1REMAP] = val & 0x000007ff;
477 gt64120_pci_mapping(s);
478 break;
479 case GT_PCI1IOLD:
480 s->regs[GT_PCI1IOLD] = val & 0x00007fff;
481 s->regs[GT_PCI1IOREMAP] = val & 0x000007ff;
482 break;
483 case GT_PCI1M0LD:
484 s->regs[GT_PCI1M0LD] = val & 0x00007fff;
485 s->regs[GT_PCI1M0REMAP] = val & 0x000007ff;
486 break;
487 case GT_PCI1M1LD:
488 s->regs[GT_PCI1M1LD] = val & 0x00007fff;
489 s->regs[GT_PCI1M1REMAP] = val & 0x000007ff;
490 break;
491 case GT_PCI0M0HD:
492 case GT_PCI0M1HD:
493 case GT_PCI0IOHD:
494 s->regs[saddr] = val & 0x0000007f;
495 gt64120_pci_mapping(s);
496 break;
497 case GT_PCI1IOHD:
498 case GT_PCI1M0HD:
499 case GT_PCI1M1HD:
500 s->regs[saddr] = val & 0x0000007f;
501 break;
502 case GT_ISD:
503 s->regs[saddr] = val & 0x00007fff;
504 gt64120_isd_mapping(s);
505 break;
506
507 case GT_PCI0IOREMAP:
508 case GT_PCI0M0REMAP:
509 case GT_PCI0M1REMAP:
510 case GT_PCI1IOREMAP:
511 case GT_PCI1M0REMAP:
512 case GT_PCI1M1REMAP:
513 s->regs[saddr] = val & 0x000007ff;
514 break;
515
516 /* CPU Error Report */
517 case GT_CPUERR_ADDRLO:
518 case GT_CPUERR_ADDRHI:
519 case GT_CPUERR_DATALO:
520 case GT_CPUERR_DATAHI:
521 case GT_CPUERR_PARITY:
522 /* Read-only registers, do nothing */
523 qemu_log_mask(LOG_GUEST_ERROR,
524 "gt64120: Read-only register write "
525 "reg:0x%03x size:%u value:0x%0*" PRIx64 "\n",
526 saddr << 2, size, size << 1, val);
527 break;
528
529 /* CPU Sync Barrier */
530 case GT_PCI0SYNC:
531 case GT_PCI1SYNC:
532 /* Read-only registers, do nothing */
533 qemu_log_mask(LOG_GUEST_ERROR,
534 "gt64120: Read-only register write "
535 "reg:0x%03x size:%u value:0x%0*" PRIx64 "\n",
536 saddr << 2, size, size << 1, val);
537 break;
538
539 /* SDRAM and Device Address Decode */
540 case GT_SCS0LD:
541 case GT_SCS0HD:
542 case GT_SCS1LD:
543 case GT_SCS1HD:
544 case GT_SCS2LD:
545 case GT_SCS2HD:
546 case GT_SCS3LD:
547 case GT_SCS3HD:
548 case GT_CS0LD:
549 case GT_CS0HD:
550 case GT_CS1LD:
551 case GT_CS1HD:
552 case GT_CS2LD:
553 case GT_CS2HD:
554 case GT_CS3LD:
555 case GT_CS3HD:
556 case GT_BOOTLD:
557 case GT_BOOTHD:
558 case GT_ADERR:
559 /* SDRAM Configuration */
560 case GT_SDRAM_CFG:
561 case GT_SDRAM_OPMODE:
562 case GT_SDRAM_BM:
563 case GT_SDRAM_ADDRDECODE:
564 /* Accept and ignore SDRAM interleave configuration */
565 s->regs[saddr] = val;
566 break;
567
568 /* Device Parameters */
569 case GT_DEV_B0:
570 case GT_DEV_B1:
571 case GT_DEV_B2:
572 case GT_DEV_B3:
573 case GT_DEV_BOOT:
574 /* Not implemented */
575 qemu_log_mask(LOG_UNIMP,
576 "gt64120: Unimplemented device register write "
577 "reg:0x%03x size:%u value:0x%0*" PRIx64 "\n",
578 saddr << 2, size, size << 1, val);
579 break;
580
581 /* ECC */
582 case GT_ECC_ERRDATALO:
583 case GT_ECC_ERRDATAHI:
584 case GT_ECC_MEM:
585 case GT_ECC_CALC:
586 case GT_ECC_ERRADDR:
587 /* Read-only registers, do nothing */
588 qemu_log_mask(LOG_GUEST_ERROR,
589 "gt64120: Read-only register write "
590 "reg:0x%03x size:%u value:0x%0*" PRIx64 "\n",
591 saddr << 2, size, size << 1, val);
592 break;
593
594 /* DMA Record */
595 case GT_DMA0_CNT:
596 case GT_DMA1_CNT:
597 case GT_DMA2_CNT:
598 case GT_DMA3_CNT:
599 case GT_DMA0_SA:
600 case GT_DMA1_SA:
601 case GT_DMA2_SA:
602 case GT_DMA3_SA:
603 case GT_DMA0_DA:
604 case GT_DMA1_DA:
605 case GT_DMA2_DA:
606 case GT_DMA3_DA:
607 case GT_DMA0_NEXT:
608 case GT_DMA1_NEXT:
609 case GT_DMA2_NEXT:
610 case GT_DMA3_NEXT:
611 case GT_DMA0_CUR:
612 case GT_DMA1_CUR:
613 case GT_DMA2_CUR:
614 case GT_DMA3_CUR:
615
616 /* DMA Channel Control */
617 case GT_DMA0_CTRL:
618 case GT_DMA1_CTRL:
619 case GT_DMA2_CTRL:
620 case GT_DMA3_CTRL:
621
622 /* DMA Arbiter */
623 case GT_DMA_ARB:
624 /* Not implemented */
625 qemu_log_mask(LOG_UNIMP,
626 "gt64120: Unimplemented DMA register write "
627 "reg:0x%03x size:%u value:0x%0*" PRIx64 "\n",
628 saddr << 2, size, size << 1, val);
629 break;
630
631 /* Timer/Counter */
632 case GT_TC0:
633 case GT_TC1:
634 case GT_TC2:
635 case GT_TC3:
636 case GT_TC_CONTROL:
637 /* Not implemented */
638 qemu_log_mask(LOG_UNIMP,
639 "gt64120: Unimplemented timer register write "
640 "reg:0x%03x size:%u value:0x%0*" PRIx64 "\n",
641 saddr << 2, size, size << 1, val);
642 break;
643
644 /* PCI Internal */
645 case GT_PCI0_CMD:
646 case GT_PCI1_CMD:
647 s->regs[saddr] = val & 0x0401fc0f;
648 gt64120_update_pci_cfgdata_mapping(s);
649 break;
650 case GT_PCI0_TOR:
651 case GT_PCI0_BS_SCS10:
652 case GT_PCI0_BS_SCS32:
653 case GT_PCI0_BS_CS20:
654 case GT_PCI0_BS_CS3BT:
655 case GT_PCI1_IACK:
656 case GT_PCI0_IACK:
657 case GT_PCI0_BARE:
658 case GT_PCI0_PREFMBR:
659 case GT_PCI0_SCS10_BAR:
660 case GT_PCI0_SCS32_BAR:
661 case GT_PCI0_CS20_BAR:
662 case GT_PCI0_CS3BT_BAR:
663 case GT_PCI0_SSCS10_BAR:
664 case GT_PCI0_SSCS32_BAR:
665 case GT_PCI0_SCS3BT_BAR:
666 case GT_PCI1_TOR:
667 case GT_PCI1_BS_SCS10:
668 case GT_PCI1_BS_SCS32:
669 case GT_PCI1_BS_CS20:
670 case GT_PCI1_BS_CS3BT:
671 case GT_PCI1_BARE:
672 case GT_PCI1_PREFMBR:
673 case GT_PCI1_SCS10_BAR:
674 case GT_PCI1_SCS32_BAR:
675 case GT_PCI1_CS20_BAR:
676 case GT_PCI1_CS3BT_BAR:
677 case GT_PCI1_SSCS10_BAR:
678 case GT_PCI1_SSCS32_BAR:
679 case GT_PCI1_SCS3BT_BAR:
680 case GT_PCI1_CFGADDR:
681 case GT_PCI1_CFGDATA:
682 /* not implemented */
683 qemu_log_mask(LOG_UNIMP,
684 "gt64120: Unimplemented PCI register write "
685 "reg:0x%03x size:%u value:0x%0*" PRIx64 "\n",
686 saddr << 2, size, size << 1, val);
687 break;
688 case GT_PCI0_CFGADDR:
689 case GT_PCI0_CFGDATA:
690 /* Mapped via in gt64120_pci_mapping() */
691 g_assert_not_reached();
692
693 /* Interrupts */
694 case GT_INTRCAUSE:
695 /* not really implemented */
696 s->regs[saddr] = ~(~(s->regs[saddr]) | ~(val & 0xfffffffe));
697 s->regs[saddr] |= !!(s->regs[saddr] & 0xfffffffe);
698 trace_gt64120_write_intreg("INTRCAUSE", size, val);
699 break;
700 case GT_INTRMASK:
701 s->regs[saddr] = val & 0x3c3ffffe;
702 trace_gt64120_write_intreg("INTRMASK", size, val);
703 break;
704 case GT_PCI0_ICMASK:
705 s->regs[saddr] = val & 0x03fffffe;
706 trace_gt64120_write_intreg("ICMASK", size, val);
707 break;
708 case GT_PCI0_SERR0MASK:
709 s->regs[saddr] = val & 0x0000003f;
710 trace_gt64120_write_intreg("SERR0MASK", size, val);
711 break;
712
713 /* Reserved when only PCI_0 is configured. */
714 case GT_HINTRCAUSE:
715 case GT_CPU_INTSEL:
716 case GT_PCI0_INTSEL:
717 case GT_HINTRMASK:
718 case GT_PCI0_HICMASK:
719 case GT_PCI1_SERR1MASK:
720 /* not implemented */
721 break;
722
723 /* SDRAM Parameters */
724 case GT_SDRAM_B0:
725 case GT_SDRAM_B1:
726 case GT_SDRAM_B2:
727 case GT_SDRAM_B3:
728 /*
729 * We don't simulate electrical parameters of the SDRAM.
730 * Accept, but ignore the values.
731 */
732 s->regs[saddr] = val;
733 break;
734
735 default:
736 qemu_log_mask(LOG_GUEST_ERROR,
737 "gt64120: Illegal register write "
738 "reg:0x%03x size:%u value:0x%0*" PRIx64 "\n",
739 saddr << 2, size, size << 1, val);
740 break;
741 }
742 }
743
744 static uint64_t gt64120_readl(void *opaque,
745 hwaddr addr, unsigned size)
746 {
747 GT64120State *s = opaque;
748 uint32_t val;
749 uint32_t saddr = addr >> 2;
750
751 switch (saddr) {
752
753 /* CPU Configuration */
754 case GT_MULTI:
755 /*
756 * Only one GT64xxx is present on the CPU bus, return
757 * the initial value.
758 */
759 val = s->regs[saddr];
760 break;
761
762 /* CPU Error Report */
763 case GT_CPUERR_ADDRLO:
764 case GT_CPUERR_ADDRHI:
765 case GT_CPUERR_DATALO:
766 case GT_CPUERR_DATAHI:
767 case GT_CPUERR_PARITY:
768 /* Emulated memory has no error, always return the initial values. */
769 val = s->regs[saddr];
770 break;
771
772 /* CPU Sync Barrier */
773 case GT_PCI0SYNC:
774 case GT_PCI1SYNC:
775 /*
776 * Reading those register should empty all FIFO on the PCI
777 * bus, which are not emulated. The return value should be
778 * a random value that should be ignored.
779 */
780 val = 0xc000ffee;
781 break;
782
783 /* ECC */
784 case GT_ECC_ERRDATALO:
785 case GT_ECC_ERRDATAHI:
786 case GT_ECC_MEM:
787 case GT_ECC_CALC:
788 case GT_ECC_ERRADDR:
789 /* Emulated memory has no error, always return the initial values. */
790 val = s->regs[saddr];
791 break;
792
793 case GT_CPU:
794 case GT_SCS10LD:
795 case GT_SCS10HD:
796 case GT_SCS32LD:
797 case GT_SCS32HD:
798 case GT_CS20LD:
799 case GT_CS20HD:
800 case GT_CS3BOOTLD:
801 case GT_CS3BOOTHD:
802 case GT_SCS10AR:
803 case GT_SCS32AR:
804 case GT_CS20R:
805 case GT_CS3BOOTR:
806 case GT_PCI0IOLD:
807 case GT_PCI0M0LD:
808 case GT_PCI0M1LD:
809 case GT_PCI1IOLD:
810 case GT_PCI1M0LD:
811 case GT_PCI1M1LD:
812 case GT_PCI0IOHD:
813 case GT_PCI0M0HD:
814 case GT_PCI0M1HD:
815 case GT_PCI1IOHD:
816 case GT_PCI1M0HD:
817 case GT_PCI1M1HD:
818 case GT_PCI0IOREMAP:
819 case GT_PCI0M0REMAP:
820 case GT_PCI0M1REMAP:
821 case GT_PCI1IOREMAP:
822 case GT_PCI1M0REMAP:
823 case GT_PCI1M1REMAP:
824 case GT_ISD:
825 val = s->regs[saddr];
826 break;
827 case GT_PCI0_IACK:
828 /* Read the IRQ number */
829 val = pic_read_irq(isa_pic);
830 break;
831
832 /* SDRAM and Device Address Decode */
833 case GT_SCS0LD:
834 case GT_SCS0HD:
835 case GT_SCS1LD:
836 case GT_SCS1HD:
837 case GT_SCS2LD:
838 case GT_SCS2HD:
839 case GT_SCS3LD:
840 case GT_SCS3HD:
841 case GT_CS0LD:
842 case GT_CS0HD:
843 case GT_CS1LD:
844 case GT_CS1HD:
845 case GT_CS2LD:
846 case GT_CS2HD:
847 case GT_CS3LD:
848 case GT_CS3HD:
849 case GT_BOOTLD:
850 case GT_BOOTHD:
851 case GT_ADERR:
852 val = s->regs[saddr];
853 break;
854
855 /* SDRAM Configuration */
856 case GT_SDRAM_CFG:
857 case GT_SDRAM_OPMODE:
858 case GT_SDRAM_BM:
859 case GT_SDRAM_ADDRDECODE:
860 val = s->regs[saddr];
861 break;
862
863 /* SDRAM Parameters */
864 case GT_SDRAM_B0:
865 case GT_SDRAM_B1:
866 case GT_SDRAM_B2:
867 case GT_SDRAM_B3:
868 /*
869 * We don't simulate electrical parameters of the SDRAM.
870 * Just return the last written value.
871 */
872 val = s->regs[saddr];
873 break;
874
875 /* Device Parameters */
876 case GT_DEV_B0:
877 case GT_DEV_B1:
878 case GT_DEV_B2:
879 case GT_DEV_B3:
880 case GT_DEV_BOOT:
881 val = s->regs[saddr];
882 break;
883
884 /* DMA Record */
885 case GT_DMA0_CNT:
886 case GT_DMA1_CNT:
887 case GT_DMA2_CNT:
888 case GT_DMA3_CNT:
889 case GT_DMA0_SA:
890 case GT_DMA1_SA:
891 case GT_DMA2_SA:
892 case GT_DMA3_SA:
893 case GT_DMA0_DA:
894 case GT_DMA1_DA:
895 case GT_DMA2_DA:
896 case GT_DMA3_DA:
897 case GT_DMA0_NEXT:
898 case GT_DMA1_NEXT:
899 case GT_DMA2_NEXT:
900 case GT_DMA3_NEXT:
901 case GT_DMA0_CUR:
902 case GT_DMA1_CUR:
903 case GT_DMA2_CUR:
904 case GT_DMA3_CUR:
905 val = s->regs[saddr];
906 break;
907
908 /* DMA Channel Control */
909 case GT_DMA0_CTRL:
910 case GT_DMA1_CTRL:
911 case GT_DMA2_CTRL:
912 case GT_DMA3_CTRL:
913 val = s->regs[saddr];
914 break;
915
916 /* DMA Arbiter */
917 case GT_DMA_ARB:
918 val = s->regs[saddr];
919 break;
920
921 /* Timer/Counter */
922 case GT_TC0:
923 case GT_TC1:
924 case GT_TC2:
925 case GT_TC3:
926 case GT_TC_CONTROL:
927 val = s->regs[saddr];
928 break;
929
930 /* PCI Internal */
931 case GT_PCI0_CFGADDR:
932 case GT_PCI0_CFGDATA:
933 /* Mapped via in gt64120_pci_mapping() */
934 g_assert_not_reached();
935
936 case GT_PCI0_CMD:
937 case GT_PCI0_TOR:
938 case GT_PCI0_BS_SCS10:
939 case GT_PCI0_BS_SCS32:
940 case GT_PCI0_BS_CS20:
941 case GT_PCI0_BS_CS3BT:
942 case GT_PCI1_IACK:
943 case GT_PCI0_BARE:
944 case GT_PCI0_PREFMBR:
945 case GT_PCI0_SCS10_BAR:
946 case GT_PCI0_SCS32_BAR:
947 case GT_PCI0_CS20_BAR:
948 case GT_PCI0_CS3BT_BAR:
949 case GT_PCI0_SSCS10_BAR:
950 case GT_PCI0_SSCS32_BAR:
951 case GT_PCI0_SCS3BT_BAR:
952 case GT_PCI1_CMD:
953 case GT_PCI1_TOR:
954 case GT_PCI1_BS_SCS10:
955 case GT_PCI1_BS_SCS32:
956 case GT_PCI1_BS_CS20:
957 case GT_PCI1_BS_CS3BT:
958 case GT_PCI1_BARE:
959 case GT_PCI1_PREFMBR:
960 case GT_PCI1_SCS10_BAR:
961 case GT_PCI1_SCS32_BAR:
962 case GT_PCI1_CS20_BAR:
963 case GT_PCI1_CS3BT_BAR:
964 case GT_PCI1_SSCS10_BAR:
965 case GT_PCI1_SSCS32_BAR:
966 case GT_PCI1_SCS3BT_BAR:
967 case GT_PCI1_CFGADDR:
968 case GT_PCI1_CFGDATA:
969 val = s->regs[saddr];
970 break;
971
972 /* Interrupts */
973 case GT_INTRCAUSE:
974 val = s->regs[saddr];
975 trace_gt64120_read_intreg("INTRCAUSE", size, val);
976 break;
977 case GT_INTRMASK:
978 val = s->regs[saddr];
979 trace_gt64120_read_intreg("INTRMASK", size, val);
980 break;
981 case GT_PCI0_ICMASK:
982 val = s->regs[saddr];
983 trace_gt64120_read_intreg("ICMASK", size, val);
984 break;
985 case GT_PCI0_SERR0MASK:
986 val = s->regs[saddr];
987 trace_gt64120_read_intreg("SERR0MASK", size, val);
988 break;
989
990 /* Reserved when only PCI_0 is configured. */
991 case GT_HINTRCAUSE:
992 case GT_CPU_INTSEL:
993 case GT_PCI0_INTSEL:
994 case GT_HINTRMASK:
995 case GT_PCI0_HICMASK:
996 case GT_PCI1_SERR1MASK:
997 val = s->regs[saddr];
998 break;
999
1000 default:
1001 val = s->regs[saddr];
1002 qemu_log_mask(LOG_GUEST_ERROR,
1003 "gt64120: Illegal register read "
1004 "reg:0x%03x size:%u value:0x%0*x\n",
1005 saddr << 2, size, size << 1, val);
1006 break;
1007 }
1008
1009 if (!(s->regs[GT_CPU] & 0x00001000)) {
1010 val = bswap32(val);
1011 }
1012 trace_gt64120_read(addr, val);
1013
1014 return val;
1015 }
1016
1017 static const MemoryRegionOps isd_mem_ops = {
1018 .read = gt64120_readl,
1019 .write = gt64120_writel,
1020 .endianness = DEVICE_NATIVE_ENDIAN,
1021 .impl = {
1022 .min_access_size = 4,
1023 .max_access_size = 4,
1024 },
1025 };
1026
1027 static void gt64120_reset(DeviceState *dev)
1028 {
1029 GT64120State *s = GT64120_PCI_HOST_BRIDGE(dev);
1030
1031 /* FIXME: Malta specific hw assumptions ahead */
1032
1033 /* CPU Configuration */
1034 s->regs[GT_CPU] = s->cpu_little_endian ? R_GT_CPU_Endianness_MASK : 0;
1035 s->regs[GT_MULTI] = 0x00000003;
1036
1037 /* CPU Address decode */
1038 s->regs[GT_SCS10LD] = 0x00000000;
1039 s->regs[GT_SCS10HD] = 0x00000007;
1040 s->regs[GT_SCS32LD] = 0x00000008;
1041 s->regs[GT_SCS32HD] = 0x0000000f;
1042 s->regs[GT_CS20LD] = 0x000000e0;
1043 s->regs[GT_CS20HD] = 0x00000070;
1044 s->regs[GT_CS3BOOTLD] = 0x000000f8;
1045 s->regs[GT_CS3BOOTHD] = 0x0000007f;
1046
1047 s->regs[GT_PCI0IOLD] = 0x00000080;
1048 s->regs[GT_PCI0IOHD] = 0x0000000f;
1049 s->regs[GT_PCI0M0LD] = 0x00000090;
1050 s->regs[GT_PCI0M0HD] = 0x0000001f;
1051 s->regs[GT_ISD] = 0x000000a0;
1052 s->regs[GT_PCI0M1LD] = 0x00000790;
1053 s->regs[GT_PCI0M1HD] = 0x0000001f;
1054 s->regs[GT_PCI1IOLD] = 0x00000100;
1055 s->regs[GT_PCI1IOHD] = 0x0000000f;
1056 s->regs[GT_PCI1M0LD] = 0x00000110;
1057 s->regs[GT_PCI1M0HD] = 0x0000001f;
1058 s->regs[GT_PCI1M1LD] = 0x00000120;
1059 s->regs[GT_PCI1M1HD] = 0x0000002f;
1060
1061 s->regs[GT_SCS10AR] = 0x00000000;
1062 s->regs[GT_SCS32AR] = 0x00000008;
1063 s->regs[GT_CS20R] = 0x000000e0;
1064 s->regs[GT_CS3BOOTR] = 0x000000f8;
1065
1066 s->regs[GT_PCI0IOREMAP] = 0x00000080;
1067 s->regs[GT_PCI0M0REMAP] = 0x00000090;
1068 s->regs[GT_PCI0M1REMAP] = 0x00000790;
1069 s->regs[GT_PCI1IOREMAP] = 0x00000100;
1070 s->regs[GT_PCI1M0REMAP] = 0x00000110;
1071 s->regs[GT_PCI1M1REMAP] = 0x00000120;
1072
1073 /* CPU Error Report */
1074 s->regs[GT_CPUERR_ADDRLO] = 0x00000000;
1075 s->regs[GT_CPUERR_ADDRHI] = 0x00000000;
1076 s->regs[GT_CPUERR_DATALO] = 0xffffffff;
1077 s->regs[GT_CPUERR_DATAHI] = 0xffffffff;
1078 s->regs[GT_CPUERR_PARITY] = 0x000000ff;
1079
1080 /* CPU Sync Barrier */
1081 s->regs[GT_PCI0SYNC] = 0x00000000;
1082 s->regs[GT_PCI1SYNC] = 0x00000000;
1083
1084 /* SDRAM and Device Address Decode */
1085 s->regs[GT_SCS0LD] = 0x00000000;
1086 s->regs[GT_SCS0HD] = 0x00000007;
1087 s->regs[GT_SCS1LD] = 0x00000008;
1088 s->regs[GT_SCS1HD] = 0x0000000f;
1089 s->regs[GT_SCS2LD] = 0x00000010;
1090 s->regs[GT_SCS2HD] = 0x00000017;
1091 s->regs[GT_SCS3LD] = 0x00000018;
1092 s->regs[GT_SCS3HD] = 0x0000001f;
1093 s->regs[GT_CS0LD] = 0x000000c0;
1094 s->regs[GT_CS0HD] = 0x000000c7;
1095 s->regs[GT_CS1LD] = 0x000000c8;
1096 s->regs[GT_CS1HD] = 0x000000cf;
1097 s->regs[GT_CS2LD] = 0x000000d0;
1098 s->regs[GT_CS2HD] = 0x000000df;
1099 s->regs[GT_CS3LD] = 0x000000f0;
1100 s->regs[GT_CS3HD] = 0x000000fb;
1101 s->regs[GT_BOOTLD] = 0x000000fc;
1102 s->regs[GT_BOOTHD] = 0x000000ff;
1103 s->regs[GT_ADERR] = 0xffffffff;
1104
1105 /* SDRAM Configuration */
1106 s->regs[GT_SDRAM_CFG] = 0x00000200;
1107 s->regs[GT_SDRAM_OPMODE] = 0x00000000;
1108 s->regs[GT_SDRAM_BM] = 0x00000007;
1109 s->regs[GT_SDRAM_ADDRDECODE] = 0x00000002;
1110
1111 /* SDRAM Parameters */
1112 s->regs[GT_SDRAM_B0] = 0x00000005;
1113 s->regs[GT_SDRAM_B1] = 0x00000005;
1114 s->regs[GT_SDRAM_B2] = 0x00000005;
1115 s->regs[GT_SDRAM_B3] = 0x00000005;
1116
1117 /* ECC */
1118 s->regs[GT_ECC_ERRDATALO] = 0x00000000;
1119 s->regs[GT_ECC_ERRDATAHI] = 0x00000000;
1120 s->regs[GT_ECC_MEM] = 0x00000000;
1121 s->regs[GT_ECC_CALC] = 0x00000000;
1122 s->regs[GT_ECC_ERRADDR] = 0x00000000;
1123
1124 /* Device Parameters */
1125 s->regs[GT_DEV_B0] = 0x386fffff;
1126 s->regs[GT_DEV_B1] = 0x386fffff;
1127 s->regs[GT_DEV_B2] = 0x386fffff;
1128 s->regs[GT_DEV_B3] = 0x386fffff;
1129 s->regs[GT_DEV_BOOT] = 0x146fffff;
1130
1131 /* DMA registers are all zeroed at reset */
1132
1133 /* Timer/Counter */
1134 s->regs[GT_TC0] = 0xffffffff;
1135 s->regs[GT_TC1] = 0x00ffffff;
1136 s->regs[GT_TC2] = 0x00ffffff;
1137 s->regs[GT_TC3] = 0x00ffffff;
1138 s->regs[GT_TC_CONTROL] = 0x00000000;
1139
1140 /* PCI Internal */
1141 s->regs[GT_PCI0_CMD] = s->cpu_little_endian ? R_GT_PCI0_CMD_ByteSwap_MASK : 0;
1142 s->regs[GT_PCI0_TOR] = 0x0000070f;
1143 s->regs[GT_PCI0_BS_SCS10] = 0x00fff000;
1144 s->regs[GT_PCI0_BS_SCS32] = 0x00fff000;
1145 s->regs[GT_PCI0_BS_CS20] = 0x01fff000;
1146 s->regs[GT_PCI0_BS_CS3BT] = 0x00fff000;
1147 s->regs[GT_PCI1_IACK] = 0x00000000;
1148 s->regs[GT_PCI0_IACK] = 0x00000000;
1149 s->regs[GT_PCI0_BARE] = 0x0000000f;
1150 s->regs[GT_PCI0_PREFMBR] = 0x00000040;
1151 s->regs[GT_PCI0_SCS10_BAR] = 0x00000000;
1152 s->regs[GT_PCI0_SCS32_BAR] = 0x01000000;
1153 s->regs[GT_PCI0_CS20_BAR] = 0x1c000000;
1154 s->regs[GT_PCI0_CS3BT_BAR] = 0x1f000000;
1155 s->regs[GT_PCI0_SSCS10_BAR] = 0x00000000;
1156 s->regs[GT_PCI0_SSCS32_BAR] = 0x01000000;
1157 s->regs[GT_PCI0_SCS3BT_BAR] = 0x1f000000;
1158 s->regs[GT_PCI1_CMD] = s->cpu_little_endian ? R_GT_PCI1_CMD_ByteSwap_MASK : 0;
1159 s->regs[GT_PCI1_TOR] = 0x0000070f;
1160 s->regs[GT_PCI1_BS_SCS10] = 0x00fff000;
1161 s->regs[GT_PCI1_BS_SCS32] = 0x00fff000;
1162 s->regs[GT_PCI1_BS_CS20] = 0x01fff000;
1163 s->regs[GT_PCI1_BS_CS3BT] = 0x00fff000;
1164 s->regs[GT_PCI1_BARE] = 0x0000000f;
1165 s->regs[GT_PCI1_PREFMBR] = 0x00000040;
1166 s->regs[GT_PCI1_SCS10_BAR] = 0x00000000;
1167 s->regs[GT_PCI1_SCS32_BAR] = 0x01000000;
1168 s->regs[GT_PCI1_CS20_BAR] = 0x1c000000;
1169 s->regs[GT_PCI1_CS3BT_BAR] = 0x1f000000;
1170 s->regs[GT_PCI1_SSCS10_BAR] = 0x00000000;
1171 s->regs[GT_PCI1_SSCS32_BAR] = 0x01000000;
1172 s->regs[GT_PCI1_SCS3BT_BAR] = 0x1f000000;
1173 s->regs[GT_PCI1_CFGADDR] = 0x00000000;
1174 s->regs[GT_PCI1_CFGDATA] = 0x00000000;
1175 s->regs[GT_PCI0_CFGADDR] = 0x00000000;
1176
1177 /* Interrupt registers are all zeroed at reset */
1178
1179 gt64120_isd_mapping(s);
1180 gt64120_pci_mapping(s);
1181 gt64120_update_pci_cfgdata_mapping(s);
1182 }
1183
1184 static void gt64120_realize(DeviceState *dev, Error **errp)
1185 {
1186 GT64120State *s = GT64120_PCI_HOST_BRIDGE(dev);
1187 PCIHostState *phb = PCI_HOST_BRIDGE(dev);
1188
1189 memory_region_init_io(&s->ISD_mem, OBJECT(dev), &isd_mem_ops, s,
1190 "gt64120-isd", 0x1000);
1191 memory_region_init(&s->pci0_mem, OBJECT(dev), "pci0-mem", 4 * GiB);
1192 address_space_init(&s->pci0_mem_as, &s->pci0_mem, "pci0-mem");
1193 phb->bus = pci_root_bus_new(dev, "pci",
1194 &s->pci0_mem,
1195 get_system_io(),
1196 PCI_DEVFN(18, 0), TYPE_PCI_BUS);
1197
1198 pci_create_simple(phb->bus, PCI_DEVFN(0, 0), "gt64120_pci");
1199 memory_region_init_io(&phb->conf_mem, OBJECT(phb),
1200 &pci_host_conf_le_ops,
1201 s, "pci-conf-idx", 4);
1202 memory_region_add_subregion_overlap(&s->ISD_mem, GT_PCI0_CFGADDR << 2,
1203 &phb->conf_mem, 1);
1204
1205
1206 /*
1207 * The whole address space decoded by the GT-64120A doesn't generate
1208 * exception when accessing invalid memory. Create an empty slot to
1209 * emulate this feature.
1210 */
1211 empty_slot_init("GT64120", 0, 0x20000000);
1212 }
1213
1214 static void gt64120_pci_realize(PCIDevice *d, Error **errp)
1215 {
1216 /* Values from chapter 17.16 "PCI Configuration" */
1217
1218 pci_set_long(d->wmask + PCI_BASE_ADDRESS_0, 0xfffff008); /* SCS[1:0] */
1219 pci_set_long(d->wmask + PCI_BASE_ADDRESS_1, 0xfffff008); /* SCS[3:2] */
1220 pci_set_long(d->wmask + PCI_BASE_ADDRESS_2, 0xfffff008); /* CS[2:0] */
1221 pci_set_long(d->wmask + PCI_BASE_ADDRESS_3, 0xfffff008); /* CS[3], BootCS */
1222 pci_set_long(d->wmask + PCI_BASE_ADDRESS_4, 0xfffff000); /* ISD MMIO */
1223 pci_set_long(d->wmask + PCI_BASE_ADDRESS_5, 0xfffff001); /* ISD I/O */
1224 }
1225
1226 static void gt64120_pci_reset_hold(Object *obj, ResetType type)
1227 {
1228 PCIDevice *d = PCI_DEVICE(obj);
1229
1230 /* Values from chapter 17.16 "PCI Configuration" */
1231
1232 pci_set_word(d->config + PCI_COMMAND, 0);
1233 pci_set_word(d->config + PCI_STATUS,
1234 PCI_STATUS_FAST_BACK | PCI_STATUS_DEVSEL_MEDIUM);
1235 pci_config_set_prog_interface(d->config, 0);
1236
1237 pci_set_long(d->config + PCI_BASE_ADDRESS_0, 0x00000008);
1238 pci_set_long(d->config + PCI_BASE_ADDRESS_1, 0x01000008);
1239 pci_set_long(d->config + PCI_BASE_ADDRESS_2, 0x1c000000);
1240 pci_set_long(d->config + PCI_BASE_ADDRESS_3, 0x1f000000);
1241 pci_set_long(d->config + PCI_BASE_ADDRESS_4, 0x14000000);
1242 pci_set_long(d->config + PCI_BASE_ADDRESS_5, 0x14000001);
1243
1244 pci_set_byte(d->config + 0x3d, 0x01);
1245 }
1246
1247 static void gt64120_pci_class_init(ObjectClass *klass, void *data)
1248 {
1249 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
1250 DeviceClass *dc = DEVICE_CLASS(klass);
1251 ResettableClass *rc = RESETTABLE_CLASS(klass);
1252
1253 rc->phases.hold = gt64120_pci_reset_hold;
1254 k->realize = gt64120_pci_realize;
1255 k->vendor_id = PCI_VENDOR_ID_MARVELL;
1256 k->device_id = PCI_DEVICE_ID_MARVELL_GT6412X;
1257 k->revision = 0x10;
1258 k->class_id = PCI_CLASS_BRIDGE_HOST;
1259 /*
1260 * PCI-facing part of the host bridge, not usable without the
1261 * host-facing part, which can't be device_add'ed, yet.
1262 */
1263 dc->user_creatable = false;
1264 }
1265
1266 static const TypeInfo gt64120_pci_info = {
1267 .name = "gt64120_pci",
1268 .parent = TYPE_PCI_DEVICE,
1269 .instance_size = sizeof(PCIDevice),
1270 .class_init = gt64120_pci_class_init,
1271 .interfaces = (InterfaceInfo[]) {
1272 { INTERFACE_CONVENTIONAL_PCI_DEVICE },
1273 { },
1274 },
1275 };
1276
1277 static Property gt64120_properties[] = {
1278 DEFINE_PROP_BOOL("cpu-little-endian", GT64120State,
1279 cpu_little_endian, false),
1280 DEFINE_PROP_END_OF_LIST(),
1281 };
1282
1283 static void gt64120_class_init(ObjectClass *klass, void *data)
1284 {
1285 DeviceClass *dc = DEVICE_CLASS(klass);
1286
1287 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
1288 device_class_set_props(dc, gt64120_properties);
1289 dc->realize = gt64120_realize;
1290 device_class_set_legacy_reset(dc, gt64120_reset);
1291 dc->vmsd = &vmstate_gt64120;
1292 }
1293
1294 static const TypeInfo gt64120_info = {
1295 .name = TYPE_GT64120_PCI_HOST_BRIDGE,
1296 .parent = TYPE_PCI_HOST_BRIDGE,
1297 .instance_size = sizeof(GT64120State),
1298 .class_init = gt64120_class_init,
1299 };
1300
1301 static void gt64120_pci_register_types(void)
1302 {
1303 type_register_static(&gt64120_info);
1304 type_register_static(&gt64120_pci_info);
1305 }
1306
1307 type_init(gt64120_pci_register_types)
armbru's QEMU hackery