2 * QEMU PowerPC e500-based platforms
4 * Copyright (C) 2009 Freescale Semiconductor, Inc. All rights reserved.
6 * Author: Yu Liu, <yu.liu@freescale.com>
8 * This file is derived from hw/ppc440_bamboo.c,
9 * the copyright for that material belongs to the original owners.
11 * This is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
17 #include "qemu/osdep.h"
18 #include "qemu/datadir.h"
19 #include "qemu/units.h"
20 #include "qemu/guest-random.h"
21 #include "qapi/error.h"
23 #include "e500-ccsr.h"
25 #include "qemu/config-file.h"
26 #include "hw/block/flash.h"
27 #include "hw/char/serial-mm.h"
28 #include "hw/pci/pci.h"
29 #include "sysemu/block-backend-io.h"
30 #include "sysemu/sysemu.h"
31 #include "sysemu/kvm.h"
32 #include "sysemu/reset.h"
33 #include "sysemu/runstate.h"
35 #include "sysemu/device_tree.h"
36 #include "hw/ppc/openpic.h"
37 #include "hw/ppc/openpic_kvm.h"
38 #include "hw/ppc/ppc.h"
39 #include "hw/qdev-properties.h"
40 #include "hw/loader.h"
42 #include "hw/sysbus.h"
43 #include "qemu/host-utils.h"
44 #include "qemu/option.h"
45 #include "hw/pci-host/ppce500.h"
46 #include "qemu/error-report.h"
47 #include "hw/platform-bus.h"
48 #include "hw/net/fsl_etsec/etsec.h"
49 #include "hw/i2c/i2c.h"
51 #include "hw/sd/sdhci.h"
52 #include "hw/misc/unimp.h"
54 #define EPAPR_MAGIC (0x45504150)
55 #define DTC_LOAD_PAD 0x1800000
56 #define DTC_PAD_MASK 0xFFFFF
57 #define DTB_MAX_SIZE (8 * MiB)
58 #define INITRD_LOAD_PAD 0x2000000
59 #define INITRD_PAD_MASK 0xFFFFFF
61 #define RAM_SIZES_ALIGN (64 * MiB)
63 /* TODO: parameterize */
64 #define MPC8544_CCSRBAR_SIZE 0x00100000ULL
65 #define MPC8544_MPIC_REGS_OFFSET 0x40000ULL
66 #define MPC8544_MSI_REGS_OFFSET 0x41600ULL
67 #define MPC8544_SERIAL0_REGS_OFFSET 0x4500ULL
68 #define MPC8544_SERIAL1_REGS_OFFSET 0x4600ULL
69 #define MPC8544_PCI_REGS_OFFSET 0x8000ULL
70 #define MPC8544_PCI_REGS_SIZE 0x1000ULL
71 #define MPC85XX_ESDHC_REGS_OFFSET 0x2e000ULL
72 #define MPC85XX_ESDHC_REGS_SIZE 0x1000ULL
73 #define MPC8544_UTIL_OFFSET 0xe0000ULL
74 #define MPC8XXX_GPIO_OFFSET 0x000FF000ULL
75 #define MPC8544_I2C_REGS_OFFSET 0x3000ULL
76 #define MPC8XXX_GPIO_IRQ 47
77 #define MPC8544_I2C_IRQ 43
78 #define MPC85XX_ESDHC_IRQ 72
79 #define RTC_REGS_OFFSET 0x68
81 #define PLATFORM_CLK_FREQ_HZ (400 * 1000 * 1000)
90 static uint32_t *pci_map_create(void *fdt
, uint32_t mpic
, int first_slot
,
91 int nr_slots
, int *len
)
97 int last_slot
= first_slot
+ nr_slots
;
100 *len
= nr_slots
* 4 * 7 * sizeof(uint32_t);
101 pci_map
= g_malloc(*len
);
103 for (slot
= first_slot
; slot
< last_slot
; slot
++) {
104 for (pci_irq
= 0; pci_irq
< 4; pci_irq
++) {
105 pci_map
[i
++] = cpu_to_be32(slot
<< 11);
106 pci_map
[i
++] = cpu_to_be32(0x0);
107 pci_map
[i
++] = cpu_to_be32(0x0);
108 pci_map
[i
++] = cpu_to_be32(pci_irq
+ 1);
109 pci_map
[i
++] = cpu_to_be32(mpic
);
110 host_irq
= ppce500_pci_map_irq_slot(slot
, pci_irq
);
111 pci_map
[i
++] = cpu_to_be32(host_irq
+ 1);
112 pci_map
[i
++] = cpu_to_be32(0x1);
116 assert((i
* sizeof(uint32_t)) == *len
);
121 static void dt_serial_create(void *fdt
, unsigned long long offset
,
122 const char *soc
, const char *mpic
,
123 const char *alias
, int idx
, bool defcon
)
127 ser
= g_strdup_printf("%s/serial@%llx", soc
, offset
);
128 qemu_fdt_add_subnode(fdt
, ser
);
129 qemu_fdt_setprop_string(fdt
, ser
, "device_type", "serial");
130 qemu_fdt_setprop_string(fdt
, ser
, "compatible", "ns16550");
131 qemu_fdt_setprop_cells(fdt
, ser
, "reg", offset
, 0x100);
132 qemu_fdt_setprop_cell(fdt
, ser
, "cell-index", idx
);
133 qemu_fdt_setprop_cell(fdt
, ser
, "clock-frequency", PLATFORM_CLK_FREQ_HZ
);
134 qemu_fdt_setprop_cells(fdt
, ser
, "interrupts", 42, 2);
135 qemu_fdt_setprop_phandle(fdt
, ser
, "interrupt-parent", mpic
);
136 qemu_fdt_setprop_string(fdt
, "/aliases", alias
, ser
);
140 * "linux,stdout-path" and "stdout" properties are deprecated by linux
141 * kernel. New platforms should only use the "stdout-path" property. Set
142 * the new property and continue using older property to remain
143 * compatible with the existing firmware.
145 qemu_fdt_setprop_string(fdt
, "/chosen", "linux,stdout-path", ser
);
146 qemu_fdt_setprop_string(fdt
, "/chosen", "stdout-path", ser
);
151 static void create_dt_mpc8xxx_gpio(void *fdt
, const char *soc
, const char *mpic
)
153 hwaddr mmio0
= MPC8XXX_GPIO_OFFSET
;
154 int irq0
= MPC8XXX_GPIO_IRQ
;
155 gchar
*node
= g_strdup_printf("%s/gpio@%"PRIx64
, soc
, mmio0
);
156 gchar
*poweroff
= g_strdup_printf("%s/power-off", soc
);
159 qemu_fdt_add_subnode(fdt
, node
);
160 qemu_fdt_setprop_string(fdt
, node
, "compatible", "fsl,qoriq-gpio");
161 qemu_fdt_setprop_cells(fdt
, node
, "reg", mmio0
, 0x1000);
162 qemu_fdt_setprop_cells(fdt
, node
, "interrupts", irq0
, 0x2);
163 qemu_fdt_setprop_phandle(fdt
, node
, "interrupt-parent", mpic
);
164 qemu_fdt_setprop_cells(fdt
, node
, "#gpio-cells", 2);
165 qemu_fdt_setprop(fdt
, node
, "gpio-controller", NULL
, 0);
166 gpio_ph
= qemu_fdt_alloc_phandle(fdt
);
167 qemu_fdt_setprop_cell(fdt
, node
, "phandle", gpio_ph
);
168 qemu_fdt_setprop_cell(fdt
, node
, "linux,phandle", gpio_ph
);
171 qemu_fdt_add_subnode(fdt
, poweroff
);
172 qemu_fdt_setprop_string(fdt
, poweroff
, "compatible", "gpio-poweroff");
173 qemu_fdt_setprop_cells(fdt
, poweroff
, "gpios", gpio_ph
, 0, 0);
179 static void dt_rtc_create(void *fdt
, const char *i2c
, const char *alias
)
181 int offset
= RTC_REGS_OFFSET
;
183 gchar
*rtc
= g_strdup_printf("%s/rtc@%"PRIx32
, i2c
, offset
);
184 qemu_fdt_add_subnode(fdt
, rtc
);
185 qemu_fdt_setprop_string(fdt
, rtc
, "compatible", "pericom,pt7c4338");
186 qemu_fdt_setprop_cells(fdt
, rtc
, "reg", offset
);
187 qemu_fdt_setprop_string(fdt
, "/aliases", alias
, rtc
);
192 static void dt_i2c_create(void *fdt
, const char *soc
, const char *mpic
,
195 hwaddr mmio0
= MPC8544_I2C_REGS_OFFSET
;
196 int irq0
= MPC8544_I2C_IRQ
;
198 gchar
*i2c
= g_strdup_printf("%s/i2c@%"PRIx64
, soc
, mmio0
);
199 qemu_fdt_add_subnode(fdt
, i2c
);
200 qemu_fdt_setprop_string(fdt
, i2c
, "device_type", "i2c");
201 qemu_fdt_setprop_string(fdt
, i2c
, "compatible", "fsl-i2c");
202 qemu_fdt_setprop_cells(fdt
, i2c
, "reg", mmio0
, 0x14);
203 qemu_fdt_setprop_cells(fdt
, i2c
, "cell-index", 0);
204 qemu_fdt_setprop_cells(fdt
, i2c
, "interrupts", irq0
, 0x2);
205 qemu_fdt_setprop_phandle(fdt
, i2c
, "interrupt-parent", mpic
);
206 qemu_fdt_setprop_string(fdt
, "/aliases", alias
, i2c
);
211 static void dt_sdhc_create(void *fdt
, const char *parent
, const char *mpic
)
213 hwaddr mmio
= MPC85XX_ESDHC_REGS_OFFSET
;
214 hwaddr size
= MPC85XX_ESDHC_REGS_SIZE
;
215 int irq
= MPC85XX_ESDHC_IRQ
;
216 g_autofree
char *name
= NULL
;
218 name
= g_strdup_printf("%s/sdhc@%" PRIx64
, parent
, mmio
);
219 qemu_fdt_add_subnode(fdt
, name
);
220 qemu_fdt_setprop(fdt
, name
, "sdhci,auto-cmd12", NULL
, 0);
221 qemu_fdt_setprop_phandle(fdt
, name
, "interrupt-parent", mpic
);
222 qemu_fdt_setprop_cells(fdt
, name
, "bus-width", 4);
223 qemu_fdt_setprop_cells(fdt
, name
, "interrupts", irq
, 0x2);
224 qemu_fdt_setprop_cells(fdt
, name
, "reg", mmio
, size
);
225 qemu_fdt_setprop_string(fdt
, name
, "compatible", "fsl,esdhc");
228 typedef struct PlatformDevtreeData
{
233 PlatformBusDevice
*pbus
;
234 } PlatformDevtreeData
;
236 static int create_devtree_etsec(SysBusDevice
*sbdev
, PlatformDevtreeData
*data
)
238 eTSEC
*etsec
= ETSEC_COMMON(sbdev
);
239 PlatformBusDevice
*pbus
= data
->pbus
;
240 hwaddr mmio0
= platform_bus_get_mmio_addr(pbus
, sbdev
, 0);
241 int irq0
= platform_bus_get_irqn(pbus
, sbdev
, 0);
242 int irq1
= platform_bus_get_irqn(pbus
, sbdev
, 1);
243 int irq2
= platform_bus_get_irqn(pbus
, sbdev
, 2);
244 gchar
*node
= g_strdup_printf("%s/ethernet@%"PRIx64
, data
->node
, mmio0
);
245 gchar
*group
= g_strdup_printf("%s/queue-group", node
);
246 void *fdt
= data
->fdt
;
248 assert((int64_t)mmio0
>= 0);
253 qemu_fdt_add_subnode(fdt
, node
);
254 qemu_fdt_setprop(fdt
, node
, "ranges", NULL
, 0);
255 qemu_fdt_setprop_string(fdt
, node
, "device_type", "network");
256 qemu_fdt_setprop_string(fdt
, node
, "compatible", "fsl,etsec2");
257 qemu_fdt_setprop_string(fdt
, node
, "model", "eTSEC");
258 qemu_fdt_setprop(fdt
, node
, "local-mac-address", etsec
->conf
.macaddr
.a
, 6);
259 qemu_fdt_setprop_cells(fdt
, node
, "fixed-link", 0, 1, 1000, 0, 0);
260 qemu_fdt_setprop_cells(fdt
, node
, "#size-cells", 1);
261 qemu_fdt_setprop_cells(fdt
, node
, "#address-cells", 1);
263 qemu_fdt_add_subnode(fdt
, group
);
264 qemu_fdt_setprop_cells(fdt
, group
, "reg", mmio0
, 0x1000);
265 qemu_fdt_setprop_cells(fdt
, group
, "interrupts",
266 data
->irq_start
+ irq0
, 0x2,
267 data
->irq_start
+ irq1
, 0x2,
268 data
->irq_start
+ irq2
, 0x2);
276 static void sysbus_device_create_devtree(SysBusDevice
*sbdev
, void *opaque
)
278 PlatformDevtreeData
*data
= opaque
;
279 bool matched
= false;
281 if (object_dynamic_cast(OBJECT(sbdev
), TYPE_ETSEC_COMMON
)) {
282 create_devtree_etsec(sbdev
, data
);
287 error_report("Device %s is not supported by this machine yet.",
288 qdev_fw_name(DEVICE(sbdev
)));
293 static void create_devtree_flash(SysBusDevice
*sbdev
,
294 PlatformDevtreeData
*data
)
296 g_autofree
char *name
= NULL
;
297 uint64_t num_blocks
= object_property_get_uint(OBJECT(sbdev
),
300 uint64_t sector_length
= object_property_get_uint(OBJECT(sbdev
),
303 uint64_t bank_width
= object_property_get_uint(OBJECT(sbdev
),
306 hwaddr flashbase
= 0;
307 hwaddr flashsize
= num_blocks
* sector_length
;
308 void *fdt
= data
->fdt
;
310 name
= g_strdup_printf("%s/nor@%" PRIx64
, data
->node
, flashbase
);
311 qemu_fdt_add_subnode(fdt
, name
);
312 qemu_fdt_setprop_string(fdt
, name
, "compatible", "cfi-flash");
313 qemu_fdt_setprop_sized_cells(fdt
, name
, "reg",
314 1, flashbase
, 1, flashsize
);
315 qemu_fdt_setprop_cell(fdt
, name
, "bank-width", bank_width
);
318 static void platform_bus_create_devtree(PPCE500MachineState
*pms
,
319 void *fdt
, const char *mpic
)
321 const PPCE500MachineClass
*pmc
= PPCE500_MACHINE_GET_CLASS(pms
);
322 gchar
*node
= g_strdup_printf("/platform@%"PRIx64
, pmc
->platform_bus_base
);
323 const char platcomp
[] = "qemu,platform\0simple-bus";
324 uint64_t addr
= pmc
->platform_bus_base
;
325 uint64_t size
= pmc
->platform_bus_size
;
326 int irq_start
= pmc
->platform_bus_first_irq
;
330 /* Create a /platform node that we can put all devices into */
332 qemu_fdt_add_subnode(fdt
, node
);
333 qemu_fdt_setprop(fdt
, node
, "compatible", platcomp
, sizeof(platcomp
));
335 /* Our platform bus region is less than 32bit big, so 1 cell is enough for
337 qemu_fdt_setprop_cells(fdt
, node
, "#size-cells", 1);
338 qemu_fdt_setprop_cells(fdt
, node
, "#address-cells", 1);
339 qemu_fdt_setprop_cells(fdt
, node
, "ranges", 0, addr
>> 32, addr
, size
);
341 qemu_fdt_setprop_phandle(fdt
, node
, "interrupt-parent", mpic
);
343 /* Create dt nodes for dynamic devices */
344 PlatformDevtreeData data
= {
347 .irq_start
= irq_start
,
349 .pbus
= pms
->pbus_dev
,
352 /* Loop through all dynamic sysbus devices and create nodes for them */
353 foreach_dynamic_sysbus_device(sysbus_device_create_devtree
, &data
);
355 sbdev
= SYS_BUS_DEVICE(object_resolve_path_type("", TYPE_PFLASH_CFI01
,
359 create_devtree_flash(sbdev
, &data
);
365 static int ppce500_load_device_tree(PPCE500MachineState
*pms
,
373 MachineState
*machine
= MACHINE(pms
);
374 unsigned int smp_cpus
= machine
->smp
.cpus
;
375 const PPCE500MachineClass
*pmc
= PPCE500_MACHINE_GET_CLASS(pms
);
376 CPUPPCState
*env
= cpu_env(first_cpu
);
378 uint64_t mem_reg_property
[] = { 0, cpu_to_be64(machine
->ram_size
) };
381 uint8_t hypercall
[16];
382 uint32_t clock_freq
= PLATFORM_CLK_FREQ_HZ
;
383 uint32_t tb_freq
= PLATFORM_CLK_FREQ_HZ
;
385 char compatible_sb
[] = "fsl,mpc8544-immr\0simple-bus";
393 uint32_t *pci_map
= NULL
;
395 uint32_t pci_ranges
[14] =
397 0x2000000, 0x0, pmc
->pci_mmio_bus_base
,
398 pmc
->pci_mmio_base
>> 32, pmc
->pci_mmio_base
,
402 pmc
->pci_pio_base
>> 32, pmc
->pci_pio_base
,
405 const char *dtb_file
= machine
->dtb
;
406 const char *toplevel_compat
= machine
->dt_compatible
;
407 uint8_t rng_seed
[32];
411 filename
= qemu_find_file(QEMU_FILE_TYPE_BIOS
, dtb_file
);
416 fdt
= load_device_tree(filename
, &fdt_size
);
424 fdt
= create_device_tree(&fdt_size
);
429 /* Manipulate device tree in memory. */
430 qemu_fdt_setprop_cell(fdt
, "/", "#address-cells", 2);
431 qemu_fdt_setprop_cell(fdt
, "/", "#size-cells", 2);
433 qemu_fdt_add_subnode(fdt
, "/memory");
434 qemu_fdt_setprop_string(fdt
, "/memory", "device_type", "memory");
435 qemu_fdt_setprop(fdt
, "/memory", "reg", mem_reg_property
,
436 sizeof(mem_reg_property
));
438 qemu_fdt_add_subnode(fdt
, "/chosen");
440 ret
= qemu_fdt_setprop_cell(fdt
, "/chosen", "linux,initrd-start",
443 fprintf(stderr
, "couldn't set /chosen/linux,initrd-start\n");
446 ret
= qemu_fdt_setprop_cell(fdt
, "/chosen", "linux,initrd-end",
447 (initrd_base
+ initrd_size
));
449 fprintf(stderr
, "couldn't set /chosen/linux,initrd-end\n");
454 if (kernel_base
!= -1ULL) {
455 qemu_fdt_setprop_cells(fdt
, "/chosen", "qemu,boot-kernel",
456 kernel_base
>> 32, kernel_base
,
457 kernel_size
>> 32, kernel_size
);
460 ret
= qemu_fdt_setprop_string(fdt
, "/chosen", "bootargs",
461 machine
->kernel_cmdline
);
463 fprintf(stderr
, "couldn't set /chosen/bootargs\n");
465 qemu_guest_getrandom_nofail(rng_seed
, sizeof(rng_seed
));
466 qemu_fdt_setprop(fdt
, "/chosen", "rng-seed", rng_seed
, sizeof(rng_seed
));
469 /* Read out host's frequencies */
470 clock_freq
= kvmppc_get_clockfreq();
471 tb_freq
= kvmppc_get_tbfreq();
473 /* indicate KVM hypercall interface */
474 qemu_fdt_add_subnode(fdt
, "/hypervisor");
475 qemu_fdt_setprop_string(fdt
, "/hypervisor", "compatible",
477 kvmppc_get_hypercall(env
, hypercall
, sizeof(hypercall
));
478 qemu_fdt_setprop(fdt
, "/hypervisor", "hcall-instructions",
479 hypercall
, sizeof(hypercall
));
480 /* if KVM supports the idle hcall, set property indicating this */
481 if (kvmppc_get_hasidle(env
)) {
482 qemu_fdt_setprop(fdt
, "/hypervisor", "has-idle", NULL
, 0);
486 /* Create CPU nodes */
487 qemu_fdt_add_subnode(fdt
, "/cpus");
488 qemu_fdt_setprop_cell(fdt
, "/cpus", "#address-cells", 1);
489 qemu_fdt_setprop_cell(fdt
, "/cpus", "#size-cells", 0);
491 /* We need to generate the cpu nodes in reverse order, so Linux can pick
492 the first node as boot node and be happy */
493 for (i
= smp_cpus
- 1; i
>= 0; i
--) {
496 uint64_t cpu_release_addr
= pmc
->spin_base
+ (i
* 0x20);
498 cpu
= qemu_get_cpu(i
);
504 cpu_name
= g_strdup_printf("/cpus/PowerPC,8544@%x", i
);
505 qemu_fdt_add_subnode(fdt
, cpu_name
);
506 qemu_fdt_setprop_cell(fdt
, cpu_name
, "clock-frequency", clock_freq
);
507 qemu_fdt_setprop_cell(fdt
, cpu_name
, "timebase-frequency", tb_freq
);
508 qemu_fdt_setprop_string(fdt
, cpu_name
, "device_type", "cpu");
509 qemu_fdt_setprop_cell(fdt
, cpu_name
, "reg", i
);
510 qemu_fdt_setprop_cell(fdt
, cpu_name
, "d-cache-line-size",
511 env
->dcache_line_size
);
512 qemu_fdt_setprop_cell(fdt
, cpu_name
, "i-cache-line-size",
513 env
->icache_line_size
);
514 qemu_fdt_setprop_cell(fdt
, cpu_name
, "d-cache-size", 0x8000);
515 qemu_fdt_setprop_cell(fdt
, cpu_name
, "i-cache-size", 0x8000);
516 qemu_fdt_setprop_cell(fdt
, cpu_name
, "bus-frequency", 0);
517 if (cpu
->cpu_index
) {
518 qemu_fdt_setprop_string(fdt
, cpu_name
, "status", "disabled");
519 qemu_fdt_setprop_string(fdt
, cpu_name
, "enable-method",
521 qemu_fdt_setprop_u64(fdt
, cpu_name
, "cpu-release-addr",
524 qemu_fdt_setprop_string(fdt
, cpu_name
, "status", "okay");
529 qemu_fdt_add_subnode(fdt
, "/aliases");
530 /* XXX These should go into their respective devices' code */
531 soc
= g_strdup_printf("/soc@%"PRIx64
, pmc
->ccsrbar_base
);
532 qemu_fdt_add_subnode(fdt
, soc
);
533 qemu_fdt_setprop_string(fdt
, soc
, "device_type", "soc");
534 qemu_fdt_setprop(fdt
, soc
, "compatible", compatible_sb
,
535 sizeof(compatible_sb
));
536 qemu_fdt_setprop_cell(fdt
, soc
, "#address-cells", 1);
537 qemu_fdt_setprop_cell(fdt
, soc
, "#size-cells", 1);
538 qemu_fdt_setprop_cells(fdt
, soc
, "ranges", 0x0,
539 pmc
->ccsrbar_base
>> 32, pmc
->ccsrbar_base
,
540 MPC8544_CCSRBAR_SIZE
);
541 /* XXX should contain a reasonable value */
542 qemu_fdt_setprop_cell(fdt
, soc
, "bus-frequency", 0);
544 mpic
= g_strdup_printf("%s/pic@%llx", soc
, MPC8544_MPIC_REGS_OFFSET
);
545 qemu_fdt_add_subnode(fdt
, mpic
);
546 qemu_fdt_setprop_string(fdt
, mpic
, "device_type", "open-pic");
547 qemu_fdt_setprop_string(fdt
, mpic
, "compatible", "fsl,mpic");
548 qemu_fdt_setprop_cells(fdt
, mpic
, "reg", MPC8544_MPIC_REGS_OFFSET
,
550 qemu_fdt_setprop_cell(fdt
, mpic
, "#address-cells", 0);
551 qemu_fdt_setprop_cell(fdt
, mpic
, "#interrupt-cells", 2);
552 mpic_ph
= qemu_fdt_alloc_phandle(fdt
);
553 qemu_fdt_setprop_cell(fdt
, mpic
, "phandle", mpic_ph
);
554 qemu_fdt_setprop_cell(fdt
, mpic
, "linux,phandle", mpic_ph
);
555 qemu_fdt_setprop(fdt
, mpic
, "interrupt-controller", NULL
, 0);
558 * We have to generate ser1 first, because Linux takes the first
559 * device it finds in the dt as serial output device. And we generate
560 * devices in reverse order to the dt.
563 dt_serial_create(fdt
, MPC8544_SERIAL1_REGS_OFFSET
,
564 soc
, mpic
, "serial1", 1, false);
568 dt_serial_create(fdt
, MPC8544_SERIAL0_REGS_OFFSET
,
569 soc
, mpic
, "serial0", 0, true);
573 dt_i2c_create(fdt
, soc
, mpic
, "i2c");
575 dt_rtc_create(fdt
, "i2c", "rtc");
578 if (pmc
->has_esdhc
) {
579 dt_sdhc_create(fdt
, soc
, mpic
);
582 gutil
= g_strdup_printf("%s/global-utilities@%llx", soc
,
583 MPC8544_UTIL_OFFSET
);
584 qemu_fdt_add_subnode(fdt
, gutil
);
585 qemu_fdt_setprop_string(fdt
, gutil
, "compatible", "fsl,mpc8544-guts");
586 qemu_fdt_setprop_cells(fdt
, gutil
, "reg", MPC8544_UTIL_OFFSET
, 0x1000);
587 qemu_fdt_setprop(fdt
, gutil
, "fsl,has-rstcr", NULL
, 0);
590 msi
= g_strdup_printf("/%s/msi@%llx", soc
, MPC8544_MSI_REGS_OFFSET
);
591 qemu_fdt_add_subnode(fdt
, msi
);
592 qemu_fdt_setprop_string(fdt
, msi
, "compatible", "fsl,mpic-msi");
593 qemu_fdt_setprop_cells(fdt
, msi
, "reg", MPC8544_MSI_REGS_OFFSET
, 0x200);
594 msi_ph
= qemu_fdt_alloc_phandle(fdt
);
595 qemu_fdt_setprop_cells(fdt
, msi
, "msi-available-ranges", 0x0, 0x100);
596 qemu_fdt_setprop_phandle(fdt
, msi
, "interrupt-parent", mpic
);
597 qemu_fdt_setprop_cells(fdt
, msi
, "interrupts",
606 qemu_fdt_setprop_cell(fdt
, msi
, "phandle", msi_ph
);
607 qemu_fdt_setprop_cell(fdt
, msi
, "linux,phandle", msi_ph
);
610 pci
= g_strdup_printf("/pci@%llx",
611 pmc
->ccsrbar_base
+ MPC8544_PCI_REGS_OFFSET
);
612 qemu_fdt_add_subnode(fdt
, pci
);
613 qemu_fdt_setprop_cell(fdt
, pci
, "cell-index", 0);
614 qemu_fdt_setprop_string(fdt
, pci
, "compatible", "fsl,mpc8540-pci");
615 qemu_fdt_setprop_string(fdt
, pci
, "device_type", "pci");
616 qemu_fdt_setprop_cells(fdt
, pci
, "interrupt-map-mask", 0xf800, 0x0,
618 pci_map
= pci_map_create(fdt
, qemu_fdt_get_phandle(fdt
, mpic
),
619 pmc
->pci_first_slot
, pmc
->pci_nr_slots
,
621 qemu_fdt_setprop(fdt
, pci
, "interrupt-map", pci_map
, len
);
622 qemu_fdt_setprop_phandle(fdt
, pci
, "interrupt-parent", mpic
);
623 qemu_fdt_setprop_cells(fdt
, pci
, "interrupts", 24, 2);
624 qemu_fdt_setprop_cells(fdt
, pci
, "bus-range", 0, 255);
625 for (i
= 0; i
< 14; i
++) {
626 pci_ranges
[i
] = cpu_to_be32(pci_ranges
[i
]);
628 qemu_fdt_setprop_cell(fdt
, pci
, "fsl,msi", msi_ph
);
629 qemu_fdt_setprop(fdt
, pci
, "ranges", pci_ranges
, sizeof(pci_ranges
));
630 qemu_fdt_setprop_cells(fdt
, pci
, "reg",
631 (pmc
->ccsrbar_base
+ MPC8544_PCI_REGS_OFFSET
) >> 32,
632 (pmc
->ccsrbar_base
+ MPC8544_PCI_REGS_OFFSET
),
634 qemu_fdt_setprop_cell(fdt
, pci
, "clock-frequency", 66666666);
635 qemu_fdt_setprop_cell(fdt
, pci
, "#interrupt-cells", 1);
636 qemu_fdt_setprop_cell(fdt
, pci
, "#size-cells", 2);
637 qemu_fdt_setprop_cell(fdt
, pci
, "#address-cells", 3);
638 qemu_fdt_setprop_string(fdt
, "/aliases", "pci0", pci
);
641 if (pmc
->has_mpc8xxx_gpio
) {
642 create_dt_mpc8xxx_gpio(fdt
, soc
, mpic
);
646 platform_bus_create_devtree(pms
, fdt
, mpic
);
650 pmc
->fixup_devtree(fdt
);
652 if (toplevel_compat
) {
653 qemu_fdt_setprop(fdt
, "/", "compatible", toplevel_compat
,
654 strlen(toplevel_compat
) + 1);
659 qemu_fdt_dumpdtb(fdt
, fdt_size
);
660 cpu_physical_memory_write(addr
, fdt
, fdt_size
);
662 /* Set machine->fdt for 'dumpdtb' QMP/HMP command */
663 g_free(machine
->fdt
);
676 typedef struct DeviceTreeParams
{
677 PPCE500MachineState
*machine
;
686 static void ppce500_reset_device_tree(void *opaque
)
688 DeviceTreeParams
*p
= opaque
;
689 ppce500_load_device_tree(p
->machine
, p
->addr
, p
->initrd_base
,
690 p
->initrd_size
, p
->kernel_base
, p
->kernel_size
,
694 static void ppce500_init_notify(Notifier
*notifier
, void *data
)
696 DeviceTreeParams
*p
= container_of(notifier
, DeviceTreeParams
, notifier
);
697 ppce500_reset_device_tree(p
);
700 static int ppce500_prep_device_tree(PPCE500MachineState
*machine
,
707 DeviceTreeParams
*p
= g_new(DeviceTreeParams
, 1);
708 p
->machine
= machine
;
710 p
->initrd_base
= initrd_base
;
711 p
->initrd_size
= initrd_size
;
712 p
->kernel_base
= kernel_base
;
713 p
->kernel_size
= kernel_size
;
715 qemu_register_reset_nosnapshotload(ppce500_reset_device_tree
, p
);
716 p
->notifier
.notify
= ppce500_init_notify
;
717 qemu_add_machine_init_done_notifier(&p
->notifier
);
719 /* Issue the device tree loader once, so that we get the size of the blob */
720 return ppce500_load_device_tree(machine
, addr
, initrd_base
, initrd_size
,
721 kernel_base
, kernel_size
, true);
724 hwaddr
booke206_page_size_to_tlb(uint64_t size
)
726 return 63 - clz64(size
/ KiB
);
729 static int booke206_initial_map_tsize(CPUPPCState
*env
)
731 struct boot_info
*bi
= env
->load_info
;
735 /* Our initial TLB entry needs to cover everything from 0 to
736 the device tree top */
737 dt_end
= bi
->dt_base
+ bi
->dt_size
;
738 ps
= booke206_page_size_to_tlb(dt_end
) + 1;
740 /* e500v2 can only do even TLB size bits */
746 static uint64_t mmubooke_initial_mapsize(CPUPPCState
*env
)
750 tsize
= booke206_initial_map_tsize(env
);
751 return (1ULL << 10 << tsize
);
754 /* Create -kernel TLB entries for BookE. */
755 static void mmubooke_create_initial_mapping(CPUPPCState
*env
)
757 ppcmas_tlb_t
*tlb
= booke206_get_tlbm(env
, 1, 0, 0);
761 ps
= booke206_initial_map_tsize(env
);
762 size
= (ps
<< MAS1_TSIZE_SHIFT
);
763 tlb
->mas1
= MAS1_VALID
| size
;
766 tlb
->mas7_3
|= MAS3_UR
| MAS3_UW
| MAS3_UX
| MAS3_SR
| MAS3_SW
| MAS3_SX
;
769 env
->tlb_dirty
= true;
773 static void ppce500_cpu_reset_sec(void *opaque
)
775 PowerPCCPU
*cpu
= opaque
;
776 CPUState
*cs
= CPU(cpu
);
780 cs
->exception_index
= EXCP_HLT
;
783 static void ppce500_cpu_reset(void *opaque
)
785 PowerPCCPU
*cpu
= opaque
;
786 CPUState
*cs
= CPU(cpu
);
787 CPUPPCState
*env
= &cpu
->env
;
788 struct boot_info
*bi
= env
->load_info
;
792 /* Set initial guest state. */
794 env
->gpr
[1] = (16 * MiB
) - 8;
795 env
->gpr
[3] = bi
->dt_base
;
798 env
->gpr
[6] = EPAPR_MAGIC
;
799 env
->gpr
[7] = mmubooke_initial_mapsize(env
);
802 env
->nip
= bi
->entry
;
803 mmubooke_create_initial_mapping(env
);
806 static DeviceState
*ppce500_init_mpic_qemu(PPCE500MachineState
*pms
,
812 MachineState
*machine
= MACHINE(pms
);
813 unsigned int smp_cpus
= machine
->smp
.cpus
;
814 const PPCE500MachineClass
*pmc
= PPCE500_MACHINE_GET_CLASS(pms
);
816 dev
= qdev_new(TYPE_OPENPIC
);
817 object_property_add_child(OBJECT(machine
), "pic", OBJECT(dev
));
818 qdev_prop_set_uint32(dev
, "model", pmc
->mpic_version
);
819 qdev_prop_set_uint32(dev
, "nb_cpus", smp_cpus
);
821 s
= SYS_BUS_DEVICE(dev
);
822 sysbus_realize_and_unref(s
, &error_fatal
);
825 for (i
= 0; i
< smp_cpus
; i
++) {
826 for (j
= 0; j
< OPENPIC_OUTPUT_NB
; j
++) {
827 sysbus_connect_irq(s
, k
++, irqs
[i
].irq
[j
]);
834 static DeviceState
*ppce500_init_mpic_kvm(const PPCE500MachineClass
*pmc
,
835 IrqLines
*irqs
, Error
**errp
)
841 dev
= qdev_new(TYPE_KVM_OPENPIC
);
842 qdev_prop_set_uint32(dev
, "model", pmc
->mpic_version
);
844 if (!sysbus_realize_and_unref(SYS_BUS_DEVICE(dev
), errp
)) {
845 object_unparent(OBJECT(dev
));
850 if (kvm_openpic_connect_vcpu(dev
, cs
)) {
851 fprintf(stderr
, "%s: failed to connect vcpu to irqchip\n",
859 g_assert_not_reached();
863 static DeviceState
*ppce500_init_mpic(PPCE500MachineState
*pms
,
867 const PPCE500MachineClass
*pmc
= PPCE500_MACHINE_GET_CLASS(pms
);
868 DeviceState
*dev
= NULL
;
874 if (kvm_kernel_irqchip_allowed()) {
875 dev
= ppce500_init_mpic_kvm(pmc
, irqs
, &err
);
877 if (kvm_kernel_irqchip_required() && !dev
) {
878 error_reportf_err(err
,
879 "kernel_irqchip requested but unavailable: ");
885 dev
= ppce500_init_mpic_qemu(pms
, irqs
);
888 s
= SYS_BUS_DEVICE(dev
);
889 memory_region_add_subregion(ccsr
, MPC8544_MPIC_REGS_OFFSET
,
895 static void ppce500_power_off(void *opaque
, int line
, int on
)
898 qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN
);
902 void ppce500_init(MachineState
*machine
)
904 MemoryRegion
*address_space_mem
= get_system_memory();
905 PPCE500MachineState
*pms
= PPCE500_MACHINE(machine
);
906 const PPCE500MachineClass
*pmc
= PPCE500_MACHINE_GET_CLASS(machine
);
907 MachineClass
*mc
= MACHINE_CLASS(pmc
);
909 CPUPPCState
*env
= NULL
;
911 hwaddr kernel_base
= -1LL;
914 hwaddr initrd_base
= 0;
918 const char *payload_name
;
919 bool kernel_as_payload
;
920 hwaddr bios_entry
= 0;
921 target_long payload_size
;
922 struct boot_info
*boot_info
= NULL
;
925 unsigned int smp_cpus
= machine
->smp
.cpus
;
926 /* irq num for pin INTA, INTB, INTC and INTD is 1, 2, 3 and
928 unsigned int pci_irq_nrs
[PCI_NUM_PINS
] = {1, 2, 3, 4};
930 DeviceState
*dev
, *mpicdev
;
932 CPUPPCState
*firstenv
= NULL
;
933 MemoryRegion
*ccsr_addr_space
;
935 PPCE500CCSRState
*ccsr
;
938 irqs
= g_new0(IrqLines
, smp_cpus
);
939 for (i
= 0; i
< smp_cpus
; i
++) {
943 cpu
= POWERPC_CPU(object_new(machine
->cpu_type
));
947 if (env
->mmu_model
!= POWERPC_MMU_BOOKE206
) {
948 error_report("MMU model %i not supported by this machine",
954 * Secondary CPU starts in halted state for now. Needs to change
955 * when implementing non-kernel boot.
957 object_property_set_bool(OBJECT(cs
), "start-powered-off", i
!= 0,
959 qdev_realize_and_unref(DEVICE(cs
), NULL
, &error_fatal
);
965 irqs
[i
].irq
[OPENPIC_OUTPUT_INT
] =
966 qdev_get_gpio_in(DEVICE(cpu
), PPCE500_INPUT_INT
);
967 irqs
[i
].irq
[OPENPIC_OUTPUT_CINT
] =
968 qdev_get_gpio_in(DEVICE(cpu
), PPCE500_INPUT_CINT
);
969 env
->spr_cb
[SPR_BOOKE_PIR
].default_value
= cs
->cpu_index
= i
;
970 env
->mpic_iack
= pmc
->ccsrbar_base
+ MPC8544_MPIC_REGS_OFFSET
+ 0xa0;
972 ppc_booke_timers_init(cpu
, PLATFORM_CLK_FREQ_HZ
, PPC_TIMER_E500
);
974 /* Register reset handler */
977 boot_info
= g_new0(struct boot_info
, 1);
978 qemu_register_reset(ppce500_cpu_reset
, cpu
);
979 env
->load_info
= boot_info
;
982 qemu_register_reset(ppce500_cpu_reset_sec
, cpu
);
988 if (!QEMU_IS_ALIGNED(machine
->ram_size
, RAM_SIZES_ALIGN
)) {
989 error_report("RAM size must be multiple of %" PRIu64
, RAM_SIZES_ALIGN
);
993 /* Register Memory */
994 memory_region_add_subregion(address_space_mem
, 0, machine
->ram
);
996 dev
= qdev_new("e500-ccsr");
997 object_property_add_child(OBJECT(machine
), "e500-ccsr", OBJECT(dev
));
998 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev
), &error_fatal
);
1000 ccsr_addr_space
= &ccsr
->ccsr_space
;
1001 memory_region_add_subregion(address_space_mem
, pmc
->ccsrbar_base
,
1004 mpicdev
= ppce500_init_mpic(pms
, ccsr_addr_space
, irqs
);
1009 serial_mm_init(ccsr_addr_space
, MPC8544_SERIAL0_REGS_OFFSET
,
1010 0, qdev_get_gpio_in(mpicdev
, 42), 399193,
1011 serial_hd(0), DEVICE_BIG_ENDIAN
);
1015 serial_mm_init(ccsr_addr_space
, MPC8544_SERIAL1_REGS_OFFSET
,
1016 0, qdev_get_gpio_in(mpicdev
, 42), 399193,
1017 serial_hd(1), DEVICE_BIG_ENDIAN
);
1021 dev
= qdev_new("mpc-i2c");
1022 s
= SYS_BUS_DEVICE(dev
);
1023 sysbus_realize_and_unref(s
, &error_fatal
);
1024 sysbus_connect_irq(s
, 0, qdev_get_gpio_in(mpicdev
, MPC8544_I2C_IRQ
));
1025 memory_region_add_subregion(ccsr_addr_space
, MPC8544_I2C_REGS_OFFSET
,
1026 sysbus_mmio_get_region(s
, 0));
1027 i2c
= (I2CBus
*)qdev_get_child_bus(dev
, "i2c");
1028 i2c_slave_create_simple(i2c
, "ds1338", RTC_REGS_OFFSET
);
1031 if (pmc
->has_esdhc
) {
1032 dev
= qdev_new(TYPE_UNIMPLEMENTED_DEVICE
);
1033 qdev_prop_set_string(dev
, "name", "esdhc");
1034 qdev_prop_set_uint64(dev
, "size", MPC85XX_ESDHC_REGS_SIZE
);
1035 s
= SYS_BUS_DEVICE(dev
);
1036 sysbus_realize_and_unref(s
, &error_fatal
);
1037 memory_region_add_subregion(ccsr_addr_space
, MPC85XX_ESDHC_REGS_OFFSET
,
1038 sysbus_mmio_get_region(s
, 0));
1042 * - SD Host Controller Specification Version 2.0 Part A2
1043 * (See MPC8569E Reference Manual)
1045 dev
= qdev_new(TYPE_SYSBUS_SDHCI
);
1046 qdev_prop_set_uint8(dev
, "sd-spec-version", 2);
1047 qdev_prop_set_uint8(dev
, "endianness", DEVICE_BIG_ENDIAN
);
1048 s
= SYS_BUS_DEVICE(dev
);
1049 sysbus_realize_and_unref(s
, &error_fatal
);
1050 sysbus_connect_irq(s
, 0, qdev_get_gpio_in(mpicdev
, MPC85XX_ESDHC_IRQ
));
1051 memory_region_add_subregion(ccsr_addr_space
, MPC85XX_ESDHC_REGS_OFFSET
,
1052 sysbus_mmio_get_region(s
, 0));
1055 /* General Utility device */
1056 dev
= qdev_new("mpc8544-guts");
1057 s
= SYS_BUS_DEVICE(dev
);
1058 sysbus_realize_and_unref(s
, &error_fatal
);
1059 memory_region_add_subregion(ccsr_addr_space
, MPC8544_UTIL_OFFSET
,
1060 sysbus_mmio_get_region(s
, 0));
1063 dev
= qdev_new("e500-pcihost");
1064 object_property_add_child(OBJECT(machine
), "pci-host", OBJECT(dev
));
1065 qdev_prop_set_uint32(dev
, "first_slot", pmc
->pci_first_slot
);
1066 qdev_prop_set_uint32(dev
, "first_pin_irq", pci_irq_nrs
[0]);
1067 s
= SYS_BUS_DEVICE(dev
);
1068 sysbus_realize_and_unref(s
, &error_fatal
);
1069 for (i
= 0; i
< PCI_NUM_PINS
; i
++) {
1070 sysbus_connect_irq(s
, i
, qdev_get_gpio_in(mpicdev
, pci_irq_nrs
[i
]));
1073 memory_region_add_subregion(ccsr_addr_space
, MPC8544_PCI_REGS_OFFSET
,
1074 sysbus_mmio_get_region(s
, 0));
1076 pci_bus
= (PCIBus
*)qdev_get_child_bus(dev
, "pci.0");
1078 printf("couldn't create PCI controller!\n");
1081 /* Register network interfaces. */
1082 pci_init_nic_devices(pci_bus
, mc
->default_nic
);
1085 /* Register spinning region */
1086 sysbus_create_simple("e500-spin", pmc
->spin_base
, NULL
);
1088 if (pmc
->has_mpc8xxx_gpio
) {
1089 qemu_irq poweroff_irq
;
1091 dev
= qdev_new("mpc8xxx_gpio");
1092 s
= SYS_BUS_DEVICE(dev
);
1093 sysbus_realize_and_unref(s
, &error_fatal
);
1094 sysbus_connect_irq(s
, 0, qdev_get_gpio_in(mpicdev
, MPC8XXX_GPIO_IRQ
));
1095 memory_region_add_subregion(ccsr_addr_space
, MPC8XXX_GPIO_OFFSET
,
1096 sysbus_mmio_get_region(s
, 0));
1098 /* Power Off GPIO at Pin 0 */
1099 poweroff_irq
= qemu_allocate_irq(ppce500_power_off
, NULL
, 0);
1100 qdev_connect_gpio_out(dev
, 0, poweroff_irq
);
1103 /* Platform Bus Device */
1104 dev
= qdev_new(TYPE_PLATFORM_BUS_DEVICE
);
1105 dev
->id
= g_strdup(TYPE_PLATFORM_BUS_DEVICE
);
1106 qdev_prop_set_uint32(dev
, "num_irqs", pmc
->platform_bus_num_irqs
);
1107 qdev_prop_set_uint32(dev
, "mmio_size", pmc
->platform_bus_size
);
1108 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev
), &error_fatal
);
1109 pms
->pbus_dev
= PLATFORM_BUS_DEVICE(dev
);
1111 s
= SYS_BUS_DEVICE(pms
->pbus_dev
);
1112 for (i
= 0; i
< pmc
->platform_bus_num_irqs
; i
++) {
1113 int irqn
= pmc
->platform_bus_first_irq
+ i
;
1114 sysbus_connect_irq(s
, i
, qdev_get_gpio_in(mpicdev
, irqn
));
1117 memory_region_add_subregion(address_space_mem
,
1118 pmc
->platform_bus_base
,
1119 &pms
->pbus_dev
->mmio
);
1121 dinfo
= drive_get(IF_PFLASH
, 0, 0);
1123 BlockBackend
*blk
= blk_by_legacy_dinfo(dinfo
);
1124 BlockDriverState
*bs
= blk_bs(blk
);
1125 uint64_t mmio_size
= memory_region_size(&pms
->pbus_dev
->mmio
);
1126 uint64_t size
= bdrv_getlength(bs
);
1127 uint32_t sector_len
= 64 * KiB
;
1129 if (!is_power_of_2(size
)) {
1130 error_report("Size of pflash file must be a power of two.");
1134 if (size
> mmio_size
) {
1135 error_report("Size of pflash file must not be bigger than %" PRIu64
1136 " bytes.", mmio_size
);
1140 if (!QEMU_IS_ALIGNED(size
, sector_len
)) {
1141 error_report("Size of pflash file must be a multiple of %" PRIu32
1146 dev
= qdev_new(TYPE_PFLASH_CFI01
);
1147 qdev_prop_set_drive(dev
, "drive", blk
);
1148 qdev_prop_set_uint32(dev
, "num-blocks", size
/ sector_len
);
1149 qdev_prop_set_uint64(dev
, "sector-length", sector_len
);
1150 qdev_prop_set_uint8(dev
, "width", 2);
1151 qdev_prop_set_bit(dev
, "big-endian", true);
1152 qdev_prop_set_uint16(dev
, "id0", 0x89);
1153 qdev_prop_set_uint16(dev
, "id1", 0x18);
1154 qdev_prop_set_uint16(dev
, "id2", 0x0000);
1155 qdev_prop_set_uint16(dev
, "id3", 0x0);
1156 qdev_prop_set_string(dev
, "name", "e500.flash");
1157 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev
), &error_fatal
);
1159 memory_region_add_subregion(&pms
->pbus_dev
->mmio
, 0,
1160 pflash_cfi01_get_memory(PFLASH_CFI01(dev
)));
1164 * Smart firmware defaults ahead!
1166 * We follow the following table to select which payload we execute.
1168 * -kernel | -bios | payload
1169 * ---------+-------+---------
1175 * This ensures backwards compatibility with how we used to expose
1176 * -kernel to users but allows them to run through u-boot as well.
1178 kernel_as_payload
= false;
1179 if (machine
->firmware
== NULL
) {
1180 if (machine
->kernel_filename
) {
1181 payload_name
= machine
->kernel_filename
;
1182 kernel_as_payload
= true;
1184 payload_name
= "u-boot.e500";
1187 payload_name
= machine
->firmware
;
1190 filename
= qemu_find_file(QEMU_FILE_TYPE_BIOS
, payload_name
);
1192 error_report("could not find firmware/kernel file '%s'", payload_name
);
1196 payload_size
= load_elf(filename
, NULL
, NULL
, NULL
,
1197 &bios_entry
, &loadaddr
, NULL
, NULL
,
1198 1, PPC_ELF_MACHINE
, 0, 0);
1199 if (payload_size
< 0) {
1201 * Hrm. No ELF image? Try a uImage, maybe someone is giving us an
1202 * ePAPR compliant kernel
1204 loadaddr
= LOAD_UIMAGE_LOADADDR_INVALID
;
1205 payload_size
= load_uimage(filename
, &bios_entry
, &loadaddr
, NULL
,
1207 if (payload_size
< 0) {
1208 error_report("could not load firmware '%s'", filename
);
1215 if (kernel_as_payload
) {
1216 kernel_base
= loadaddr
;
1217 kernel_size
= payload_size
;
1220 cur_base
= loadaddr
+ payload_size
;
1221 if (cur_base
< 32 * MiB
) {
1222 /* u-boot occupies memory up to 32MB, so load blobs above */
1223 cur_base
= 32 * MiB
;
1226 /* Load bare kernel only if no bios/u-boot has been provided */
1227 if (machine
->kernel_filename
&& !kernel_as_payload
) {
1228 kernel_base
= cur_base
;
1229 kernel_size
= load_image_targphys(machine
->kernel_filename
,
1231 machine
->ram_size
- cur_base
);
1232 if (kernel_size
< 0) {
1233 error_report("could not load kernel '%s'",
1234 machine
->kernel_filename
);
1238 cur_base
+= kernel_size
;
1242 if (machine
->initrd_filename
) {
1243 initrd_base
= (cur_base
+ INITRD_LOAD_PAD
) & ~INITRD_PAD_MASK
;
1244 initrd_size
= load_image_targphys(machine
->initrd_filename
, initrd_base
,
1245 machine
->ram_size
- initrd_base
);
1247 if (initrd_size
< 0) {
1248 error_report("could not load initial ram disk '%s'",
1249 machine
->initrd_filename
);
1253 cur_base
= initrd_base
+ initrd_size
;
1257 * Reserve space for dtb behind the kernel image because Linux has a bug
1258 * where it can only handle the dtb if it's within the first 64MB of where
1259 * <kernel> starts. dtb cannot not reach initrd_base because INITRD_LOAD_PAD
1260 * ensures enough space between kernel and initrd.
1262 dt_base
= (loadaddr
+ payload_size
+ DTC_LOAD_PAD
) & ~DTC_PAD_MASK
;
1263 if (dt_base
+ DTB_MAX_SIZE
> machine
->ram_size
) {
1264 error_report("not enough memory for device tree");
1268 dt_size
= ppce500_prep_device_tree(pms
, dt_base
,
1269 initrd_base
, initrd_size
,
1270 kernel_base
, kernel_size
);
1272 error_report("couldn't load device tree");
1275 assert(dt_size
< DTB_MAX_SIZE
);
1277 boot_info
->entry
= bios_entry
;
1278 boot_info
->dt_base
= dt_base
;
1279 boot_info
->dt_size
= dt_size
;
1282 static void e500_ccsr_initfn(Object
*obj
)
1284 PPCE500CCSRState
*ccsr
= CCSR(obj
);
1285 memory_region_init(&ccsr
->ccsr_space
, obj
, "e500-ccsr",
1286 MPC8544_CCSRBAR_SIZE
);
1289 static const TypeInfo e500_ccsr_info
= {
1291 .parent
= TYPE_SYS_BUS_DEVICE
,
1292 .instance_size
= sizeof(PPCE500CCSRState
),
1293 .instance_init
= e500_ccsr_initfn
,
1296 static const TypeInfo ppce500_info
= {
1297 .name
= TYPE_PPCE500_MACHINE
,
1298 .parent
= TYPE_MACHINE
,
1300 .instance_size
= sizeof(PPCE500MachineState
),
1301 .class_size
= sizeof(PPCE500MachineClass
),
1304 static void e500_register_types(void)
1306 type_register_static(&e500_ccsr_info
);
1307 type_register_static(&ppce500_info
);
1310 type_init(e500_register_types
)