hw/ppc/pnv_xscom.c

   1 /*
   2  * QEMU PowerPC PowerNV XSCOM bus
   3  *
   4  * Copyright (c) 2016, IBM Corporation.
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2.1 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include "qemu/osdep.h"
  21 #include "qemu/log.h"
  22 #include "qemu/module.h"
  23 #include "sysemu/hw_accel.h"
  24 #include "target/ppc/cpu.h"
  25 #include "hw/sysbus.h"
  26
  27 #include "hw/ppc/fdt.h"
  28 #include "hw/ppc/pnv.h"
  29 #include "hw/ppc/pnv_chip.h"
  30 #include "hw/ppc/pnv_xscom.h"
  31
  32 #include <libfdt.h>
  33
  34 /* PRD registers */
  35 #define PRD_P8_IPOLL_REG_MASK           0x01020013
  36 #define PRD_P8_IPOLL_REG_STATUS         0x01020014
  37 #define PRD_P9_IPOLL_REG_MASK           0x000F0033
  38 #define PRD_P9_IPOLL_REG_STATUS         0x000F0034
  39
  40 static void xscom_complete(CPUState *cs, uint64_t hmer_bits)
  41 {
  42     /*
  43      * TODO: When the read/write comes from the monitor, NULL is
  44      * passed for the cpu, and no CPU completion is generated.
  45      */
  46     if (cs) {
  47         /*
  48          * TODO: Need a CPU helper to set HMER, also handle generation
  49          * of HMIs
  50          */
  51         cpu_synchronize_state(cs);
  52         cpu_env(cs)->spr[SPR_HMER] |= hmer_bits;
  53     }
  54 }
  55
  56 static uint32_t pnv_xscom_pcba(PnvChip *chip, uint64_t addr)
  57 {
  58     return PNV_CHIP_GET_CLASS(chip)->xscom_pcba(chip, addr);
  59 }
  60
  61 static uint64_t xscom_read_default(PnvChip *chip, uint32_t pcba)
  62 {
  63     switch (pcba) {
  64     case 0xf000f:
  65         return PNV_CHIP_GET_CLASS(chip)->chip_cfam_id;
  66     case 0x18002:       /* ECID2 */
  67         return 0;
  68
  69     case 0x1010c00:     /* PIBAM FIR */
  70     case 0x1010c03:     /* PIBAM FIR MASK */
  71
  72         /* PRD registers */
  73     case PRD_P8_IPOLL_REG_MASK:
  74     case PRD_P8_IPOLL_REG_STATUS:
  75     case PRD_P9_IPOLL_REG_MASK:
  76     case PRD_P9_IPOLL_REG_STATUS:
  77
  78         /* P8 xscom reset */
  79     case 0x2020007:     /* ADU stuff, log register */
  80     case 0x2020009:     /* ADU stuff, error register */
  81     case 0x202000f:     /* ADU stuff, receive status register*/
  82         return 0;
  83     case 0x2013f01:     /* PBA stuff */
  84     case 0x2013f05:     /* PBA stuff */
  85         return 0;
  86     case 0x2013028:     /* CAPP stuff */
  87     case 0x201302a:     /* CAPP stuff */
  88     case 0x2013801:     /* CAPP stuff */
  89     case 0x2013802:     /* CAPP stuff */
  90
  91         /* P9 CAPP regs */
  92     case 0x2010841:
  93     case 0x2010842:
  94     case 0x201082a:
  95     case 0x2010828:
  96     case 0x4010841:
  97     case 0x4010842:
  98     case 0x401082a:
  99     case 0x4010828:
 100         return 0;
 101     default:
 102         return -1;
 103     }
 104 }
 105
 106 static bool xscom_write_default(PnvChip *chip, uint32_t pcba, uint64_t val)
 107 {
 108     /* We ignore writes to these */
 109     switch (pcba) {
 110     case 0xf000f:       /* chip id is RO */
 111     case 0x1010c00:     /* PIBAM FIR */
 112     case 0x1010c01:     /* PIBAM FIR */
 113     case 0x1010c02:     /* PIBAM FIR */
 114     case 0x1010c03:     /* PIBAM FIR MASK */
 115     case 0x1010c04:     /* PIBAM FIR MASK */
 116     case 0x1010c05:     /* PIBAM FIR MASK */
 117
 118         /* P8 xscom reset */
 119     case 0x2020007:     /* ADU stuff, log register */
 120     case 0x2020009:     /* ADU stuff, error register */
 121     case 0x202000f:     /* ADU stuff, receive status register*/
 122
 123     case 0x2013028:     /* CAPP stuff */
 124     case 0x201302a:     /* CAPP stuff */
 125     case 0x2013801:     /* CAPP stuff */
 126     case 0x2013802:     /* CAPP stuff */
 127
 128         /* P9 CAPP regs */
 129     case 0x2010841:
 130     case 0x2010842:
 131     case 0x201082a:
 132     case 0x2010828:
 133     case 0x4010841:
 134     case 0x4010842:
 135     case 0x401082a:
 136     case 0x4010828:
 137
 138         /* P8 PRD registers */
 139     case PRD_P8_IPOLL_REG_MASK:
 140     case PRD_P8_IPOLL_REG_STATUS:
 141     case PRD_P9_IPOLL_REG_MASK:
 142     case PRD_P9_IPOLL_REG_STATUS:
 143         return true;
 144     default:
 145         return false;
 146     }
 147 }
 148
 149 static uint64_t xscom_read(void *opaque, hwaddr addr, unsigned width)
 150 {
 151     PnvChip *chip = opaque;
 152     uint32_t pcba = pnv_xscom_pcba(chip, addr);
 153     uint64_t val = 0;
 154     MemTxResult result;
 155
 156     /* Handle some SCOMs here before dispatch */
 157     val = xscom_read_default(chip, pcba);
 158     if (val != -1) {
 159         goto complete;
 160     }
 161
 162     val = address_space_ldq(&chip->xscom_as, (uint64_t) pcba << 3,
 163                             MEMTXATTRS_UNSPECIFIED, &result);
 164     if (result != MEMTX_OK) {
 165         qemu_log_mask(LOG_GUEST_ERROR, "XSCOM read failed at @0x%"
 166                       HWADDR_PRIx " pcba=0x%08x\n", addr, pcba);
 167         xscom_complete(current_cpu, HMER_XSCOM_FAIL | HMER_XSCOM_DONE);
 168         return 0;
 169     }
 170
 171 complete:
 172     xscom_complete(current_cpu, HMER_XSCOM_DONE);
 173     return val;
 174 }
 175
 176 static void xscom_write(void *opaque, hwaddr addr, uint64_t val,
 177                         unsigned width)
 178 {
 179     PnvChip *chip = opaque;
 180     uint32_t pcba = pnv_xscom_pcba(chip, addr);
 181     MemTxResult result;
 182
 183     /* Handle some SCOMs here before dispatch */
 184     if (xscom_write_default(chip, pcba, val)) {
 185         goto complete;
 186     }
 187
 188     address_space_stq(&chip->xscom_as, (uint64_t) pcba << 3, val,
 189                       MEMTXATTRS_UNSPECIFIED, &result);
 190     if (result != MEMTX_OK) {
 191         qemu_log_mask(LOG_GUEST_ERROR, "XSCOM write failed at @0x%"
 192                       HWADDR_PRIx " pcba=0x%08x data=0x%" PRIx64 "\n",
 193                       addr, pcba, val);
 194         xscom_complete(current_cpu, HMER_XSCOM_FAIL | HMER_XSCOM_DONE);
 195         return;
 196     }
 197
 198 complete:
 199     xscom_complete(current_cpu, HMER_XSCOM_DONE);
 200 }
 201
 202 const MemoryRegionOps pnv_xscom_ops = {
 203     .read = xscom_read,
 204     .write = xscom_write,
 205     .valid.min_access_size = 8,
 206     .valid.max_access_size = 8,
 207     .impl.min_access_size = 8,
 208     .impl.max_access_size = 8,
 209     .endianness = DEVICE_BIG_ENDIAN,
 210 };
 211
 212 void pnv_xscom_init(PnvChip *chip, uint64_t size, hwaddr addr)
 213 {
 214     char *name;
 215
 216     name = g_strdup_printf("xscom-%x", chip->chip_id);
 217     memory_region_init_io(&chip->xscom_mmio, OBJECT(chip), &pnv_xscom_ops,
 218                           chip, name, size);
 219     memory_region_add_subregion(get_system_memory(), addr, &chip->xscom_mmio);
 220
 221     memory_region_init(&chip->xscom, OBJECT(chip), name, size);
 222     address_space_init(&chip->xscom_as, &chip->xscom, name);
 223     g_free(name);
 224 }
 225
 226 static const TypeInfo pnv_xscom_interface_info = {
 227     .name = TYPE_PNV_XSCOM_INTERFACE,
 228     .parent = TYPE_INTERFACE,
 229     .class_size = sizeof(PnvXScomInterfaceClass),
 230 };
 231
 232 static void pnv_xscom_register_types(void)
 233 {
 234     type_register_static(&pnv_xscom_interface_info);
 235 }
 236
 237 type_init(pnv_xscom_register_types)
 238
 239 typedef struct ForeachPopulateArgs {
 240     void *fdt;
 241     int xscom_offset;
 242 } ForeachPopulateArgs;
 243
 244 static int xscom_dt_child(Object *child, void *opaque)
 245 {
 246     if (object_dynamic_cast(child, TYPE_PNV_XSCOM_INTERFACE)) {
 247         ForeachPopulateArgs *args = opaque;
 248         PnvXScomInterface *xd = PNV_XSCOM_INTERFACE(child);
 249         PnvXScomInterfaceClass *xc = PNV_XSCOM_INTERFACE_GET_CLASS(xd);
 250
 251         /*
 252          * Only "realized" devices should be configured in the DT
 253          */
 254         if (xc->dt_xscom && DEVICE(child)->realized) {
 255             _FDT((xc->dt_xscom(xd, args->fdt, args->xscom_offset)));
 256         }
 257     }
 258     return 0;
 259 }
 260
 261 int pnv_dt_xscom(PnvChip *chip, void *fdt, int root_offset,
 262                  uint64_t xscom_base, uint64_t xscom_size,
 263                  const char *compat, int compat_size)
 264 {
 265     uint64_t reg[] = { xscom_base, xscom_size };
 266     int xscom_offset;
 267     ForeachPopulateArgs args;
 268     char *name;
 269
 270     name = g_strdup_printf("xscom@%" PRIx64, be64_to_cpu(reg[0]));
 271     xscom_offset = fdt_add_subnode(fdt, root_offset, name);
 272     _FDT(xscom_offset);
 273     g_free(name);
 274     _FDT((fdt_setprop_cell(fdt, xscom_offset, "ibm,chip-id", chip->chip_id)));
 275     /*
 276      * On P10, the xscom bus id has been deprecated and the chip id is
 277      * calculated from the "Primary topology table index". See skiboot.
 278      */
 279     _FDT((fdt_setprop_cell(fdt, xscom_offset, "ibm,primary-topology-index",
 280                            chip->chip_id)));
 281     _FDT((fdt_setprop_cell(fdt, xscom_offset, "#address-cells", 1)));
 282     _FDT((fdt_setprop_cell(fdt, xscom_offset, "#size-cells", 1)));
 283     _FDT((fdt_setprop(fdt, xscom_offset, "reg", reg, sizeof(reg))));
 284     _FDT((fdt_setprop(fdt, xscom_offset, "compatible", compat, compat_size)));
 285     _FDT((fdt_setprop(fdt, xscom_offset, "scom-controller", NULL, 0)));
 286     if (chip->chip_id == 0) {
 287         _FDT((fdt_setprop(fdt, xscom_offset, "primary", NULL, 0)));
 288     }
 289
 290     args.fdt = fdt;
 291     args.xscom_offset = xscom_offset;
 292
 293     /*
 294      * Loop on the whole object hierarchy to catch all
 295      * PnvXScomInterface objects which can lie a bit deeper than the
 296      * first layer.
 297      */
 298     object_child_foreach_recursive(OBJECT(chip), xscom_dt_child, &args);
 299     return 0;
 300 }
 301
 302 void pnv_xscom_add_subregion(PnvChip *chip, hwaddr offset, MemoryRegion *mr)
 303 {
 304     memory_region_add_subregion(&chip->xscom, offset << 3, mr);
 305 }
 306
 307 void pnv_xscom_region_init(MemoryRegion *mr,
 308                            Object *owner,
 309                            const MemoryRegionOps *ops,
 310                            void *opaque,
 311                            const char *name,
 312                            uint64_t size)
 313 {
 314     memory_region_init_io(mr, owner, ops, opaque, name, size << 3);
 315 }