hw/sparc/leon3.c

   1 /*
   2  * QEMU Leon3 System Emulator
   3  *
   4  * SPDX-License-Identifier: MIT
   5  *
   6  * Copyright (c) 2010-2024 AdaCore
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a copy
   9  * of this software and associated documentation files (the "Software"), to deal
  10  * in the Software without restriction, including without limitation the rights
  11  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  12  * copies of the Software, and to permit persons to whom the Software is
  13  * furnished to do so, subject to the following conditions:
  14  *
  15  * The above copyright notice and this permission notice shall be included in
  16  * all copies or substantial portions of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  19  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  20  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  21  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  22  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  23  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  24  * THE SOFTWARE.
  25  */
  26
  27 #include "qemu/osdep.h"
  28 #include "qemu/units.h"
  29 #include "qemu/error-report.h"
  30 #include "qapi/error.h"
  31 #include "qemu/datadir.h"
  32 #include "cpu.h"
  33 #include "hw/irq.h"
  34 #include "qemu/timer.h"
  35 #include "hw/ptimer.h"
  36 #include "hw/qdev-properties.h"
  37 #include "sysemu/sysemu.h"
  38 #include "sysemu/qtest.h"
  39 #include "sysemu/reset.h"
  40 #include "hw/boards.h"
  41 #include "hw/loader.h"
  42 #include "elf.h"
  43 #include "trace.h"
  44
  45 #include "hw/timer/grlib_gptimer.h"
  46 #include "hw/char/grlib_uart.h"
  47 #include "hw/intc/grlib_irqmp.h"
  48 #include "hw/misc/grlib_ahb_apb_pnp.h"
  49
  50 /* Default system clock.  */
  51 #define CPU_CLK (40 * 1000 * 1000)
  52
  53 #define LEON3_PROM_FILENAME "u-boot.bin"
  54 #define LEON3_PROM_OFFSET    (0x00000000)
  55 #define LEON3_RAM_OFFSET     (0x40000000)
  56
  57 #define MAX_CPUS  4
  58
  59 #define LEON3_UART_OFFSET  (0x80000100)
  60 #define LEON3_UART_IRQ     (3)
  61
  62 #define LEON3_IRQMP_OFFSET (0x80000200)
  63
  64 #define LEON3_TIMER_OFFSET (0x80000300)
  65 #define LEON3_TIMER_IRQ    (6)
  66 #define LEON3_TIMER_COUNT  (2)
  67
  68 #define LEON3_APB_PNP_OFFSET (0x800FF000)
  69 #define LEON3_AHB_PNP_OFFSET (0xFFFFF000)
  70
  71 typedef struct ResetData {
  72     struct CPUResetData {
  73         int id;
  74         SPARCCPU *cpu;
  75     } info[MAX_CPUS];
  76     uint32_t entry;             /* save kernel entry in case of reset */
  77 } ResetData;
  78
  79 static uint32_t *gen_store_u32(uint32_t *code, hwaddr addr, uint32_t val)
  80 {
  81     stl_p(code++, 0x82100000); /* mov %g0, %g1                */
  82     stl_p(code++, 0x84100000); /* mov %g0, %g2                */
  83     stl_p(code++, 0x03000000 +
  84       extract32(addr, 10, 22));
  85                                /* sethi %hi(addr), %g1        */
  86     stl_p(code++, 0x82106000 +
  87       extract32(addr, 0, 10));
  88                                /* or %g1, addr, %g1           */
  89     stl_p(code++, 0x05000000 +
  90       extract32(val, 10, 22));
  91                                /* sethi %hi(val), %g2         */
  92     stl_p(code++, 0x8410a000 +
  93       extract32(val, 0, 10));
  94                                /* or %g2, val, %g2            */
  95     stl_p(code++, 0xc4204000); /* st %g2, [ %g1 ]             */
  96
  97     return code;
  98 }
  99
 100 /*
 101  * When loading a kernel in RAM the machine is expected to be in a different
 102  * state (eg: initialized by the bootloader).  This little code reproduces
 103  * this behavior.  Also this code can be executed by the secondary cpus as
 104  * well since it looks at the %asr17 register before doing any
 105  * initialization, it allows to use the same reset address for all the
 106  * cpus.
 107  */
 108 static void write_bootloader(void *ptr, hwaddr kernel_addr)
 109 {
 110     uint32_t *p = ptr;
 111     uint32_t *sec_cpu_branch_p = NULL;
 112
 113     /* If we are running on a secondary CPU, jump directly to the kernel.  */
 114
 115     stl_p(p++, 0x85444000); /* rd %asr17, %g2      */
 116     stl_p(p++, 0x8530a01c); /* srl  %g2, 0x1c, %g2 */
 117     stl_p(p++, 0x80908000); /* tst  %g2            */
 118     /* Filled below.  */
 119     sec_cpu_branch_p = p;
 120     stl_p(p++, 0x0BADC0DE); /* bne xxx             */
 121     stl_p(p++, 0x01000000); /* nop */
 122
 123     /* Initialize the UARTs                                        */
 124     /* *UART_CONTROL = UART_RECEIVE_ENABLE | UART_TRANSMIT_ENABLE; */
 125     p = gen_store_u32(p, 0x80000108, 3);
 126
 127     /* Initialize the TIMER 0                                      */
 128     /* *GPTIMER_SCALER_RELOAD = 40 - 1;                            */
 129     p = gen_store_u32(p, 0x80000304, 39);
 130     /* *GPTIMER0_COUNTER_RELOAD = 0xFFFE;                          */
 131     p = gen_store_u32(p, 0x80000314, 0xFFFFFFFE);
 132     /* *GPTIMER0_CONFIG = GPTIMER_ENABLE | GPTIMER_RESTART;        */
 133     p = gen_store_u32(p, 0x80000318, 3);
 134
 135     /* Now, the relative branch above can be computed.  */
 136     stl_p(sec_cpu_branch_p, 0x12800000
 137           + (p - sec_cpu_branch_p));
 138
 139     /* JUMP to the entry point                                     */
 140     stl_p(p++, 0x82100000); /* mov %g0, %g1 */
 141     stl_p(p++, 0x03000000 + extract32(kernel_addr, 10, 22));
 142                             /* sethi %hi(kernel_addr), %g1 */
 143     stl_p(p++, 0x82106000 + extract32(kernel_addr, 0, 10));
 144                             /* or kernel_addr, %g1 */
 145     stl_p(p++, 0x81c04000); /* jmp  %g1 */
 146     stl_p(p++, 0x01000000); /* nop */
 147 }
 148
 149 static void leon3_cpu_reset(void *opaque)
 150 {
 151     struct CPUResetData *info = (struct CPUResetData *) opaque;
 152     int id = info->id;
 153     ResetData *s = container_of(info, ResetData, info[id]);
 154     CPUState *cpu = CPU(s->info[id].cpu);
 155     CPUSPARCState *env = cpu_env(cpu);
 156
 157     cpu_reset(cpu);
 158
 159     cpu->halted = cpu->cpu_index != 0;
 160     env->pc = s->entry;
 161     env->npc = s->entry + 4;
 162 }
 163
 164 static void leon3_cache_control_int(CPUSPARCState *env)
 165 {
 166     uint32_t state = 0;
 167
 168     if (env->cache_control & CACHE_CTRL_IF) {
 169         /* Instruction cache state */
 170         state = env->cache_control & CACHE_STATE_MASK;
 171         if (state == CACHE_ENABLED) {
 172             state = CACHE_FROZEN;
 173             trace_int_helper_icache_freeze();
 174         }
 175
 176         env->cache_control &= ~CACHE_STATE_MASK;
 177         env->cache_control |= state;
 178     }
 179
 180     if (env->cache_control & CACHE_CTRL_DF) {
 181         /* Data cache state */
 182         state = (env->cache_control >> 2) & CACHE_STATE_MASK;
 183         if (state == CACHE_ENABLED) {
 184             state = CACHE_FROZEN;
 185             trace_int_helper_dcache_freeze();
 186         }
 187
 188         env->cache_control &= ~(CACHE_STATE_MASK << 2);
 189         env->cache_control |= (state << 2);
 190     }
 191 }
 192
 193 static void leon3_irq_ack(CPUSPARCState *env, int intno)
 194 {
 195     CPUState *cpu = CPU(env_cpu(env));
 196     grlib_irqmp_ack(env->irq_manager, cpu->cpu_index, intno);
 197 }
 198
 199 /*
 200  * This device assumes that the incoming 'level' value on the
 201  * qemu_irq is the interrupt number, not just a simple 0/1 level.
 202  */
 203 static void leon3_set_pil_in(void *opaque, int n, int level)
 204 {
 205     DeviceState *cpu = opaque;
 206     CPUState *cs = CPU(cpu);
 207     CPUSPARCState *env = cpu_env(cs);
 208     uint32_t pil_in = level;
 209
 210     assert(env != NULL);
 211
 212     env->pil_in = pil_in;
 213
 214     if (env->pil_in && (env->interrupt_index == 0 ||
 215                         (env->interrupt_index & ~15) == TT_EXTINT)) {
 216         unsigned int i;
 217
 218         for (i = 15; i > 0; i--) {
 219             if (env->pil_in & (1 << i)) {
 220                 int old_interrupt = env->interrupt_index;
 221
 222                 env->interrupt_index = TT_EXTINT | i;
 223                 if (old_interrupt != env->interrupt_index) {
 224                     trace_leon3_set_irq(i);
 225                     cpu_interrupt(cs, CPU_INTERRUPT_HARD);
 226                 }
 227                 break;
 228             }
 229         }
 230     } else if (!env->pil_in && (env->interrupt_index & ~15) == TT_EXTINT) {
 231         trace_leon3_reset_irq(env->interrupt_index & 15);
 232         env->interrupt_index = 0;
 233         cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
 234     }
 235 }
 236
 237 static void leon3_start_cpu_async_work(CPUState *cpu, run_on_cpu_data data)
 238 {
 239     cpu->halted = 0;
 240 }
 241
 242 static void leon3_start_cpu(void *opaque, int n, int level)
 243 {
 244     DeviceState *cpu = opaque;
 245     CPUState *cs = CPU(cpu);
 246
 247     assert(level == 1);
 248     async_run_on_cpu(cs, leon3_start_cpu_async_work, RUN_ON_CPU_NULL);
 249 }
 250
 251 static void leon3_irq_manager(CPUSPARCState *env, int intno)
 252 {
 253     leon3_irq_ack(env, intno);
 254     leon3_cache_control_int(env);
 255 }
 256
 257 static void leon3_generic_hw_init(MachineState *machine)
 258 {
 259     ram_addr_t ram_size = machine->ram_size;
 260     const char *bios_name = machine->firmware ?: LEON3_PROM_FILENAME;
 261     const char *kernel_filename = machine->kernel_filename;
 262     SPARCCPU *cpu;
 263     CPUSPARCState   *env;
 264     MemoryRegion *address_space_mem = get_system_memory();
 265     MemoryRegion *prom = g_new(MemoryRegion, 1);
 266     int         ret;
 267     char       *filename;
 268     int         bios_size;
 269     int         prom_size;
 270     ResetData  *reset_info;
 271     DeviceState *dev, *irqmpdev;
 272     int i;
 273     AHBPnp *ahb_pnp;
 274     APBPnp *apb_pnp;
 275
 276     reset_info = g_malloc0(sizeof(ResetData));
 277
 278     for (i = 0; i < machine->smp.cpus; i++) {
 279         /* Init CPU */
 280         cpu = SPARC_CPU(object_new(machine->cpu_type));
 281         qdev_init_gpio_in_named(DEVICE(cpu), leon3_start_cpu, "start_cpu", 1);
 282         qdev_init_gpio_in_named(DEVICE(cpu), leon3_set_pil_in, "pil", 1);
 283         qdev_realize(DEVICE(cpu), NULL, &error_fatal);
 284         env = &cpu->env;
 285
 286         cpu_sparc_set_id(env, i);
 287
 288         /* Reset data */
 289         reset_info->info[i].id = i;
 290         reset_info->info[i].cpu = cpu;
 291         qemu_register_reset(leon3_cpu_reset, &reset_info->info[i]);
 292     }
 293
 294     ahb_pnp = GRLIB_AHB_PNP(qdev_new(TYPE_GRLIB_AHB_PNP));
 295     sysbus_realize_and_unref(SYS_BUS_DEVICE(ahb_pnp), &error_fatal);
 296     sysbus_mmio_map(SYS_BUS_DEVICE(ahb_pnp), 0, LEON3_AHB_PNP_OFFSET);
 297     grlib_ahb_pnp_add_entry(ahb_pnp, 0, 0, GRLIB_VENDOR_GAISLER,
 298                             GRLIB_LEON3_DEV, GRLIB_AHB_MASTER,
 299                             GRLIB_CPU_AREA);
 300
 301     apb_pnp = GRLIB_APB_PNP(qdev_new(TYPE_GRLIB_APB_PNP));
 302     sysbus_realize_and_unref(SYS_BUS_DEVICE(apb_pnp), &error_fatal);
 303     sysbus_mmio_map(SYS_BUS_DEVICE(apb_pnp), 0, LEON3_APB_PNP_OFFSET);
 304     grlib_ahb_pnp_add_entry(ahb_pnp, LEON3_APB_PNP_OFFSET, 0xFFF,
 305                             GRLIB_VENDOR_GAISLER, GRLIB_APBMST_DEV,
 306                             GRLIB_AHB_SLAVE, GRLIB_AHBMEM_AREA);
 307
 308     /* Allocate IRQ manager */
 309     irqmpdev = qdev_new(TYPE_GRLIB_IRQMP);
 310     object_property_set_int(OBJECT(irqmpdev), "ncpus", machine->smp.cpus,
 311                             &error_fatal);
 312     sysbus_realize_and_unref(SYS_BUS_DEVICE(irqmpdev), &error_fatal);
 313
 314     for (i = 0; i < machine->smp.cpus; i++) {
 315         cpu = reset_info->info[i].cpu;
 316         env = &cpu->env;
 317         qdev_connect_gpio_out_named(irqmpdev, "grlib-start-cpu", i,
 318                                     qdev_get_gpio_in_named(DEVICE(cpu),
 319                                                            "start_cpu", 0));
 320         qdev_connect_gpio_out_named(irqmpdev, "grlib-irq", i,
 321                                     qdev_get_gpio_in_named(DEVICE(cpu),
 322                                                            "pil", 0));
 323         env->irq_manager = irqmpdev;
 324         env->qemu_irq_ack = leon3_irq_manager;
 325     }
 326
 327     sysbus_mmio_map(SYS_BUS_DEVICE(irqmpdev), 0, LEON3_IRQMP_OFFSET);
 328     grlib_apb_pnp_add_entry(apb_pnp, LEON3_IRQMP_OFFSET, 0xFFF,
 329                             GRLIB_VENDOR_GAISLER, GRLIB_IRQMP_DEV,
 330                             2, 0, GRLIB_APBIO_AREA);
 331
 332     /* Allocate RAM */
 333     if (ram_size > 1 * GiB) {
 334         error_report("Too much memory for this machine: %" PRId64 "MB,"
 335                      " maximum 1G",
 336                      ram_size / MiB);
 337         exit(1);
 338     }
 339
 340     memory_region_add_subregion(address_space_mem, LEON3_RAM_OFFSET,
 341                                 machine->ram);
 342
 343     /* Allocate BIOS */
 344     prom_size = 8 * MiB;
 345     memory_region_init_rom(prom, NULL, "Leon3.bios", prom_size, &error_fatal);
 346     memory_region_add_subregion(address_space_mem, LEON3_PROM_OFFSET, prom);
 347
 348     /* Load boot prom */
 349     filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
 350
 351     if (filename) {
 352         bios_size = get_image_size(filename);
 353     } else {
 354         bios_size = -1;
 355     }
 356
 357     if (bios_size > prom_size) {
 358         error_report("could not load prom '%s': file too big", filename);
 359         exit(1);
 360     }
 361
 362     if (bios_size > 0) {
 363         ret = load_image_targphys(filename, LEON3_PROM_OFFSET, bios_size);
 364         if (ret < 0 || ret > prom_size) {
 365             error_report("could not load prom '%s'", filename);
 366             exit(1);
 367         }
 368     } else if (kernel_filename == NULL && !qtest_enabled()) {
 369         error_report("Can't read bios image '%s'", filename
 370                                                    ? filename
 371                                                    : LEON3_PROM_FILENAME);
 372         exit(1);
 373     }
 374     g_free(filename);
 375
 376     /* Can directly load an application. */
 377     if (kernel_filename != NULL) {
 378         long     kernel_size;
 379         uint64_t entry;
 380
 381         kernel_size = load_elf(kernel_filename, NULL, NULL, NULL,
 382                                &entry, NULL, NULL, NULL,
 383                                1 /* big endian */, EM_SPARC, 0, 0);
 384         if (kernel_size < 0) {
 385             kernel_size = load_uimage(kernel_filename, NULL, &entry,
 386                                       NULL, NULL, NULL);
 387         }
 388         if (kernel_size < 0) {
 389             error_report("could not load kernel '%s'", kernel_filename);
 390             exit(1);
 391         }
 392         if (bios_size <= 0) {
 393             /*
 394              * If there is no bios/monitor just start the application but put
 395              * the machine in an initialized state through a little
 396              * bootloader.
 397              */
 398             write_bootloader(memory_region_get_ram_ptr(prom), entry);
 399             reset_info->entry = LEON3_PROM_OFFSET;
 400             for (i = 0; i < machine->smp.cpus; i++) {
 401                 reset_info->info[i].cpu->env.pc = LEON3_PROM_OFFSET;
 402                 reset_info->info[i].cpu->env.npc = LEON3_PROM_OFFSET + 4;
 403             }
 404         }
 405     }
 406
 407     /* Allocate timers */
 408     dev = qdev_new(TYPE_GRLIB_GPTIMER);
 409     qdev_prop_set_uint32(dev, "nr-timers", LEON3_TIMER_COUNT);
 410     qdev_prop_set_uint32(dev, "frequency", CPU_CLK);
 411     qdev_prop_set_uint32(dev, "irq-line", LEON3_TIMER_IRQ);
 412     sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
 413
 414     sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, LEON3_TIMER_OFFSET);
 415     for (i = 0; i < LEON3_TIMER_COUNT; i++) {
 416         sysbus_connect_irq(SYS_BUS_DEVICE(dev), i,
 417                            qdev_get_gpio_in(irqmpdev, LEON3_TIMER_IRQ + i));
 418     }
 419
 420     grlib_apb_pnp_add_entry(apb_pnp, LEON3_TIMER_OFFSET, 0xFFF,
 421                             GRLIB_VENDOR_GAISLER, GRLIB_GPTIMER_DEV,
 422                             0, LEON3_TIMER_IRQ, GRLIB_APBIO_AREA);
 423
 424     /* Allocate uart */
 425     dev = qdev_new(TYPE_GRLIB_APB_UART);
 426     qdev_prop_set_chr(dev, "chrdev", serial_hd(0));
 427     sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
 428     sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, LEON3_UART_OFFSET);
 429     sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0,
 430                        qdev_get_gpio_in(irqmpdev, LEON3_UART_IRQ));
 431     grlib_apb_pnp_add_entry(apb_pnp, LEON3_UART_OFFSET, 0xFFF,
 432                             GRLIB_VENDOR_GAISLER, GRLIB_APBUART_DEV, 1,
 433                             LEON3_UART_IRQ, GRLIB_APBIO_AREA);
 434 }
 435
 436 static void leon3_generic_machine_init(MachineClass *mc)
 437 {
 438     mc->desc = "Leon-3 generic";
 439     mc->init = leon3_generic_hw_init;
 440     mc->default_cpu_type = SPARC_CPU_TYPE_NAME("LEON3");
 441     mc->default_ram_id = "leon3.ram";
 442     mc->max_cpus = MAX_CPUS;
 443 }
 444
 445 DEFINE_MACHINE("leon3_generic", leon3_generic_machine_init)