4 * Copyright (C) 2021 Avery Design Systems, Inc.
6 * This work is licensed under the terms of the GNU GPL, version 2 or later.
7 * See the COPYING file in the top-level directory.
13 #include "hw/cxl/cxl_pci.h"
14 #include "hw/pci/pcie_doe.h"
18 * Coherent Device Attribute Table (CDAT) Specification, Rev. 1.03, July. 2022
19 * Compute Express Link (CXL) Specification, Rev. 3.1, Aug. 2023
21 /* Table Access DOE - CXL r3.1 8.1.11 */
22 #define CXL_DOE_TABLE_ACCESS 2
23 #define CXL_DOE_PROTOCOL_CDAT ((CXL_DOE_TABLE_ACCESS << 16) | CXL_VENDOR_ID)
25 /* Read Entry - CXL r3.1 8.1.11.1 */
26 #define CXL_DOE_TAB_TYPE_CDAT 0
27 #define CXL_DOE_TAB_ENT_MAX 0xFFFF
29 /* Read Entry Request - CXL r3.1 8.1.11.1 Table 8-13 */
30 #define CXL_DOE_TAB_REQ 0
31 typedef struct CDATReq
{
35 uint16_t entry_handle
;
36 } QEMU_PACKED CDATReq
;
38 /* Read Entry Response - CXL r3.1 8.1.11.1 Table 8-14 */
39 #define CXL_DOE_TAB_RSP 0
40 typedef struct CDATRsp
{
44 uint16_t entry_handle
;
45 } QEMU_PACKED CDATRsp
;
47 /* CDAT Table Format - CDAT Table 1 */
48 #define CXL_CDAT_REV 2
49 typedef struct CDATTableHeader
{
55 } QEMU_PACKED CDATTableHeader
;
57 /* CDAT Structure Types - CDAT Table 2 */
61 CDAT_TYPE_DSMSCIS
= 2,
67 typedef struct CDATSubHeader
{
73 /* Device Scoped Memory Affinity Structure - CDAT Table 3 */
74 typedef struct CDATDsmas
{
78 #define CDAT_DSMAS_FLAG_NV (1 << 2)
79 #define CDAT_DSMAS_FLAG_SHAREABLE (1 << 3)
80 #define CDAT_DSMAS_FLAG_HW_COHERENT (1 << 4)
81 #define CDAT_DSMAS_FLAG_DYNAMIC_CAP (1 << 5)
86 QEMU_BUILD_BUG_ON(sizeof(CDATDsmas
) != 24);
88 /* Device Scoped Latency and Bandwidth Information Structure - CDAT Table 5 */
89 typedef struct CDATDslbis
{
92 /* Definitions of these fields refer directly to HMAT fields */
96 uint64_t entry_base_unit
;
100 QEMU_BUILD_BUG_ON(sizeof(CDATDslbis
) != 24);
102 /* Device Scoped Memory Side Cache Information Structure - CDAT Table 6 */
103 typedef struct CDATDsmscis
{
104 CDATSubHeader header
;
105 uint8_t DSMAS_handle
;
107 uint64_t memory_side_cache_size
;
108 uint32_t cache_attributes
;
109 } QEMU_PACKED CDATDsmscis
;
111 /* Device Scoped Initiator Structure - CDAT Table 7 */
112 typedef struct CDATDsis
{
113 CDATSubHeader header
;
117 } QEMU_PACKED CDATDsis
;
119 /* Device Scoped EFI Memory Type Structure - CDAT Table 8 */
120 typedef struct CDATDsemts
{
121 CDATSubHeader header
;
122 uint8_t DSMAS_handle
;
123 uint8_t EFI_memory_type_attr
;
128 QEMU_BUILD_BUG_ON(sizeof(CDATDsemts
) != 24);
130 /* Switch Scoped Latency and Bandwidth Information Structure - CDAT Table 9 */
131 typedef struct CDATSslbisHeader
{
132 CDATSubHeader header
;
135 uint64_t entry_base_unit
;
137 QEMU_BUILD_BUG_ON(sizeof(CDATSslbisHeader
) != 16);
139 #define CDAT_PORT_ID_USP 0x100
140 /* Switch Scoped Latency and Bandwidth Entry - CDAT Table 10 */
141 typedef struct CDATSslbe
{
144 uint16_t latency_bandwidth
;
147 QEMU_BUILD_BUG_ON(sizeof(CDATSslbe
) != 8);
149 typedef struct CDATSslbis
{
150 CDATSslbisHeader sslbis_header
;
154 typedef struct CDATEntry
{
159 typedef struct CDATObject
{
163 int (*build_cdat_table
)(CDATSubHeader
***cdat_table
, void *priv
);
164 void (*free_cdat_table
)(CDATSubHeader
**cdat_table
, int num
, void *priv
);
169 struct CDATSubHeader
**built_buf
;
172 #endif /* CXL_CDAT_H */